Updates to spice, PEX and PXI files as well as the addition of lvs reports
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report
new file mode 100644
index 0000000..a230e8c
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_0.sp ('sky130_fd_sc_lp__a2111o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice ('sky130_fd_sc_lp__a2111o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_0 sky130_fd_sc_lp__a2111o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice
index 280addd..c467f93 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_0.pex.spice
-* Created: Fri Aug 28 09:45:42 2020
+* Created: Wed Sep 2 09:16:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice
index f876d2c..1f71730 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_0.pxi.spice
-* Created: Fri Aug 28 09:45:42 2020
+* Created: Wed Sep 2 09:16:07 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_0%A_80_159# N_A_80_159#_M1001_d N_A_80_159#_M1004_d
+ N_A_80_159#_M1002_s N_A_80_159#_c_91_n N_A_80_159#_M1005_g N_A_80_159#_M1008_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice
index 44f5ca5..f263071 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_0.spice
-* Created: Fri Aug 28 09:45:42 2020
+* Created: Wed Sep 2 09:16:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report
new file mode 100644
index 0000000..856024a
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_1.sp ('sky130_fd_sc_lp__a2111o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice ('sky130_fd_sc_lp__a2111o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_1 sky130_fd_sc_lp__a2111o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice
index ada3cb7..69438ba 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_1.pex.spice
-* Created: Fri Aug 28 09:45:49 2020
+* Created: Wed Sep 2 09:16:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice
index 3d67aea..f80dc05 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_1.pxi.spice
-* Created: Fri Aug 28 09:45:49 2020
+* Created: Wed Sep 2 09:16:13 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_1%A_105_239# N_A_105_239#_M1011_d
+ N_A_105_239#_M1003_d N_A_105_239#_M1009_s N_A_105_239#_M1008_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice
index fc9ff88..6b600f4 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_1.spice
-* Created: Fri Aug 28 09:45:49 2020
+* Created: Wed Sep 2 09:16:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report
new file mode 100644
index 0000000..d12ce91
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_2.sp ('sky130_fd_sc_lp__a2111o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice ('sky130_fd_sc_lp__a2111o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_2 sky130_fd_sc_lp__a2111o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice
index abfcee8..f8fa10d 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_2.pex.spice
-* Created: Fri Aug 28 09:45:57 2020
+* Created: Wed Sep 2 09:16:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice
index 1ca03ae..e36a20b 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_2.pxi.spice
-* Created: Fri Aug 28 09:45:57 2020
+* Created: Wed Sep 2 09:16:19 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_2%A_86_275# N_A_86_275#_M1004_d N_A_86_275#_M1000_d
+ N_A_86_275#_M1008_s N_A_86_275#_M1005_g N_A_86_275#_c_75_n N_A_86_275#_M1003_g
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice
index 7b9be4e..019a11c 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_2.spice
-* Created: Fri Aug 28 09:45:57 2020
+* Created: Wed Sep 2 09:16:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report
new file mode 100644
index 0000000..e70d48a
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_4.sp ('sky130_fd_sc_lp__a2111o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice ('sky130_fd_sc_lp__a2111o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_4 sky130_fd_sc_lp__a2111o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice
index 0bb936e..6cd5993 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_4.pex.spice
-* Created: Fri Aug 28 09:46:04 2020
+* Created: Wed Sep 2 09:16:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice
index 7faa317..f05d32d 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_4.pxi.spice
-* Created: Fri Aug 28 09:46:04 2020
+* Created: Wed Sep 2 09:16:25 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_4%D1 N_D1_M1006_g N_D1_M1004_g N_D1_c_144_n
+ N_D1_M1018_g N_D1_M1022_g N_D1_c_147_n N_D1_c_148_n N_D1_c_149_n D1
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice
index 5d4e246..55ba8c1 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_4.spice
-* Created: Fri Aug 28 09:46:04 2020
+* Created: Wed Sep 2 09:16:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report
new file mode 100644
index 0000000..391ddeb
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_lp.sp ('sky130_fd_sc_lp__a2111o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice ('sky130_fd_sc_lp__a2111o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_lp sky130_fd_sc_lp__a2111o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice
index 63d6c14..ec8ed31 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_lp.pex.spice
-* Created: Fri Aug 28 09:46:11 2020
+* Created: Wed Sep 2 09:16:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice
index 7421f62..b527171 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_lp.pxi.spice
-* Created: Fri Aug 28 09:46:11 2020
+* Created: Wed Sep 2 09:16:31 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_LP%D1 N_D1_M1001_g N_D1_M1000_g N_D1_c_106_n
+ N_D1_M1014_g N_D1_c_108_n N_D1_c_109_n D1 D1 N_D1_c_110_n N_D1_c_111_n
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice
index b1d3800..b27f0f0 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_lp.spice
-* Created: Fri Aug 28 09:46:11 2020
+* Created: Wed Sep 2 09:16:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report
new file mode 100644
index 0000000..de89644
--- /dev/null
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111o_m.sp ('sky130_fd_sc_lp__a2111o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice ('sky130_fd_sc_lp__a2111o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111o_m sky130_fd_sc_lp__a2111o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice
index b254502..ea5746a 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_m.pex.spice
-* Created: Fri Aug 28 09:46:18 2020
+* Created: Wed Sep 2 09:16:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice
index 5ec81f4..e6aa4c3 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_m.pxi.spice
-* Created: Fri Aug 28 09:46:18 2020
+* Created: Wed Sep 2 09:16:37 2020
*
x_PM_SKY130_FD_SC_LP__A2111O_M%A_85_21# N_A_85_21#_M1001_d N_A_85_21#_M1009_d
+ N_A_85_21#_M1011_s N_A_85_21#_M1010_g N_A_85_21#_M1007_g N_A_85_21#_c_85_n
diff --git a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice
index da9ffea..6dd6a14 100644
--- a/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice
+++ b/cells/a2111o/sky130_fd_sc_lp__a2111o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111o_m.spice
-* Created: Fri Aug 28 09:46:18 2020
+* Created: Wed Sep 2 09:16:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report
new file mode 100644
index 0000000..c71c075
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_0.sp ('sky130_fd_sc_lp__a2111oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice ('sky130_fd_sc_lp__a2111oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_0 sky130_fd_sc_lp__a2111oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice
index 51c4daa..7149f12 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_0.pex.spice
-* Created: Fri Aug 28 09:46:26 2020
+* Created: Wed Sep 2 09:16:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice
index 6dc07f9..8463d07 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_0.pxi.spice
-* Created: Fri Aug 28 09:46:26 2020
+* Created: Wed Sep 2 09:16:43 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_0%D1 N_D1_c_79_n N_D1_c_80_n N_D1_c_81_n
+ N_D1_c_87_n N_D1_c_88_n N_D1_M1002_g N_D1_c_89_n N_D1_M1003_g N_D1_c_83_n D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice
index 9733d69..2b2cedb 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_0.spice
-* Created: Fri Aug 28 09:46:26 2020
+* Created: Wed Sep 2 09:16:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report
new file mode 100644
index 0000000..b4571a7
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_1.sp ('sky130_fd_sc_lp__a2111oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice ('sky130_fd_sc_lp__a2111oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_1 sky130_fd_sc_lp__a2111oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice
index 0d76f95..0caa1d3 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_1.pex.spice
-* Created: Fri Aug 28 09:46:33 2020
+* Created: Wed Sep 2 09:16:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice
index 1e5209d..2cef549 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_1.pxi.spice
-* Created: Fri Aug 28 09:46:33 2020
+* Created: Wed Sep 2 09:16:49 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_1%D1 N_D1_M1002_g N_D1_M1005_g D1 D1 D1 D1
+ N_D1_c_50_n N_D1_c_51_n PM_SKY130_FD_SC_LP__A2111OI_1%D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice
index 576c37a..f87553a 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_1.spice
-* Created: Fri Aug 28 09:46:33 2020
+* Created: Wed Sep 2 09:16:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report
new file mode 100644
index 0000000..8017042
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_2.sp ('sky130_fd_sc_lp__a2111oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice ('sky130_fd_sc_lp__a2111oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_2 sky130_fd_sc_lp__a2111oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 D1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice
index 8869209..2428060 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_2.pex.spice
-* Created: Fri Aug 28 09:46:49 2020
+* Created: Wed Sep 2 09:16:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice
index 68a0244..556e51e 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_2.pxi.spice
-* Created: Fri Aug 28 09:46:49 2020
+* Created: Wed Sep 2 09:16:56 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_2%C1 N_C1_M1012_g N_C1_M1005_g N_C1_M1008_g
+ N_C1_M1017_g N_C1_c_104_n N_C1_c_105_n C1 N_C1_c_106_n N_C1_c_107_n
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice
index fb767b5..4896f2c 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_2.spice
-* Created: Fri Aug 28 09:46:49 2020
+* Created: Wed Sep 2 09:16:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report
new file mode 100644
index 0000000..cba9c4a
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_4.sp ('sky130_fd_sc_lp__a2111oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice ('sky130_fd_sc_lp__a2111oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:16:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_4 sky130_fd_sc_lp__a2111oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice
index 137420f..ce9671b 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_4.pex.spice
-* Created: Fri Aug 28 09:46:57 2020
+* Created: Wed Sep 2 09:17:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice
index 0fe93a7..7564827 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_4.pxi.spice
-* Created: Fri Aug 28 09:46:57 2020
+* Created: Wed Sep 2 09:17:02 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_4%D1 N_D1_c_153_n N_D1_M1014_g N_D1_M1000_g
+ N_D1_c_155_n N_D1_M1022_g N_D1_M1016_g N_D1_c_157_n N_D1_M1023_g N_D1_M1027_g
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice
index 109385f..683780c 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_4.spice
-* Created: Fri Aug 28 09:46:57 2020
+* Created: Wed Sep 2 09:17:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report
new file mode 100644
index 0000000..cebf00f
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_lp.sp ('sky130_fd_sc_lp__a2111oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice ('sky130_fd_sc_lp__a2111oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_lp sky130_fd_sc_lp__a2111oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 4 4 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 D1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice
index ee9e26a..9a9887c 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_lp.pex.spice
-* Created: Fri Aug 28 09:47:04 2020
+* Created: Wed Sep 2 09:17:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice
index ecb6b28..76033e6 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_lp.pxi.spice
-* Created: Fri Aug 28 09:47:04 2020
+* Created: Wed Sep 2 09:17:08 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_LP%A1 N_A1_M1006_g N_A1_M1008_g N_A1_c_89_n
+ N_A1_c_94_n A1 A1 N_A1_c_91_n PM_SKY130_FD_SC_LP__A2111OI_LP%A1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice
index a64cb51..1cc85c0 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_lp.spice
-* Created: Fri Aug 28 09:47:04 2020
+* Created: Wed Sep 2 09:17:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report
new file mode 100644
index 0000000..0c3a473
--- /dev/null
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2111oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2111oi_m.sp ('sky130_fd_sc_lp__a2111oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice ('sky130_fd_sc_lp__a2111oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2111oi_m sky130_fd_sc_lp__a2111oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2111oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a2111oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice
index a1b65c4..6611614 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_m.pex.spice
-* Created: Fri Aug 28 09:47:11 2020
+* Created: Wed Sep 2 09:17:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice
index 32d8a88..1bdc184 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_m.pxi.spice
-* Created: Fri Aug 28 09:47:11 2020
+* Created: Wed Sep 2 09:17:14 2020
*
x_PM_SKY130_FD_SC_LP__A2111OI_M%D1 N_D1_M1009_g N_D1_M1000_g N_D1_c_71_n
+ N_D1_c_76_n D1 D1 D1 D1 D1 N_D1_c_73_n PM_SKY130_FD_SC_LP__A2111OI_M%D1
diff --git a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice
index 1d4d597..6245294 100644
--- a/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice
+++ b/cells/a2111oi/sky130_fd_sc_lp__a2111oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2111oi_m.spice
-* Created: Fri Aug 28 09:47:11 2020
+* Created: Wed Sep 2 09:17:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report
new file mode 100644
index 0000000..9aff253
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_0.sp ('sky130_fd_sc_lp__a211o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_0.spice ('sky130_fd_sc_lp__a211o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_0 sky130_fd_sc_lp__a211o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice
index f651e13..576c430 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_0.pex.spice
-* Created: Fri Aug 28 09:47:18 2020
+* Created: Wed Sep 2 09:17:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice
index 0915280..5aafaca 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_0.pxi.spice
-* Created: Fri Aug 28 09:47:18 2020
+* Created: Wed Sep 2 09:17:21 2020
*
x_PM_SKY130_FD_SC_LP__A211O_0%A_80_172# N_A_80_172#_M1002_d N_A_80_172#_M1000_d
+ N_A_80_172#_M1005_d N_A_80_172#_c_78_n N_A_80_172#_M1009_g N_A_80_172#_M1007_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_0.spice b/cells/a211o/sky130_fd_sc_lp__a211o_0.spice
index db2354f..1480e73 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_0.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_0.spice
-* Created: Fri Aug 28 09:47:18 2020
+* Created: Wed Sep 2 09:17:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report
new file mode 100644
index 0000000..40a77a9
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_1.sp ('sky130_fd_sc_lp__a211o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_1.spice ('sky130_fd_sc_lp__a211o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_1 sky130_fd_sc_lp__a211o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice
index fc28250..7a3ca24 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_1.pex.spice
-* Created: Fri Aug 28 09:47:25 2020
+* Created: Wed Sep 2 09:17:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice
index f8e4b5a..7f5efd6 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_1.pxi.spice
-* Created: Fri Aug 28 09:47:25 2020
+* Created: Wed Sep 2 09:17:27 2020
*
x_PM_SKY130_FD_SC_LP__A211O_1%A_80_237# N_A_80_237#_M1001_d N_A_80_237#_M1007_d
+ N_A_80_237#_M1000_d N_A_80_237#_M1008_g N_A_80_237#_c_53_n N_A_80_237#_M1009_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_1.spice b/cells/a211o/sky130_fd_sc_lp__a211o_1.spice
index 3e7c9fa..c1b75a9 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_1.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_1.spice
-* Created: Fri Aug 28 09:47:25 2020
+* Created: Wed Sep 2 09:17:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report
new file mode 100644
index 0000000..3b043ea
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_2.sp ('sky130_fd_sc_lp__a211o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_2.spice ('sky130_fd_sc_lp__a211o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_2 sky130_fd_sc_lp__a211o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice
index 5a398a5..4657dfd 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_2.pex.spice
-* Created: Fri Aug 28 09:47:32 2020
+* Created: Wed Sep 2 09:17:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice
index 2f3e0ed..7263702 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_2.pxi.spice
-* Created: Fri Aug 28 09:47:32 2020
+* Created: Wed Sep 2 09:17:33 2020
*
x_PM_SKY130_FD_SC_LP__A211O_2%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1001_d
+ N_A_80_21#_M1006_d N_A_80_21#_M1002_g N_A_80_21#_M1003_g N_A_80_21#_M1004_g
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_2.spice b/cells/a211o/sky130_fd_sc_lp__a211o_2.spice
index dce0f8c..9793815 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_2.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_2.spice
-* Created: Fri Aug 28 09:47:32 2020
+* Created: Wed Sep 2 09:17:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report
new file mode 100644
index 0000000..6e7d3f6
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_4.sp ('sky130_fd_sc_lp__a211o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_4.spice ('sky130_fd_sc_lp__a211o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_4 sky130_fd_sc_lp__a211o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 C1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice
index 959fa7d..bbbae42 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_4.pex.spice
-* Created: Fri Aug 28 09:47:39 2020
+* Created: Wed Sep 2 09:17:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice
index c3fd52a..48641b4 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_4.pxi.spice
-* Created: Fri Aug 28 09:47:39 2020
+* Created: Wed Sep 2 09:17:39 2020
*
x_PM_SKY130_FD_SC_LP__A211O_4%A_103_263# N_A_103_263#_M1002_s
+ N_A_103_263#_M1019_s N_A_103_263#_M1009_s N_A_103_263#_M1000_s
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_4.spice b/cells/a211o/sky130_fd_sc_lp__a211o_4.spice
index cc601e8..f939240 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_4.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_4.spice
-* Created: Fri Aug 28 09:47:39 2020
+* Created: Wed Sep 2 09:17:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report
new file mode 100644
index 0000000..81e1fcd
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_lp.sp ('sky130_fd_sc_lp__a211o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice ('sky130_fd_sc_lp__a211o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_lp sky130_fd_sc_lp__a211o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice
index 3103609..6c54253 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_lp.pex.spice
-* Created: Fri Aug 28 09:47:55 2020
+* Created: Wed Sep 2 09:17:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice
index 2e9257c..7f2760f 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_lp.pxi.spice
-* Created: Fri Aug 28 09:47:55 2020
+* Created: Wed Sep 2 09:17:45 2020
*
x_PM_SKY130_FD_SC_LP__A211O_LP%A1 N_A1_c_70_n N_A1_M1000_g N_A1_M1001_g A1 A1
+ N_A1_c_72_n PM_SKY130_FD_SC_LP__A211O_LP%A1
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice b/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice
index ec8a61e..4e9e02a 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_lp.spice
-* Created: Fri Aug 28 09:47:55 2020
+* Created: Wed Sep 2 09:17:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report b/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report
new file mode 100644
index 0000000..592b5cb
--- /dev/null
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211o_m.sp ('sky130_fd_sc_lp__a211o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211o/sky130_fd_sc_lp__a211o_m.spice ('sky130_fd_sc_lp__a211o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211o_m sky130_fd_sc_lp__a211o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a211o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice
index ed94b31..eb4d405 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_m.pex.spice
-* Created: Fri Aug 28 09:48:02 2020
+* Created: Wed Sep 2 09:17:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice
index fed2e99..598b592 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_m.pxi.spice
-* Created: Fri Aug 28 09:48:02 2020
+* Created: Wed Sep 2 09:17:51 2020
*
x_PM_SKY130_FD_SC_LP__A211O_M%A2 N_A2_M1002_g N_A2_M1001_g A2 N_A2_c_65_n
+ N_A2_c_66_n PM_SKY130_FD_SC_LP__A211O_M%A2
diff --git a/cells/a211o/sky130_fd_sc_lp__a211o_m.spice b/cells/a211o/sky130_fd_sc_lp__a211o_m.spice
index a158432..040f72b 100644
--- a/cells/a211o/sky130_fd_sc_lp__a211o_m.spice
+++ b/cells/a211o/sky130_fd_sc_lp__a211o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211o_m.spice
-* Created: Fri Aug 28 09:48:02 2020
+* Created: Wed Sep 2 09:17:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report
new file mode 100644
index 0000000..66e8224
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_0.sp ('sky130_fd_sc_lp__a211oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice ('sky130_fd_sc_lp__a211oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:17:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_0 sky130_fd_sc_lp__a211oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice
index 7b8568e..462f484 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_0.pex.spice
-* Created: Fri Aug 28 09:48:09 2020
+* Created: Wed Sep 2 09:17:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice
index d9bca78..8cd69e5 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_0.pxi.spice
-* Created: Fri Aug 28 09:48:09 2020
+* Created: Wed Sep 2 09:17:57 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_0%A2 N_A2_c_65_n N_A2_c_66_n N_A2_c_67_n
+ N_A2_M1003_g N_A2_M1000_g N_A2_c_69_n N_A2_c_74_n A2 A2 A2 N_A2_c_71_n
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice
index d5d7524..df29f29 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_0.spice
-* Created: Fri Aug 28 09:48:09 2020
+* Created: Wed Sep 2 09:17:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report
new file mode 100644
index 0000000..7da964a
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_1.sp ('sky130_fd_sc_lp__a211oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice ('sky130_fd_sc_lp__a211oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_1 sky130_fd_sc_lp__a211oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice
index e474c87..4e39484 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_1.pex.spice
-* Created: Fri Aug 28 09:48:16 2020
+* Created: Wed Sep 2 09:18:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice
index a756d78..4583949 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_1.pxi.spice
-* Created: Fri Aug 28 09:48:16 2020
+* Created: Wed Sep 2 09:18:04 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_1%A2 N_A2_c_48_n N_A2_M1002_g N_A2_M1006_g A2 A2
+ N_A2_c_51_n PM_SKY130_FD_SC_LP__A211OI_1%A2
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice
index 5c2e938..71dec83 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_1.spice
-* Created: Fri Aug 28 09:48:16 2020
+* Created: Wed Sep 2 09:18:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report
new file mode 100644
index 0000000..541549e
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_2.sp ('sky130_fd_sc_lp__a211oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice ('sky130_fd_sc_lp__a211oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_2 sky130_fd_sc_lp__a211oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice
index 75fa200..c444351 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_2.pex.spice
-* Created: Fri Aug 28 09:48:24 2020
+* Created: Wed Sep 2 09:18:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice
index 25bb241..e97fc1f 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_2.pxi.spice
-* Created: Fri Aug 28 09:48:24 2020
+* Created: Wed Sep 2 09:18:10 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_2%C1 N_C1_c_76_n N_C1_M1012_g N_C1_M1008_g
+ N_C1_c_78_n N_C1_M1013_g N_C1_M1014_g C1 C1 N_C1_c_81_n
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice
index 8016af1..ce6a2de 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_2.spice
-* Created: Fri Aug 28 09:48:24 2020
+* Created: Wed Sep 2 09:18:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report
new file mode 100644
index 0000000..f24248f
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_4.sp ('sky130_fd_sc_lp__a211oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice ('sky130_fd_sc_lp__a211oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_4 sky130_fd_sc_lp__a211oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice
index 68730e4..29a83e2 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_4.pex.spice
-* Created: Fri Aug 28 09:48:31 2020
+* Created: Wed Sep 2 09:18:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice
index 0b94f0d..5d98ac7 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_4.pxi.spice
-* Created: Fri Aug 28 09:48:31 2020
+* Created: Wed Sep 2 09:18:16 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_4%A2 N_A2_M1006_g N_A2_c_126_n N_A2_M1004_g
+ N_A2_M1008_g N_A2_c_127_n N_A2_M1009_g N_A2_M1023_g N_A2_c_128_n N_A2_M1012_g
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice
index 9b97d01..9e6f2f2 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_4.spice
-* Created: Fri Aug 28 09:48:31 2020
+* Created: Wed Sep 2 09:18:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report
new file mode 100644
index 0000000..1e70444
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_lp.sp ('sky130_fd_sc_lp__a211oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice ('sky130_fd_sc_lp__a211oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_lp sky130_fd_sc_lp__a211oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice
index 3a4bd50..fb0aadc 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_lp.pex.spice
-* Created: Fri Aug 28 09:48:38 2020
+* Created: Wed Sep 2 09:18:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice
index dd37806..823ebef 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_lp.pxi.spice
-* Created: Fri Aug 28 09:48:38 2020
+* Created: Wed Sep 2 09:18:22 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_LP%C1 N_C1_c_62_n N_C1_M1008_g N_C1_c_63_n
+ N_C1_M1004_g N_C1_c_64_n N_C1_c_65_n N_C1_M1005_g N_C1_c_66_n N_C1_c_72_n C1
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice
index a76076e..9bca1bb 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_lp.spice
-* Created: Fri Aug 28 09:48:38 2020
+* Created: Wed Sep 2 09:18:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report
new file mode 100644
index 0000000..ada9440
--- /dev/null
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a211oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a211oi_m.sp ('sky130_fd_sc_lp__a211oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice ('sky130_fd_sc_lp__a211oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a211oi_m sky130_fd_sc_lp__a211oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a211oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a211oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice
index aceb4c4..29c8fcd 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_m.pex.spice
-* Created: Fri Aug 28 09:48:45 2020
+* Created: Wed Sep 2 09:18:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice
index 69f73c4..8551cfd 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_m.pxi.spice
-* Created: Fri Aug 28 09:48:45 2020
+* Created: Wed Sep 2 09:18:28 2020
*
x_PM_SKY130_FD_SC_LP__A211OI_M%A2 N_A2_M1005_g N_A2_M1004_g N_A2_c_48_n
+ N_A2_c_49_n N_A2_c_50_n A2 A2 N_A2_c_51_n PM_SKY130_FD_SC_LP__A211OI_M%A2
diff --git a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice
index 99e3d7b..e32c3ed 100644
--- a/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice
+++ b/cells/a211oi/sky130_fd_sc_lp__a211oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a211oi_m.spice
-* Created: Fri Aug 28 09:48:45 2020
+* Created: Wed Sep 2 09:18:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report
new file mode 100644
index 0000000..e9693c0
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_0.sp ('sky130_fd_sc_lp__a21bo_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice ('sky130_fd_sc_lp__a21bo_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_0 sky130_fd_sc_lp__a21bo_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice
index 784fdca..727ace4 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_0.pex.spice
-* Created: Fri Aug 28 09:49:02 2020
+* Created: Wed Sep 2 09:18:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice
index 291bc3e..b7faa0c 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_0.pxi.spice
-* Created: Fri Aug 28 09:49:02 2020
+* Created: Wed Sep 2 09:18:35 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_0%A_72_212# N_A_72_212#_M1004_d N_A_72_212#_M1001_s
+ N_A_72_212#_M1002_g N_A_72_212#_M1007_g N_A_72_212#_c_82_n N_A_72_212#_c_83_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice
index 0b8ff52..51042d0 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_0.spice
-* Created: Fri Aug 28 09:49:02 2020
+* Created: Wed Sep 2 09:18:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report
new file mode 100644
index 0000000..ce46e3a
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_1.sp ('sky130_fd_sc_lp__a21bo_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice ('sky130_fd_sc_lp__a21bo_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_1 sky130_fd_sc_lp__a21bo_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice
index 367af1c..3d12ea9 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_1.pex.spice
-* Created: Fri Aug 28 09:49:09 2020
+* Created: Wed Sep 2 09:18:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice
index 74b83b5..dd5610d 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_1.pxi.spice
-* Created: Fri Aug 28 09:49:09 2020
+* Created: Wed Sep 2 09:18:41 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_1%A_80_43# N_A_80_43#_M1007_d N_A_80_43#_M1001_s
+ N_A_80_43#_M1005_g N_A_80_43#_M1009_g N_A_80_43#_c_76_n N_A_80_43#_c_70_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice
index 3ba16e6..2b4b7bc 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_1.spice
-* Created: Fri Aug 28 09:49:09 2020
+* Created: Wed Sep 2 09:18:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report
new file mode 100644
index 0000000..5d29cf5
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_2.sp ('sky130_fd_sc_lp__a21bo_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice ('sky130_fd_sc_lp__a21bo_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_2 sky130_fd_sc_lp__a21bo_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice
index 7e37a3d..d8ca4c1 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_2.pex.spice
-* Created: Fri Aug 28 09:49:16 2020
+* Created: Wed Sep 2 09:18:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice
index b6469e1..14a4374 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_2.pxi.spice
-* Created: Fri Aug 28 09:49:16 2020
+* Created: Wed Sep 2 09:18:47 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_2%A_22_259# N_A_22_259#_M1006_d N_A_22_259#_M1010_s
+ N_A_22_259#_c_73_n N_A_22_259#_M1000_g N_A_22_259#_M1001_g N_A_22_259#_c_75_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice
index e4bdb17..ef123a8 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_2.spice
-* Created: Fri Aug 28 09:49:16 2020
+* Created: Wed Sep 2 09:18:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report
new file mode 100644
index 0000000..313d636
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_4.sp ('sky130_fd_sc_lp__a21bo_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice ('sky130_fd_sc_lp__a21bo_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_4 sky130_fd_sc_lp__a21bo_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice
index f43e40b..f450101 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_4.pex.spice
-* Created: Fri Aug 28 09:49:23 2020
+* Created: Wed Sep 2 09:18:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice
index 4ade7ff..09ebbd9 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_4.pxi.spice
-* Created: Fri Aug 28 09:49:23 2020
+* Created: Wed Sep 2 09:18:53 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_4%B1_N N_B1_N_M1013_g N_B1_N_M1021_g B1_N B1_N
+ N_B1_N_c_116_n PM_SKY130_FD_SC_LP__A21BO_4%B1_N
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice
index 71f8488..f7538bc 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_4.spice
-* Created: Fri Aug 28 09:49:23 2020
+* Created: Wed Sep 2 09:18:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report
new file mode 100644
index 0000000..24d7a08
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_lp.sp ('sky130_fd_sc_lp__a21bo_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice ('sky130_fd_sc_lp__a21bo_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:18:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_lp sky130_fd_sc_lp__a21bo_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1_N X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice
index cc43515..a3d404b 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_lp.pex.spice
-* Created: Fri Aug 28 09:49:30 2020
+* Created: Wed Sep 2 09:18:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice
index 22461bc..12f344b 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_lp.pxi.spice
-* Created: Fri Aug 28 09:49:30 2020
+* Created: Wed Sep 2 09:18:59 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_LP%A_84_29# N_A_84_29#_M1009_d N_A_84_29#_M1006_d
+ N_A_84_29#_M1007_g N_A_84_29#_c_82_n N_A_84_29#_M1004_g N_A_84_29#_M1001_g
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice
index 8348461..44cc91d 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_lp.spice
-* Created: Fri Aug 28 09:49:30 2020
+* Created: Wed Sep 2 09:18:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report
new file mode 100644
index 0000000..26ba299
--- /dev/null
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21bo_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21bo_m.sp ('sky130_fd_sc_lp__a21bo_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice ('sky130_fd_sc_lp__a21bo_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21bo_m sky130_fd_sc_lp__a21bo_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21bo_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a21bo_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice
index 8e1dc6b..c860f10 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_m.pex.spice
-* Created: Fri Aug 28 09:49:38 2020
+* Created: Wed Sep 2 09:19:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice
index aed3e6c..f6e473c 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_m.pxi.spice
-* Created: Fri Aug 28 09:49:38 2020
+* Created: Wed Sep 2 09:19:05 2020
*
x_PM_SKY130_FD_SC_LP__A21BO_M%A_80_72# N_A_80_72#_M1000_d N_A_80_72#_M1003_s
+ N_A_80_72#_M1002_g N_A_80_72#_c_87_n N_A_80_72#_M1008_g N_A_80_72#_c_89_n
diff --git a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice
index 5ca0bde..9b2f6bb 100644
--- a/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice
+++ b/cells/a21bo/sky130_fd_sc_lp__a21bo_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21bo_m.spice
-* Created: Fri Aug 28 09:49:38 2020
+* Created: Wed Sep 2 09:19:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report
new file mode 100644
index 0000000..ae27d32
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_0.sp ('sky130_fd_sc_lp__a21boi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice ('sky130_fd_sc_lp__a21boi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_0 sky130_fd_sc_lp__a21boi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice
index ff8cefc..6e41b6d 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_0.pex.spice
-* Created: Fri Aug 28 09:49:45 2020
+* Created: Wed Sep 2 09:19:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice
index fd67708..b3cd822 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_0.pxi.spice
-* Created: Fri Aug 28 09:49:45 2020
+* Created: Wed Sep 2 09:19:12 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_0%B1_N N_B1_N_M1002_g N_B1_N_c_62_n N_B1_N_M1004_g
+ N_B1_N_c_64_n B1_N B1_N B1_N N_B1_N_c_66_n PM_SKY130_FD_SC_LP__A21BOI_0%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice
index eb001e0..b3c927b 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_0.spice
-* Created: Fri Aug 28 09:49:45 2020
+* Created: Wed Sep 2 09:19:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report
new file mode 100644
index 0000000..a13705a
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_1.sp ('sky130_fd_sc_lp__a21boi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice ('sky130_fd_sc_lp__a21boi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_1 sky130_fd_sc_lp__a21boi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice
index c0aa130..3d0236d 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_1.pex.spice
-* Created: Fri Aug 28 09:49:52 2020
+* Created: Wed Sep 2 09:19:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice
index 06b098e..8e7bdee 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_1.pxi.spice
-* Created: Fri Aug 28 09:49:52 2020
+* Created: Wed Sep 2 09:19:18 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_1%B1_N N_B1_N_c_60_n N_B1_N_M1001_g N_B1_N_c_61_n
+ N_B1_N_c_62_n N_B1_N_M1002_g N_B1_N_c_64_n N_B1_N_c_69_n B1_N B1_N B1_N B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice
index 251ec10..2d21cc0 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_1.spice
-* Created: Fri Aug 28 09:49:52 2020
+* Created: Wed Sep 2 09:19:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report
new file mode 100644
index 0000000..14095c8
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_2.sp ('sky130_fd_sc_lp__a21boi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice ('sky130_fd_sc_lp__a21boi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_2 sky130_fd_sc_lp__a21boi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice
index 3732d5d..2f87c3c 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_2.pex.spice
-* Created: Fri Aug 28 09:50:08 2020
+* Created: Wed Sep 2 09:19:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice
index afc995c..e981e7b 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_2.pxi.spice
-* Created: Fri Aug 28 09:50:08 2020
+* Created: Wed Sep 2 09:19:24 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_2%B1_N N_B1_N_M1011_g N_B1_N_c_83_n N_B1_N_c_84_n
+ N_B1_N_c_85_n N_B1_N_M1012_g N_B1_N_c_86_n B1_N B1_N B1_N B1_N B1_N B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice
index 4f5452b..5cb305f 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_2.spice
-* Created: Fri Aug 28 09:50:08 2020
+* Created: Wed Sep 2 09:19:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report
new file mode 100644
index 0000000..d489cff
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_4.sp ('sky130_fd_sc_lp__a21boi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice ('sky130_fd_sc_lp__a21boi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_4 sky130_fd_sc_lp__a21boi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice
index f00c0e7..330331c 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_4.pex.spice
-* Created: Fri Aug 28 09:50:15 2020
+* Created: Wed Sep 2 09:19:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice
index f5dbe36..0e42916 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_4.pxi.spice
-* Created: Fri Aug 28 09:50:15 2020
+* Created: Wed Sep 2 09:19:30 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_4%B1_N N_B1_N_M1007_g N_B1_N_c_103_n N_B1_N_M1014_g
+ B1_N B1_N N_B1_N_c_105_n PM_SKY130_FD_SC_LP__A21BOI_4%B1_N
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice
index 984ea13..af017fe 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_4.spice
-* Created: Fri Aug 28 09:50:15 2020
+* Created: Wed Sep 2 09:19:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report
new file mode 100644
index 0000000..4e78f08
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_lp.sp ('sky130_fd_sc_lp__a21boi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice ('sky130_fd_sc_lp__a21boi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_lp sky130_fd_sc_lp__a21boi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice
index 351337d..6701413 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_lp.pex.spice
-* Created: Fri Aug 28 09:50:22 2020
+* Created: Wed Sep 2 09:19:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice
index c9c7c49..81f8e1c 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_lp.pxi.spice
-* Created: Fri Aug 28 09:50:22 2020
+* Created: Wed Sep 2 09:19:36 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_LP%A2 N_A2_M1002_g N_A2_M1003_g A2 A2 N_A2_c_64_n
+ PM_SKY130_FD_SC_LP__A21BOI_LP%A2
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice
index 01c8f50..30c79bc 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_lp.spice
-* Created: Fri Aug 28 09:50:22 2020
+* Created: Wed Sep 2 09:19:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report
new file mode 100644
index 0000000..5382737
--- /dev/null
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21boi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21boi_m.sp ('sky130_fd_sc_lp__a21boi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice ('sky130_fd_sc_lp__a21boi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21boi_m sky130_fd_sc_lp__a21boi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21boi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a21boi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice
index 40866b8..e720f1e 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_m.pex.spice
-* Created: Fri Aug 28 09:50:29 2020
+* Created: Wed Sep 2 09:19:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice
index cc4feab..24aba70 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_m.pxi.spice
-* Created: Fri Aug 28 09:50:29 2020
+* Created: Wed Sep 2 09:19:43 2020
*
x_PM_SKY130_FD_SC_LP__A21BOI_M%B1_N N_B1_N_M1005_g N_B1_N_M1002_g N_B1_N_c_64_n
+ N_B1_N_c_65_n B1_N B1_N B1_N B1_N N_B1_N_c_67_n
diff --git a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice
index 78bd9a1..5c607fc 100644
--- a/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice
+++ b/cells/a21boi/sky130_fd_sc_lp__a21boi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21boi_m.spice
-* Created: Fri Aug 28 09:50:29 2020
+* Created: Wed Sep 2 09:19:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report
new file mode 100644
index 0000000..1e635d9
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_0.sp ('sky130_fd_sc_lp__a21o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_0.spice ('sky130_fd_sc_lp__a21o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_0 sky130_fd_sc_lp__a21o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice
index c1f61e4..02e6140 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_0.pex.spice
-* Created: Fri Aug 28 09:50:36 2020
+* Created: Wed Sep 2 09:19:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice
index aeb3f7d..0de57cb 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_0.pxi.spice
-* Created: Fri Aug 28 09:50:36 2020
+* Created: Wed Sep 2 09:19:49 2020
*
x_PM_SKY130_FD_SC_LP__A21O_0%A_80_275# N_A_80_275#_M1002_d N_A_80_275#_M1000_s
+ N_A_80_275#_M1003_g N_A_80_275#_c_68_n N_A_80_275#_c_69_n N_A_80_275#_M1007_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_0.spice b/cells/a21o/sky130_fd_sc_lp__a21o_0.spice
index c93b8a4..72b8806 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_0.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_0.spice
-* Created: Fri Aug 28 09:50:36 2020
+* Created: Wed Sep 2 09:19:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report
new file mode 100644
index 0000000..6a753a0
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_1.sp ('sky130_fd_sc_lp__a21o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_1.spice ('sky130_fd_sc_lp__a21o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_1 sky130_fd_sc_lp__a21o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice
index fd7a15c..787f6a5 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_1.pex.spice
-* Created: Fri Aug 28 09:50:43 2020
+* Created: Wed Sep 2 09:19:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice
index b6833d1..ee48e83 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_1.pxi.spice
-* Created: Fri Aug 28 09:50:43 2020
+* Created: Wed Sep 2 09:19:55 2020
*
x_PM_SKY130_FD_SC_LP__A21O_1%A_80_237# N_A_80_237#_M1003_d N_A_80_237#_M1001_s
+ N_A_80_237#_M1007_g N_A_80_237#_c_50_n N_A_80_237#_M1000_g N_A_80_237#_c_51_n
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_1.spice b/cells/a21o/sky130_fd_sc_lp__a21o_1.spice
index 39173a3..b8a0294 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_1.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_1.spice
-* Created: Fri Aug 28 09:50:43 2020
+* Created: Wed Sep 2 09:19:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report
new file mode 100644
index 0000000..2843f4e
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_2.sp ('sky130_fd_sc_lp__a21o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_2.spice ('sky130_fd_sc_lp__a21o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:19:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_2 sky130_fd_sc_lp__a21o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice
index 2f3a588..0c61b66 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_2.pex.spice
-* Created: Fri Aug 28 09:50:54 2020
+* Created: Wed Sep 2 09:20:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice
index 32de5a9..1389152 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_2.pxi.spice
-* Created: Fri Aug 28 09:50:54 2020
+* Created: Wed Sep 2 09:20:01 2020
*
x_PM_SKY130_FD_SC_LP__A21O_2%A_86_269# N_A_86_269#_M1003_d N_A_86_269#_M1000_s
+ N_A_86_269#_M1002_g N_A_86_269#_M1001_g N_A_86_269#_M1006_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_2.spice b/cells/a21o/sky130_fd_sc_lp__a21o_2.spice
index 20b31ce..a795a22 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_2.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_2.spice
-* Created: Fri Aug 28 09:50:54 2020
+* Created: Wed Sep 2 09:20:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report
new file mode 100644
index 0000000..22a2490
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_4.sp ('sky130_fd_sc_lp__a21o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_4.spice ('sky130_fd_sc_lp__a21o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_4 sky130_fd_sc_lp__a21o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice
index f96d6fd..a1a4593 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_4.pex.spice
-* Created: Fri Aug 28 09:51:10 2020
+* Created: Wed Sep 2 09:20:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice
index 1be4b57..abcfb35 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_4.pxi.spice
-* Created: Fri Aug 28 09:51:10 2020
+* Created: Wed Sep 2 09:20:07 2020
*
x_PM_SKY130_FD_SC_LP__A21O_4%A_134_269# N_A_134_269#_M1009_s
+ N_A_134_269#_M1000_s N_A_134_269#_M1005_s N_A_134_269#_M1001_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_4.spice b/cells/a21o/sky130_fd_sc_lp__a21o_4.spice
index 1d9dfe0..e725114 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_4.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_4.spice
-* Created: Fri Aug 28 09:51:10 2020
+* Created: Wed Sep 2 09:20:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report
new file mode 100644
index 0000000..e7aa554
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_lp.sp ('sky130_fd_sc_lp__a21o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice ('sky130_fd_sc_lp__a21o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_lp sky130_fd_sc_lp__a21o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice
index 2449dcb..c34a179 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_lp.pex.spice
-* Created: Fri Aug 28 09:51:17 2020
+* Created: Wed Sep 2 09:20:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice
index 20e265f..f553c4d 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_lp.pxi.spice
-* Created: Fri Aug 28 09:51:17 2020
+* Created: Wed Sep 2 09:20:14 2020
*
x_PM_SKY130_FD_SC_LP__A21O_LP%A2 N_A2_M1003_g N_A2_M1006_g A2 A2 N_A2_c_61_n
+ N_A2_c_62_n PM_SKY130_FD_SC_LP__A21O_LP%A2
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice b/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice
index 101a55f..63a7eb2 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_lp.spice
-* Created: Fri Aug 28 09:51:17 2020
+* Created: Wed Sep 2 09:20:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report b/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report
new file mode 100644
index 0000000..775d5a6
--- /dev/null
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21o_m.sp ('sky130_fd_sc_lp__a21o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21o/sky130_fd_sc_lp__a21o_m.spice ('sky130_fd_sc_lp__a21o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21o_m sky130_fd_sc_lp__a21o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a21o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice
index 61a3158..e4e27a6 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_m.pex.spice
-* Created: Fri Aug 28 09:51:23 2020
+* Created: Wed Sep 2 09:20:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice
index 233f6f2..c50f308 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_m.pxi.spice
-* Created: Fri Aug 28 09:51:23 2020
+* Created: Wed Sep 2 09:20:20 2020
*
x_PM_SKY130_FD_SC_LP__A21O_M%A_80_153# N_A_80_153#_M1001_d N_A_80_153#_M1005_s
+ N_A_80_153#_c_68_n N_A_80_153#_M1004_g N_A_80_153#_c_62_n N_A_80_153#_M1007_g
diff --git a/cells/a21o/sky130_fd_sc_lp__a21o_m.spice b/cells/a21o/sky130_fd_sc_lp__a21o_m.spice
index d462f1b..5ce3167 100644
--- a/cells/a21o/sky130_fd_sc_lp__a21o_m.spice
+++ b/cells/a21o/sky130_fd_sc_lp__a21o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21o_m.spice
-* Created: Fri Aug 28 09:51:23 2020
+* Created: Wed Sep 2 09:20:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report
new file mode 100644
index 0000000..771730b
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_0.sp ('sky130_fd_sc_lp__a21oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice ('sky130_fd_sc_lp__a21oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_0 sky130_fd_sc_lp__a21oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice
index f2bb457..84c69a9 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_0.pex.spice
-* Created: Fri Aug 28 09:51:30 2020
+* Created: Wed Sep 2 09:20:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice
index a89ba44..9be8ff8 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_0.pxi.spice
-* Created: Fri Aug 28 09:51:30 2020
+* Created: Wed Sep 2 09:20:26 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_0%A2 N_A2_c_47_n N_A2_M1005_g N_A2_c_48_n
+ N_A2_M1000_g N_A2_c_49_n N_A2_c_50_n N_A2_c_55_n A2 A2 A2 N_A2_c_52_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice
index 7457415..764732a 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_0.spice
-* Created: Fri Aug 28 09:51:30 2020
+* Created: Wed Sep 2 09:20:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report
new file mode 100644
index 0000000..b50f97e
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_1.sp ('sky130_fd_sc_lp__a21oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice ('sky130_fd_sc_lp__a21oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_1 sky130_fd_sc_lp__a21oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice
index a67f9cf..244811b 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_1.pex.spice
-* Created: Fri Aug 28 09:51:37 2020
+* Created: Wed Sep 2 09:20:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice
index 154c752..c76129e 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_1.pxi.spice
-* Created: Fri Aug 28 09:51:37 2020
+* Created: Wed Sep 2 09:20:32 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_1%A2 N_A2_M1002_g N_A2_M1005_g A2 A2 N_A2_c_41_n
+ N_A2_c_42_n PM_SKY130_FD_SC_LP__A21OI_1%A2
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice
index f81502a..fad3808 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_1.spice
-* Created: Fri Aug 28 09:51:37 2020
+* Created: Wed Sep 2 09:20:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report
new file mode 100644
index 0000000..f6ae86f
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_2.sp ('sky130_fd_sc_lp__a21oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice ('sky130_fd_sc_lp__a21oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_2 sky130_fd_sc_lp__a21oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice
index d180955..6b07479 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_2.pex.spice
-* Created: Fri Aug 28 09:51:44 2020
+* Created: Wed Sep 2 09:20:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice
index a6e112b..e8bb899 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_2.pxi.spice
-* Created: Fri Aug 28 09:51:44 2020
+* Created: Wed Sep 2 09:20:38 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_2%A2 N_A2_M1003_g N_A2_M1009_g N_A2_M1006_g
+ N_A2_M1010_g N_A2_c_62_n N_A2_c_63_n A2 N_A2_c_65_n N_A2_c_66_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice
index 694307b..78f2c34 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_2.spice
-* Created: Fri Aug 28 09:51:44 2020
+* Created: Wed Sep 2 09:20:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report
new file mode 100644
index 0000000..a08e47c
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_4.sp ('sky130_fd_sc_lp__a21oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice ('sky130_fd_sc_lp__a21oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_4 sky130_fd_sc_lp__a21oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice
index 24986d1..abaf82a 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_4.pex.spice
-* Created: Fri Aug 28 09:51:51 2020
+* Created: Wed Sep 2 09:20:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice
index 97ce357..b564b0f 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_4.pxi.spice
-* Created: Fri Aug 28 09:51:51 2020
+* Created: Wed Sep 2 09:20:45 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_4%A2 N_A2_M1000_g N_A2_M1008_g N_A2_M1007_g
+ N_A2_M1018_g N_A2_M1012_g N_A2_M1020_g N_A2_M1016_g N_A2_M1022_g N_A2_c_99_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice
index e5929f2..e9035ba 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_4.spice
-* Created: Fri Aug 28 09:51:51 2020
+* Created: Wed Sep 2 09:20:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report
new file mode 100644
index 0000000..dc0962e
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_lp.sp ('sky130_fd_sc_lp__a21oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice ('sky130_fd_sc_lp__a21oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_lp sky130_fd_sc_lp__a21oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice
index a506496..0c8355d 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_lp.pex.spice
-* Created: Fri Aug 28 09:51:58 2020
+* Created: Wed Sep 2 09:20:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice
index 47fc74f..5e4588d 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_lp.pxi.spice
-* Created: Fri Aug 28 09:51:58 2020
+* Created: Wed Sep 2 09:20:51 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_LP%A2 N_A2_c_48_n N_A2_c_54_n N_A2_M1005_g
+ N_A2_M1002_g N_A2_c_50_n N_A2_c_51_n A2 N_A2_c_52_n N_A2_c_53_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice
index 1bcc208..ff05db3 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_lp.spice
-* Created: Fri Aug 28 09:51:58 2020
+* Created: Wed Sep 2 09:20:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report
new file mode 100644
index 0000000..2c01e13
--- /dev/null
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a21oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a21oi_m.sp ('sky130_fd_sc_lp__a21oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice ('sky130_fd_sc_lp__a21oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:20:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a21oi_m sky130_fd_sc_lp__a21oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a21oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a21oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice
index 8c40bf3..bd0b27d 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_m.pex.spice
-* Created: Fri Aug 28 09:52:14 2020
+* Created: Wed Sep 2 09:20:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice
index 622f2fd..e0d5359 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_m.pxi.spice
-* Created: Fri Aug 28 09:52:14 2020
+* Created: Wed Sep 2 09:20:57 2020
*
x_PM_SKY130_FD_SC_LP__A21OI_M%A2 N_A2_c_49_n N_A2_M1001_g N_A2_M1005_g
+ N_A2_c_51_n N_A2_c_52_n N_A2_c_57_n A2 A2 A2 A2 N_A2_c_54_n
diff --git a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice
index c9fd2ad..9e66f34 100644
--- a/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice
+++ b/cells/a21oi/sky130_fd_sc_lp__a21oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a21oi_m.spice
-* Created: Fri Aug 28 09:52:14 2020
+* Created: Wed Sep 2 09:20:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report
new file mode 100644
index 0000000..64f28b5
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_0.sp ('sky130_fd_sc_lp__a221o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_0.spice ('sky130_fd_sc_lp__a221o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_0 sky130_fd_sc_lp__a221o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice
index 1343cb9..da61c83 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_0.pex.spice
-* Created: Fri Aug 28 09:52:21 2020
+* Created: Wed Sep 2 09:21:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice
index 3087407..ade8dea 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_0.pxi.spice
-* Created: Fri Aug 28 09:52:21 2020
+* Created: Wed Sep 2 09:21:04 2020
*
x_PM_SKY130_FD_SC_LP__A221O_0%A_72_312# N_A_72_312#_M1005_d N_A_72_312#_M1010_d
+ N_A_72_312#_M1011_d N_A_72_312#_M1000_g N_A_72_312#_M1003_g N_A_72_312#_c_96_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_0.spice b/cells/a221o/sky130_fd_sc_lp__a221o_0.spice
index 2417086..ab63f2c 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_0.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_0.spice
-* Created: Fri Aug 28 09:52:21 2020
+* Created: Wed Sep 2 09:21:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report
new file mode 100644
index 0000000..f073665
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_1.sp ('sky130_fd_sc_lp__a221o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_1.spice ('sky130_fd_sc_lp__a221o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_1 sky130_fd_sc_lp__a221o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice
index 5b0139f..e848235 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_1.pex.spice
-* Created: Fri Aug 28 09:52:27 2020
+* Created: Wed Sep 2 09:21:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice
index 247810a..3fa30c0 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_1.pxi.spice
-* Created: Fri Aug 28 09:52:27 2020
+* Created: Wed Sep 2 09:21:10 2020
*
x_PM_SKY130_FD_SC_LP__A221O_1%A_80_21# N_A_80_21#_M1009_d N_A_80_21#_M1003_d
+ N_A_80_21#_M1000_d N_A_80_21#_M1001_g N_A_80_21#_M1011_g N_A_80_21#_c_67_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_1.spice b/cells/a221o/sky130_fd_sc_lp__a221o_1.spice
index ac4c4ae..1c53e54 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_1.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_1.spice
-* Created: Fri Aug 28 09:52:27 2020
+* Created: Wed Sep 2 09:21:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report
new file mode 100644
index 0000000..317b104
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_2.sp ('sky130_fd_sc_lp__a221o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_2.spice ('sky130_fd_sc_lp__a221o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_2 sky130_fd_sc_lp__a221o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 C1 B1 B2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice
index acd2386..272d9be 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_2.pex.spice
-* Created: Fri Aug 28 09:52:34 2020
+* Created: Wed Sep 2 09:21:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice
index b93b962..4b72201 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_2.pxi.spice
-* Created: Fri Aug 28 09:52:34 2020
+* Created: Wed Sep 2 09:21:16 2020
*
x_PM_SKY130_FD_SC_LP__A221O_2%A_86_27# N_A_86_27#_M1003_d N_A_86_27#_M1013_d
+ N_A_86_27#_M1010_s N_A_86_27#_c_73_n N_A_86_27#_M1011_g N_A_86_27#_M1004_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_2.spice b/cells/a221o/sky130_fd_sc_lp__a221o_2.spice
index e47e546..f4a558c 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_2.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_2.spice
-* Created: Fri Aug 28 09:52:34 2020
+* Created: Wed Sep 2 09:21:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report
new file mode 100644
index 0000000..4cecb6b
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_4.sp ('sky130_fd_sc_lp__a221o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_4.spice ('sky130_fd_sc_lp__a221o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_4 sky130_fd_sc_lp__a221o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 C1 B1 B2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice
index aa0180b..b94b255 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_4.pex.spice
-* Created: Fri Aug 28 09:52:41 2020
+* Created: Wed Sep 2 09:21:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice
index 49f6596..953f1cf 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_4.pxi.spice
-* Created: Fri Aug 28 09:52:41 2020
+* Created: Wed Sep 2 09:21:22 2020
*
x_PM_SKY130_FD_SC_LP__A221O_4%A_83_21# N_A_83_21#_M1013_s N_A_83_21#_M1020_s
+ N_A_83_21#_M1011_s N_A_83_21#_M1024_d N_A_83_21#_M1016_s N_A_83_21#_M1003_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_4.spice b/cells/a221o/sky130_fd_sc_lp__a221o_4.spice
index c26036c..090d4fa 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_4.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_4.spice
-* Created: Fri Aug 28 09:52:41 2020
+* Created: Wed Sep 2 09:21:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report
new file mode 100644
index 0000000..bebaddd
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_lp.sp ('sky130_fd_sc_lp__a221o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice ('sky130_fd_sc_lp__a221o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_lp sky130_fd_sc_lp__a221o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice
index 44d1b5b..20f05c8 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_lp.pex.spice
-* Created: Fri Aug 28 09:52:48 2020
+* Created: Wed Sep 2 09:21:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice
index 77cc9bf..0f70a37 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_lp.pxi.spice
-* Created: Fri Aug 28 09:52:48 2020
+* Created: Wed Sep 2 09:21:29 2020
*
x_PM_SKY130_FD_SC_LP__A221O_LP%A_96_183# N_A_96_183#_M1011_d N_A_96_183#_M1008_d
+ N_A_96_183#_M1002_d N_A_96_183#_M1003_g N_A_96_183#_M1010_g N_A_96_183#_c_94_n
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice b/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice
index f5250c6..a06f01e 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_lp.spice
-* Created: Fri Aug 28 09:52:48 2020
+* Created: Wed Sep 2 09:21:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report b/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report
new file mode 100644
index 0000000..d118c4b
--- /dev/null
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221o_m.sp ('sky130_fd_sc_lp__a221o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221o/sky130_fd_sc_lp__a221o_m.spice ('sky130_fd_sc_lp__a221o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221o_m sky130_fd_sc_lp__a221o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a221o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice
index c925fc5..c4aff2d 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_m.pex.spice
-* Created: Fri Aug 28 09:52:55 2020
+* Created: Wed Sep 2 09:21:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice
index 9cb1ee9..000c818 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_m.pxi.spice
-* Created: Fri Aug 28 09:52:55 2020
+* Created: Wed Sep 2 09:21:36 2020
*
x_PM_SKY130_FD_SC_LP__A221O_M%A_33_153# N_A_33_153#_M1008_d N_A_33_153#_M1011_d
+ N_A_33_153#_M1009_d N_A_33_153#_c_79_n N_A_33_153#_M1004_g N_A_33_153#_M1002_g
diff --git a/cells/a221o/sky130_fd_sc_lp__a221o_m.spice b/cells/a221o/sky130_fd_sc_lp__a221o_m.spice
index 5f6e52a..390be9c 100644
--- a/cells/a221o/sky130_fd_sc_lp__a221o_m.spice
+++ b/cells/a221o/sky130_fd_sc_lp__a221o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221o_m.spice
-* Created: Fri Aug 28 09:52:55 2020
+* Created: Wed Sep 2 09:21:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report
new file mode 100644
index 0000000..0a01667
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_0.sp ('sky130_fd_sc_lp__a221oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice ('sky130_fd_sc_lp__a221oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_0 sky130_fd_sc_lp__a221oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice
index 2b429ea..87fbcd8 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_0.pex.spice
-* Created: Fri Aug 28 09:53:02 2020
+* Created: Wed Sep 2 09:21:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice
index 7eb719d..b30f9fd 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_0.pxi.spice
-* Created: Fri Aug 28 09:53:02 2020
+* Created: Wed Sep 2 09:21:42 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_0%C1 N_C1_M1009_g N_C1_c_75_n N_C1_M1007_g
+ N_C1_c_80_n C1 C1 C1 N_C1_c_77_n PM_SKY130_FD_SC_LP__A221OI_0%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice
index ecc2358..590f42f 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_0.spice
-* Created: Fri Aug 28 09:53:02 2020
+* Created: Wed Sep 2 09:21:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report
new file mode 100644
index 0000000..aa1273b
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_1.sp ('sky130_fd_sc_lp__a221oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice ('sky130_fd_sc_lp__a221oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_1 sky130_fd_sc_lp__a221oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice
index c480c22..97af2aa 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_1.pex.spice
-* Created: Fri Aug 28 09:53:18 2020
+* Created: Wed Sep 2 09:21:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice
index 4186bd4..e34485e 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_1.pxi.spice
-* Created: Fri Aug 28 09:53:18 2020
+* Created: Wed Sep 2 09:21:49 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_1%C1 N_C1_M1009_g N_C1_M1007_g C1 C1 N_C1_c_55_n
+ PM_SKY130_FD_SC_LP__A221OI_1%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice
index 1199786..3e0776e 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_1.spice
-* Created: Fri Aug 28 09:53:18 2020
+* Created: Wed Sep 2 09:21:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report
new file mode 100644
index 0000000..0b3ba7e
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_2.sp ('sky130_fd_sc_lp__a221oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice ('sky130_fd_sc_lp__a221oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_2 sky130_fd_sc_lp__a221oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice
index 5e713f3..0965479 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_2.pex.spice
-* Created: Fri Aug 28 09:53:25 2020
+* Created: Wed Sep 2 09:21:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice
index 223a31b..38fb4c4 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_2.pxi.spice
-* Created: Fri Aug 28 09:53:25 2020
+* Created: Wed Sep 2 09:21:55 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_2%C1 N_C1_M1005_g N_C1_M1003_g N_C1_M1018_g
+ N_C1_M1007_g C1 C1 N_C1_c_95_n PM_SKY130_FD_SC_LP__A221OI_2%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice
index 903a145..68d6283 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_2.spice
-* Created: Fri Aug 28 09:53:25 2020
+* Created: Wed Sep 2 09:21:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report
new file mode 100644
index 0000000..d5d5a8d
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_4.sp ('sky130_fd_sc_lp__a221oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice ('sky130_fd_sc_lp__a221oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:21:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_4 sky130_fd_sc_lp__a221oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice
index c7641e6..78320d6 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_4.pex.spice
-* Created: Fri Aug 28 09:53:32 2020
+* Created: Wed Sep 2 09:22:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice
index d290151..3aa4eac 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_4.pxi.spice
-* Created: Fri Aug 28 09:53:32 2020
+* Created: Wed Sep 2 09:22:01 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_4%C1 N_C1_M1016_g N_C1_c_144_n N_C1_M1007_g
+ N_C1_M1022_g N_C1_c_146_n N_C1_M1025_g N_C1_M1031_g N_C1_c_148_n N_C1_M1028_g
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice
index 24cde74..c62b113 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_4.spice
-* Created: Fri Aug 28 09:53:32 2020
+* Created: Wed Sep 2 09:22:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report
new file mode 100644
index 0000000..9e250b3
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_lp.sp ('sky130_fd_sc_lp__a221oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice ('sky130_fd_sc_lp__a221oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_lp sky130_fd_sc_lp__a221oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice
index 91bc2db..a906dba 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_lp.pex.spice
-* Created: Fri Aug 28 09:53:39 2020
+* Created: Wed Sep 2 09:22:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice
index f5c0ffa..09e4731 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_lp.pxi.spice
-* Created: Fri Aug 28 09:53:39 2020
+* Created: Wed Sep 2 09:22:08 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_LP%B2 N_B2_M1010_g N_B2_M1008_g N_B2_c_68_n
+ N_B2_c_69_n B2 B2 N_B2_c_71_n PM_SKY130_FD_SC_LP__A221OI_LP%B2
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice
index 7a79adc..e800beb 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_lp.spice
-* Created: Fri Aug 28 09:53:39 2020
+* Created: Wed Sep 2 09:22:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report
new file mode 100644
index 0000000..750a410
--- /dev/null
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a221oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a221oi_m.sp ('sky130_fd_sc_lp__a221oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice ('sky130_fd_sc_lp__a221oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a221oi_m sky130_fd_sc_lp__a221oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a221oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a221oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice
index 5966505..6c08934 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_m.pex.spice
-* Created: Fri Aug 28 09:53:46 2020
+* Created: Wed Sep 2 09:22:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice
index d6ec7cf..8330096 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_m.pxi.spice
-* Created: Fri Aug 28 09:53:46 2020
+* Created: Wed Sep 2 09:22:14 2020
*
x_PM_SKY130_FD_SC_LP__A221OI_M%C1 N_C1_M1009_g N_C1_c_74_n N_C1_M1007_g
+ N_C1_c_71_n C1 C1 C1 N_C1_c_73_n PM_SKY130_FD_SC_LP__A221OI_M%C1
diff --git a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice
index 624be03..5a90593 100644
--- a/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice
+++ b/cells/a221oi/sky130_fd_sc_lp__a221oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a221oi_m.spice
-* Created: Fri Aug 28 09:53:46 2020
+* Created: Wed Sep 2 09:22:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report
new file mode 100644
index 0000000..c63c866
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_0.sp ('sky130_fd_sc_lp__a22o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_0.spice ('sky130_fd_sc_lp__a22o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_0 sky130_fd_sc_lp__a22o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice
index 3949ffd..e322b98 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_0.pex.spice
-* Created: Fri Aug 28 09:53:53 2020
+* Created: Wed Sep 2 09:22:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice
index a622fea..a9d1f97 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_0.pxi.spice
-* Created: Fri Aug 28 09:53:53 2020
+* Created: Wed Sep 2 09:22:21 2020
*
x_PM_SKY130_FD_SC_LP__A22O_0%A_85_155# N_A_85_155#_M1009_d N_A_85_155#_M1000_d
+ N_A_85_155#_M1008_g N_A_85_155#_M1005_g N_A_85_155#_c_67_n N_A_85_155#_c_68_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_0.spice b/cells/a22o/sky130_fd_sc_lp__a22o_0.spice
index 2948e34..4030b84 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_0.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_0.spice
-* Created: Fri Aug 28 09:53:53 2020
+* Created: Wed Sep 2 09:22:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report
new file mode 100644
index 0000000..84e41b1
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_1.sp ('sky130_fd_sc_lp__a22o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_1.spice ('sky130_fd_sc_lp__a22o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_1 sky130_fd_sc_lp__a22o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice
index 0e2ed40..dfb0b8d 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_1.pex.spice
-* Created: Fri Aug 28 09:54:00 2020
+* Created: Wed Sep 2 09:22:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice
index 5299c6b..b164eef 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_1.pxi.spice
-* Created: Fri Aug 28 09:54:00 2020
+* Created: Wed Sep 2 09:22:27 2020
*
x_PM_SKY130_FD_SC_LP__A22O_1%A_80_246# N_A_80_246#_M1004_d N_A_80_246#_M1002_d
+ N_A_80_246#_M1009_g N_A_80_246#_c_57_n N_A_80_246#_M1006_g N_A_80_246#_c_58_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_1.spice b/cells/a22o/sky130_fd_sc_lp__a22o_1.spice
index 43bc195..0e96c89 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_1.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_1.spice
-* Created: Fri Aug 28 09:54:00 2020
+* Created: Wed Sep 2 09:22:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report
new file mode 100644
index 0000000..6062377
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_2.sp ('sky130_fd_sc_lp__a22o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_2.spice ('sky130_fd_sc_lp__a22o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_2 sky130_fd_sc_lp__a22o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice
index 047649d..49e8854 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_2.pex.spice
-* Created: Fri Aug 28 09:54:07 2020
+* Created: Wed Sep 2 09:22:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice
index 4e674ff..dee55e8 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_2.pxi.spice
-* Created: Fri Aug 28 09:54:07 2020
+* Created: Wed Sep 2 09:22:33 2020
*
x_PM_SKY130_FD_SC_LP__A22O_2%A_94_249# N_A_94_249#_M1000_d N_A_94_249#_M1007_d
+ N_A_94_249#_M1010_s N_A_94_249#_M1004_d N_A_94_249#_M1008_g
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_2.spice b/cells/a22o/sky130_fd_sc_lp__a22o_2.spice
index fb558ee..d515753 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_2.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_2.spice
-* Created: Fri Aug 28 09:54:07 2020
+* Created: Wed Sep 2 09:22:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report
new file mode 100644
index 0000000..519d5f8
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_4.sp ('sky130_fd_sc_lp__a22o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_4.spice ('sky130_fd_sc_lp__a22o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_4 sky130_fd_sc_lp__a22o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice
index cd8df62..ac5830a 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_4.pex.spice
-* Created: Fri Aug 28 09:54:23 2020
+* Created: Wed Sep 2 09:22:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice
index 70eedd9..a4c17d0 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_4.pxi.spice
-* Created: Fri Aug 28 09:54:23 2020
+* Created: Wed Sep 2 09:22:40 2020
*
x_PM_SKY130_FD_SC_LP__A22O_4%A_103_263# N_A_103_263#_M1001_d
+ N_A_103_263#_M1007_s N_A_103_263#_M1005_s N_A_103_263#_M1019_s
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_4.spice b/cells/a22o/sky130_fd_sc_lp__a22o_4.spice
index f340909..5b38ab8 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_4.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_4.spice
-* Created: Fri Aug 28 09:54:23 2020
+* Created: Wed Sep 2 09:22:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report
new file mode 100644
index 0000000..7eb9a6e
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_lp.sp ('sky130_fd_sc_lp__a22o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice ('sky130_fd_sc_lp__a22o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_lp sky130_fd_sc_lp__a22o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B2 B1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice
index 537e98c..43a4a83 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_lp.pex.spice
-* Created: Fri Aug 28 09:54:30 2020
+* Created: Wed Sep 2 09:22:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice
index 7b6dce4..a7a88d4 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_lp.pxi.spice
-* Created: Fri Aug 28 09:54:30 2020
+* Created: Wed Sep 2 09:22:46 2020
*
x_PM_SKY130_FD_SC_LP__A22O_LP%A1 N_A1_M1009_g N_A1_M1008_g N_A1_c_73_n
+ N_A1_c_74_n N_A1_c_75_n N_A1_c_76_n A1 A1 N_A1_c_78_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice b/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice
index 382ee37..4cd73fa 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_lp.spice
-* Created: Fri Aug 28 09:54:30 2020
+* Created: Wed Sep 2 09:22:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report b/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report
new file mode 100644
index 0000000..a2c1c47
--- /dev/null
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22o_m.sp ('sky130_fd_sc_lp__a22o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22o/sky130_fd_sc_lp__a22o_m.spice ('sky130_fd_sc_lp__a22o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22o_m sky130_fd_sc_lp__a22o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a22o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice
index 34bd822..1684a50 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_m.pex.spice
-* Created: Fri Aug 28 09:54:37 2020
+* Created: Wed Sep 2 09:22:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice
index 8fbcdb5..9bf1675 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_m.pxi.spice
-* Created: Fri Aug 28 09:54:37 2020
+* Created: Wed Sep 2 09:22:52 2020
*
x_PM_SKY130_FD_SC_LP__A22O_M%A_85_317# N_A_85_317#_M1004_d N_A_85_317#_M1000_d
+ N_A_85_317#_M1002_g N_A_85_317#_M1001_g N_A_85_317#_c_66_n N_A_85_317#_c_72_n
diff --git a/cells/a22o/sky130_fd_sc_lp__a22o_m.spice b/cells/a22o/sky130_fd_sc_lp__a22o_m.spice
index ec67cb2..06de83c 100644
--- a/cells/a22o/sky130_fd_sc_lp__a22o_m.spice
+++ b/cells/a22o/sky130_fd_sc_lp__a22o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22o_m.spice
-* Created: Fri Aug 28 09:54:37 2020
+* Created: Wed Sep 2 09:22:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report
new file mode 100644
index 0000000..4607b92
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_0.sp ('sky130_fd_sc_lp__a22oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice ('sky130_fd_sc_lp__a22oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:22:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_0 sky130_fd_sc_lp__a22oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice
index a73ce95..1583ae3 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_0.pex.spice
-* Created: Fri Aug 28 09:54:45 2020
+* Created: Wed Sep 2 09:22:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice
index ea30dff..99aca25 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_0.pxi.spice
-* Created: Fri Aug 28 09:54:45 2020
+* Created: Wed Sep 2 09:22:58 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_0%B2 N_B2_M1006_g N_B2_M1004_g N_B2_c_54_n
+ N_B2_c_59_n B2 B2 B2 N_B2_c_56_n PM_SKY130_FD_SC_LP__A22OI_0%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice
index 35ddc02..d45cd79 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_0.spice
-* Created: Fri Aug 28 09:54:45 2020
+* Created: Wed Sep 2 09:22:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report
new file mode 100644
index 0000000..f963b73
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_1.sp ('sky130_fd_sc_lp__a22oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice ('sky130_fd_sc_lp__a22oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_1 sky130_fd_sc_lp__a22oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice
index e96dc1b..272c5aa 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_1.pex.spice
-* Created: Fri Aug 28 09:54:52 2020
+* Created: Wed Sep 2 09:23:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice
index 7d60ec3..3c4f147 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_1.pxi.spice
-* Created: Fri Aug 28 09:54:52 2020
+* Created: Wed Sep 2 09:23:05 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_1%B2 N_B2_c_47_n N_B2_M1004_g N_B2_M1002_g B2 B2
+ N_B2_c_50_n PM_SKY130_FD_SC_LP__A22OI_1%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice
index a2ddb1f..78184d8 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_1.spice
-* Created: Fri Aug 28 09:54:52 2020
+* Created: Wed Sep 2 09:23:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report
new file mode 100644
index 0000000..2e3b25b
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_2.sp ('sky130_fd_sc_lp__a22oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice ('sky130_fd_sc_lp__a22oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_2 sky130_fd_sc_lp__a22oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice
index fa4631f..0be0488 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_2.pex.spice
-* Created: Fri Aug 28 09:54:59 2020
+* Created: Wed Sep 2 09:23:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice
index 26afc70..5cceee4 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_2.pxi.spice
-* Created: Fri Aug 28 09:54:59 2020
+* Created: Wed Sep 2 09:23:11 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_2%A1 N_A1_M1004_g N_A1_M1002_g N_A1_M1003_g
+ N_A1_M1014_g A1 A1 A1 A1 N_A1_c_75_n N_A1_c_76_n N_A1_c_77_n N_A1_c_78_n
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice
index 862eb84..aa3ab8e 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_2.spice
-* Created: Fri Aug 28 09:54:59 2020
+* Created: Wed Sep 2 09:23:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report
new file mode 100644
index 0000000..84f73f5
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_4.sp ('sky130_fd_sc_lp__a22oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice ('sky130_fd_sc_lp__a22oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_4 sky130_fd_sc_lp__a22oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice
index a2c0aa6..dc638ee 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_4.pex.spice
-* Created: Fri Aug 28 09:55:07 2020
+* Created: Wed Sep 2 09:23:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice
index ae62326..a881ebf 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_4.pxi.spice
-* Created: Fri Aug 28 09:55:07 2020
+* Created: Wed Sep 2 09:23:17 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_4%B2 N_B2_c_114_n N_B2_M1009_g N_B2_M1006_g
+ N_B2_c_116_n N_B2_M1010_g N_B2_M1015_g N_B2_c_118_n N_B2_M1018_g N_B2_M1023_g
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice
index c1cea86..3b316a7 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_4.spice
-* Created: Fri Aug 28 09:55:07 2020
+* Created: Wed Sep 2 09:23:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report
new file mode 100644
index 0000000..38e868e
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_lp.sp ('sky130_fd_sc_lp__a22oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice ('sky130_fd_sc_lp__a22oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_lp sky130_fd_sc_lp__a22oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice
index 71dc7b7..c6e0e6a 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_lp.pex.spice
-* Created: Fri Aug 28 09:55:19 2020
+* Created: Wed Sep 2 09:23:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice
index 877d164..76f0c0b 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_lp.pxi.spice
-* Created: Fri Aug 28 09:55:19 2020
+* Created: Wed Sep 2 09:23:23 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_LP%B2 N_B2_M1004_g N_B2_M1005_g N_B2_c_58_n
+ N_B2_c_59_n B2 N_B2_c_61_n PM_SKY130_FD_SC_LP__A22OI_LP%B2
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice
index 0326687..d98dcc6 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_lp.spice
-* Created: Fri Aug 28 09:55:19 2020
+* Created: Wed Sep 2 09:23:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report
new file mode 100644
index 0000000..a1fd077
--- /dev/null
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a22oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a22oi_m.sp ('sky130_fd_sc_lp__a22oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice ('sky130_fd_sc_lp__a22oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a22oi_m sky130_fd_sc_lp__a22oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a22oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a22oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SPMP_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SPMP_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice
index dd6e05b..145779c 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_m.pex.spice
-* Created: Fri Aug 28 09:55:31 2020
+* Created: Wed Sep 2 09:23:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice
index eb28b5a..b553ac4 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_m.pxi.spice
-* Created: Fri Aug 28 09:55:31 2020
+* Created: Wed Sep 2 09:23:29 2020
*
x_PM_SKY130_FD_SC_LP__A22OI_M%B2 N_B2_c_56_n N_B2_M1007_g N_B2_M1005_g
+ N_B2_c_58_n N_B2_c_59_n N_B2_c_64_n B2 B2 B2 B2 B2 N_B2_c_61_n
diff --git a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice
index be405a5..26b821a 100644
--- a/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice
+++ b/cells/a22oi/sky130_fd_sc_lp__a22oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a22oi_m.spice
-* Created: Fri Aug 28 09:55:31 2020
+* Created: Wed Sep 2 09:23:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report
new file mode 100644
index 0000000..11bee3b
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_0.sp ('sky130_fd_sc_lp__a2bb2o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice ('sky130_fd_sc_lp__a2bb2o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_0 sky130_fd_sc_lp__a2bb2o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice
index 727e943..6b42819 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_0.pex.spice
-* Created: Fri Aug 28 09:55:38 2020
+* Created: Wed Sep 2 09:23:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice
index 0ec8364..393c1fa 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_0.pxi.spice
-* Created: Fri Aug 28 09:55:38 2020
+* Created: Wed Sep 2 09:23:36 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_0%A_59_194# N_A_59_194#_M1006_d N_A_59_194#_M1011_s
+ N_A_59_194#_c_95_n N_A_59_194#_M1003_g N_A_59_194#_c_96_n N_A_59_194#_c_97_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice
index 065870e..e8f59ee 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_0.spice
-* Created: Fri Aug 28 09:55:38 2020
+* Created: Wed Sep 2 09:23:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report
new file mode 100644
index 0000000..625a84d
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_1.sp ('sky130_fd_sc_lp__a2bb2o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice ('sky130_fd_sc_lp__a2bb2o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_1 sky130_fd_sc_lp__a2bb2o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice
index 7236112..f72732a 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_1.pex.spice
-* Created: Fri Aug 28 09:55:45 2020
+* Created: Wed Sep 2 09:23:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice
index 529ce74..9c93c02 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_1.pxi.spice
-* Created: Fri Aug 28 09:55:45 2020
+* Created: Wed Sep 2 09:23:43 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_1%A_91_269# N_A_91_269#_M1008_d N_A_91_269#_M1010_s
+ N_A_91_269#_M1011_g N_A_91_269#_M1009_g N_A_91_269#_c_92_n N_A_91_269#_c_99_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice
index 4af4a8e..a6351da 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_1.spice
-* Created: Fri Aug 28 09:55:45 2020
+* Created: Wed Sep 2 09:23:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report
new file mode 100644
index 0000000..9640b2b
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_2.sp ('sky130_fd_sc_lp__a2bb2o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice ('sky130_fd_sc_lp__a2bb2o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_2 sky130_fd_sc_lp__a2bb2o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice
index 9709120..266c727 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_2.pex.spice
-* Created: Fri Aug 28 09:55:52 2020
+* Created: Wed Sep 2 09:23:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice
index a4875f7..1776aba 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_2.pxi.spice
-* Created: Fri Aug 28 09:55:52 2020
+* Created: Wed Sep 2 09:23:49 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_2%B1 N_B1_M1001_g N_B1_c_79_n N_B1_M1013_g B1 B1 B1
+ N_B1_c_81_n PM_SKY130_FD_SC_LP__A2BB2O_2%B1
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice
index ca46a48..a0f192a 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_2.spice
-* Created: Fri Aug 28 09:55:52 2020
+* Created: Wed Sep 2 09:23:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report
new file mode 100644
index 0000000..e23aa62
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_4.sp ('sky130_fd_sc_lp__a2bb2o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice ('sky130_fd_sc_lp__a2bb2o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:23:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_4 sky130_fd_sc_lp__a2bb2o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1_N A2_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice
index 77354e8..9077895 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_4.pex.spice
-* Created: Fri Aug 28 09:56:00 2020
+* Created: Wed Sep 2 09:23:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice
index 4ed5ce1..b0b8fba 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_4.pxi.spice
-* Created: Fri Aug 28 09:56:00 2020
+* Created: Wed Sep 2 09:23:56 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_4%B1 N_B1_M1002_g N_B1_M1011_g N_B1_M1007_g
+ N_B1_M1017_g N_B1_c_130_n N_B1_c_131_n N_B1_c_138_n N_B1_c_132_n N_B1_c_133_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice
index c71d8b3..2ef0ee3 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_4.spice
-* Created: Fri Aug 28 09:56:00 2020
+* Created: Wed Sep 2 09:23:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report
new file mode 100644
index 0000000..629cba6
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_lp.sp ('sky130_fd_sc_lp__a2bb2o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice ('sky130_fd_sc_lp__a2bb2o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_lp sky130_fd_sc_lp__a2bb2o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1_N A2_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice
index b56187d..5a877e6 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_lp.pex.spice
-* Created: Fri Aug 28 09:56:07 2020
+* Created: Wed Sep 2 09:24:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice
index dcd6ca4..98c7eae 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_lp.pxi.spice
-* Created: Fri Aug 28 09:56:07 2020
+* Created: Wed Sep 2 09:24:03 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_LP%B2 N_B2_M1008_g N_B2_M1009_g N_B2_c_100_n
+ N_B2_c_105_n B2 B2 N_B2_c_102_n PM_SKY130_FD_SC_LP__A2BB2O_LP%B2
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice
index 8e7bced..18b2e92 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_lp.spice
-* Created: Fri Aug 28 09:56:07 2020
+* Created: Wed Sep 2 09:24:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report
new file mode 100644
index 0000000..2487953
--- /dev/null
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2o_m.sp ('sky130_fd_sc_lp__a2bb2o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice ('sky130_fd_sc_lp__a2bb2o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2o_m sky130_fd_sc_lp__a2bb2o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice
index ab10cf8..3026d61 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_m.pex.spice
-* Created: Fri Aug 28 09:56:20 2020
+* Created: Wed Sep 2 09:24:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice
index 4d5c6e2..da1ceab 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_m.pxi.spice
-* Created: Fri Aug 28 09:56:20 2020
+* Created: Wed Sep 2 09:24:10 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2O_M%A_85_345# N_A_85_345#_M1002_d N_A_85_345#_M1011_s
+ N_A_85_345#_M1006_g N_A_85_345#_M1000_g N_A_85_345#_c_81_n N_A_85_345#_c_82_n
diff --git a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice
index e170e5c..eba7eb1 100644
--- a/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice
+++ b/cells/a2bb2o/sky130_fd_sc_lp__a2bb2o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2o_m.spice
-* Created: Fri Aug 28 09:56:20 2020
+* Created: Wed Sep 2 09:24:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report
new file mode 100644
index 0000000..1ae2f36
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_0.sp ('sky130_fd_sc_lp__a2bb2oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice ('sky130_fd_sc_lp__a2bb2oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_0 sky130_fd_sc_lp__a2bb2oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice
index 0efb93a..a735e5e 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_0.pex.spice
-* Created: Fri Aug 28 09:56:30 2020
+* Created: Wed Sep 2 09:24:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice
index 7540d00..59a4259 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_0.pxi.spice
-* Created: Fri Aug 28 09:56:30 2020
+* Created: Wed Sep 2 09:24:16 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_0%A1_N N_A1_N_c_64_n N_A1_N_M1003_g N_A1_N_M1007_g
+ N_A1_N_c_67_n A1_N A1_N A1_N N_A1_N_c_69_n PM_SKY130_FD_SC_LP__A2BB2OI_0%A1_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice
index 49150f5..9b78f99 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_0.spice
-* Created: Fri Aug 28 09:56:30 2020
+* Created: Wed Sep 2 09:24:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report
new file mode 100644
index 0000000..131d774
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_1.sp ('sky130_fd_sc_lp__a2bb2oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice ('sky130_fd_sc_lp__a2bb2oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_1 sky130_fd_sc_lp__a2bb2oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice
index 25594b9..429405a 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_1.pex.spice
-* Created: Fri Aug 28 09:56:38 2020
+* Created: Wed Sep 2 09:24:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice
index dd963da..e106adc 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_1.pxi.spice
-* Created: Fri Aug 28 09:56:38 2020
+* Created: Wed Sep 2 09:24:22 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_1%A1_N N_A1_N_M1003_g N_A1_N_M1005_g A1_N A1_N
+ N_A1_N_c_58_n N_A1_N_c_59_n PM_SKY130_FD_SC_LP__A2BB2OI_1%A1_N
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice
index 2d04e0e..b72a7f0 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_1.spice
-* Created: Fri Aug 28 09:56:38 2020
+* Created: Wed Sep 2 09:24:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report
new file mode 100644
index 0000000..58fc338
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_2.sp ('sky130_fd_sc_lp__a2bb2oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice ('sky130_fd_sc_lp__a2bb2oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_2 sky130_fd_sc_lp__a2bb2oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1_N A2_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice
index 6aba998..90eb176 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_2.pex.spice
-* Created: Fri Aug 28 09:56:45 2020
+* Created: Wed Sep 2 09:24:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice
index fe4e198..9cf4f35 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_2.pxi.spice
-* Created: Fri Aug 28 09:56:45 2020
+* Created: Wed Sep 2 09:24:29 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_2%B1 N_B1_M1015_g N_B1_M1002_g N_B1_M1018_g
+ N_B1_M1011_g N_B1_c_108_n N_B1_c_109_n N_B1_c_114_n N_B1_c_115_n N_B1_c_110_n
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice
index 11dc4be..3397d88 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_2.spice
-* Created: Fri Aug 28 09:56:45 2020
+* Created: Wed Sep 2 09:24:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report
new file mode 100644
index 0000000..65760e1
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_4.sp ('sky130_fd_sc_lp__a2bb2oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice ('sky130_fd_sc_lp__a2bb2oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_4 sky130_fd_sc_lp__a2bb2oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1_N A2_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice
index 53a9fd2..d165cbe 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_4.pex.spice
-* Created: Fri Aug 28 09:56:52 2020
+* Created: Wed Sep 2 09:24:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice
index d2aabbc..f40e590 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_4.pxi.spice
-* Created: Fri Aug 28 09:56:52 2020
+* Created: Wed Sep 2 09:24:36 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_4%B1 N_B1_M1002_g N_B1_M1003_g N_B1_M1005_g
+ N_B1_M1013_g N_B1_M1014_g N_B1_M1025_g N_B1_M1035_g N_B1_c_164_n N_B1_M1018_g
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice
index 7570a90..b1d5533 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_4.spice
-* Created: Fri Aug 28 09:56:52 2020
+* Created: Wed Sep 2 09:24:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report
new file mode 100644
index 0000000..b3af354
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_lp.sp ('sky130_fd_sc_lp__a2bb2oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice ('sky130_fd_sc_lp__a2bb2oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_lp sky130_fd_sc_lp__a2bb2oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 4 4 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice
index f505438..b13e8fc 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_lp.pex.spice
-* Created: Fri Aug 28 09:57:00 2020
+* Created: Wed Sep 2 09:24:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice
index e1eb4e6..55ae567 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_lp.pxi.spice
-* Created: Fri Aug 28 09:57:00 2020
+* Created: Wed Sep 2 09:24:42 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_LP%B1 N_B1_M1003_g N_B1_M1010_g B1 B1 N_B1_c_82_n
+ PM_SKY130_FD_SC_LP__A2BB2OI_LP%B1
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice
index 33af1a7..272e8c8 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_lp.spice
-* Created: Fri Aug 28 09:57:00 2020
+* Created: Wed Sep 2 09:24:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report
new file mode 100644
index 0000000..0da4f8b
--- /dev/null
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a2bb2oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a2bb2oi_m.sp ('sky130_fd_sc_lp__a2bb2oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice ('sky130_fd_sc_lp__a2bb2oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a2bb2oi_m sky130_fd_sc_lp__a2bb2oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a2bb2oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a2bb2oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice
index f67651a..3d6df83 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_m.pex.spice
-* Created: Fri Aug 28 09:57:08 2020
+* Created: Wed Sep 2 09:24:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice
index d801f3c..fedcff2 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_m.pxi.spice
-* Created: Fri Aug 28 09:57:08 2020
+* Created: Wed Sep 2 09:24:49 2020
*
x_PM_SKY130_FD_SC_LP__A2BB2OI_M%A1_N N_A1_N_c_76_n N_A1_N_c_84_n N_A1_N_c_85_n
+ N_A1_N_c_77_n N_A1_N_c_78_n N_A1_N_M1007_g N_A1_N_c_79_n N_A1_N_M1005_g
diff --git a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice
index 7f0af50..411967c 100644
--- a/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice
+++ b/cells/a2bb2oi/sky130_fd_sc_lp__a2bb2oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a2bb2oi_m.spice
-* Created: Fri Aug 28 09:57:08 2020
+* Created: Wed Sep 2 09:24:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report
new file mode 100644
index 0000000..900de11
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_0.sp ('sky130_fd_sc_lp__a311o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_0.spice ('sky130_fd_sc_lp__a311o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_0 sky130_fd_sc_lp__a311o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice
index 3d9bcc5..ee02969 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_0.pex.spice
-* Created: Fri Aug 28 09:57:20 2020
+* Created: Wed Sep 2 09:24:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice
index 53c2c35..725cedb 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_0.pxi.spice
-* Created: Fri Aug 28 09:57:20 2020
+* Created: Wed Sep 2 09:24:56 2020
*
x_PM_SKY130_FD_SC_LP__A311O_0%A_72_312# N_A_72_312#_M1001_d N_A_72_312#_M1003_d
+ N_A_72_312#_M1000_d N_A_72_312#_M1006_g N_A_72_312#_M1004_g N_A_72_312#_c_96_n
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_0.spice b/cells/a311o/sky130_fd_sc_lp__a311o_0.spice
index 1200c5c..f40d956 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_0.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_0.spice
-* Created: Fri Aug 28 09:57:20 2020
+* Created: Wed Sep 2 09:24:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report
new file mode 100644
index 0000000..3af052f
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_1.sp ('sky130_fd_sc_lp__a311o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_1.spice ('sky130_fd_sc_lp__a311o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:24:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_1 sky130_fd_sc_lp__a311o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice
index e07253e..6e689f0 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_1.pex.spice
-* Created: Fri Aug 28 09:57:31 2020
+* Created: Wed Sep 2 09:25:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice
index 264bdb8..26eeccb 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_1.pxi.spice
-* Created: Fri Aug 28 09:57:31 2020
+* Created: Wed Sep 2 09:25:02 2020
*
x_PM_SKY130_FD_SC_LP__A311O_1%A_80_21# N_A_80_21#_M1002_d N_A_80_21#_M1008_d
+ N_A_80_21#_M1010_d N_A_80_21#_c_58_n N_A_80_21#_M1004_g N_A_80_21#_M1003_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_1.spice b/cells/a311o/sky130_fd_sc_lp__a311o_1.spice
index cf7391c..5813fcf 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_1.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_1.spice
-* Created: Fri Aug 28 09:57:31 2020
+* Created: Wed Sep 2 09:25:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report
new file mode 100644
index 0000000..4d0ffa8
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_2.sp ('sky130_fd_sc_lp__a311o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_2.spice ('sky130_fd_sc_lp__a311o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_2 sky130_fd_sc_lp__a311o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice
index 777c6f7..897588f 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_2.pex.spice
-* Created: Fri Aug 28 09:57:38 2020
+* Created: Wed Sep 2 09:25:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice
index 0442230..82655af 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_2.pxi.spice
-* Created: Fri Aug 28 09:57:38 2020
+* Created: Wed Sep 2 09:25:08 2020
*
x_PM_SKY130_FD_SC_LP__A311O_2%A_85_21# N_A_85_21#_M1000_d N_A_85_21#_M1008_d
+ N_A_85_21#_M1002_d N_A_85_21#_c_67_n N_A_85_21#_M1012_g N_A_85_21#_M1001_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_2.spice b/cells/a311o/sky130_fd_sc_lp__a311o_2.spice
index c572934..33cd6b9 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_2.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_2.spice
-* Created: Fri Aug 28 09:57:38 2020
+* Created: Wed Sep 2 09:25:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report
new file mode 100644
index 0000000..13ce9ac
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_4.sp ('sky130_fd_sc_lp__a311o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_4.spice ('sky130_fd_sc_lp__a311o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_4 sky130_fd_sc_lp__a311o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice
index 68e5a1f..486ae7f 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_4.pex.spice
-* Created: Fri Aug 28 09:57:45 2020
+* Created: Wed Sep 2 09:25:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice
index f1b45ea..ac8c6fe 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_4.pxi.spice
-* Created: Fri Aug 28 09:57:45 2020
+* Created: Wed Sep 2 09:25:14 2020
*
x_PM_SKY130_FD_SC_LP__A311O_4%C1 N_C1_M1002_g N_C1_M1013_g N_C1_M1010_g
+ N_C1_M1026_g C1 C1 N_C1_c_138_n PM_SKY130_FD_SC_LP__A311O_4%C1
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_4.spice b/cells/a311o/sky130_fd_sc_lp__a311o_4.spice
index e705274..a794ef1 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_4.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_4.spice
-* Created: Fri Aug 28 09:57:45 2020
+* Created: Wed Sep 2 09:25:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report
new file mode 100644
index 0000000..ca7da62
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_lp.sp ('sky130_fd_sc_lp__a311o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice ('sky130_fd_sc_lp__a311o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_lp sky130_fd_sc_lp__a311o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 18 18
+
+ Instances: 9 9 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice
index 85c1f3d..2ec71dd 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_lp.pex.spice
-* Created: Fri Aug 28 09:57:52 2020
+* Created: Wed Sep 2 09:25:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice
index a342e77..90fb810 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_lp.pxi.spice
-* Created: Fri Aug 28 09:57:52 2020
+* Created: Wed Sep 2 09:25:20 2020
*
x_PM_SKY130_FD_SC_LP__A311O_LP%A_85_21# N_A_85_21#_M1002_d N_A_85_21#_M1013_d
+ N_A_85_21#_M1009_d N_A_85_21#_M1014_g N_A_85_21#_c_107_n N_A_85_21#_M1006_g
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice b/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice
index 4473012..a01cafa 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_lp.spice
-* Created: Fri Aug 28 09:57:52 2020
+* Created: Wed Sep 2 09:25:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report b/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report
new file mode 100644
index 0000000..66c916d
--- /dev/null
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311o_m.sp ('sky130_fd_sc_lp__a311o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311o/sky130_fd_sc_lp__a311o_m.spice ('sky130_fd_sc_lp__a311o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311o_m sky130_fd_sc_lp__a311o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a311o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice
index d9b617c..94c645f 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_m.pex.spice
-* Created: Fri Aug 28 09:57:59 2020
+* Created: Wed Sep 2 09:25:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice
index 030a429..d7869de 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_m.pxi.spice
-* Created: Fri Aug 28 09:57:59 2020
+* Created: Wed Sep 2 09:25:27 2020
*
x_PM_SKY130_FD_SC_LP__A311O_M%A3 N_A3_M1011_g N_A3_c_78_n N_A3_M1006_g
+ N_A3_c_79_n A3 A3 A3 N_A3_c_81_n N_A3_c_82_n PM_SKY130_FD_SC_LP__A311O_M%A3
diff --git a/cells/a311o/sky130_fd_sc_lp__a311o_m.spice b/cells/a311o/sky130_fd_sc_lp__a311o_m.spice
index c4f287a..d3b9f5e 100644
--- a/cells/a311o/sky130_fd_sc_lp__a311o_m.spice
+++ b/cells/a311o/sky130_fd_sc_lp__a311o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311o_m.spice
-* Created: Fri Aug 28 09:57:59 2020
+* Created: Wed Sep 2 09:25:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report
new file mode 100644
index 0000000..1e7d7f7
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_0.sp ('sky130_fd_sc_lp__a311oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice ('sky130_fd_sc_lp__a311oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_0 sky130_fd_sc_lp__a311oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice
index 2dd8fe4..291c74e 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_0.pex.spice
-* Created: Fri Aug 28 09:58:07 2020
+* Created: Wed Sep 2 09:25:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice
index afdbe6e..979ba3b 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_0.pxi.spice
-* Created: Fri Aug 28 09:58:07 2020
+* Created: Wed Sep 2 09:25:33 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_0%A3 N_A3_c_80_n N_A3_M1000_g N_A3_c_73_n
+ N_A3_M1006_g N_A3_c_74_n N_A3_c_75_n N_A3_c_76_n N_A3_c_77_n N_A3_c_83_n A3 A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice
index c649c1f..ab979fa 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_0.spice
-* Created: Fri Aug 28 09:58:07 2020
+* Created: Wed Sep 2 09:25:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report
new file mode 100644
index 0000000..cf91268
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_1.sp ('sky130_fd_sc_lp__a311oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice ('sky130_fd_sc_lp__a311oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_1 sky130_fd_sc_lp__a311oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice
index 242f81c..c7199ba 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_1.pex.spice
-* Created: Fri Aug 28 09:58:14 2020
+* Created: Wed Sep 2 09:25:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice
index 9f03695..fb8c26f 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_1.pxi.spice
-* Created: Fri Aug 28 09:58:14 2020
+* Created: Wed Sep 2 09:25:40 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_1%A3 N_A3_M1003_g N_A3_M1009_g A3 A3 N_A3_c_53_n
+ N_A3_c_54_n PM_SKY130_FD_SC_LP__A311OI_1%A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice
index 5baa005..b36f9da 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_1.spice
-* Created: Fri Aug 28 09:58:14 2020
+* Created: Wed Sep 2 09:25:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report
new file mode 100644
index 0000000..08be8a9
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_2.sp ('sky130_fd_sc_lp__a311oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice ('sky130_fd_sc_lp__a311oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_2 sky130_fd_sc_lp__a311oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice
index 5cf3643..5d871af 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_2.pex.spice
-* Created: Fri Aug 28 09:58:26 2020
+* Created: Wed Sep 2 09:25:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice
index 93eb85c..78dacd0 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_2.pxi.spice
-* Created: Fri Aug 28 09:58:26 2020
+* Created: Wed Sep 2 09:25:46 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_2%A3 N_A3_M1014_g N_A3_M1013_g N_A3_M1015_g
+ N_A3_M1018_g N_A3_c_102_n A3 N_A3_c_103_n N_A3_c_104_n
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice
index ad35922..50d9d91 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_2.spice
-* Created: Fri Aug 28 09:58:26 2020
+* Created: Wed Sep 2 09:25:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report
new file mode 100644
index 0000000..47a17da
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_4.sp ('sky130_fd_sc_lp__a311oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice ('sky130_fd_sc_lp__a311oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_4 sky130_fd_sc_lp__a311oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice
index c68540c..a8cc74d 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_4.pex.spice
-* Created: Fri Aug 28 09:58:36 2020
+* Created: Wed Sep 2 09:25:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice
index 4c4403a..4012a6c 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_4.pxi.spice
-* Created: Fri Aug 28 09:58:36 2020
+* Created: Wed Sep 2 09:25:52 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_4%A3 N_A3_c_151_n N_A3_M1012_g N_A3_M1008_g
+ N_A3_c_153_n N_A3_M1022_g N_A3_M1023_g N_A3_c_155_n N_A3_M1024_g N_A3_M1026_g
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice
index 59409bb..d2dedef 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_4.spice
-* Created: Fri Aug 28 09:58:36 2020
+* Created: Wed Sep 2 09:25:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report
new file mode 100644
index 0000000..9919d18
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_lp.sp ('sky130_fd_sc_lp__a311oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice ('sky130_fd_sc_lp__a311oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:25:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_lp sky130_fd_sc_lp__a311oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice
index a71057c..a106147 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_lp.pex.spice
-* Created: Fri Aug 28 09:58:44 2020
+* Created: Wed Sep 2 09:25:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice
index 11a2a88..4b01f0d 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_lp.pxi.spice
-* Created: Fri Aug 28 09:58:44 2020
+* Created: Wed Sep 2 09:25:59 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_LP%A1 N_A1_c_78_n N_A1_M1001_g N_A1_M1006_g
+ N_A1_c_75_n A1 N_A1_c_76_n N_A1_c_77_n PM_SKY130_FD_SC_LP__A311OI_LP%A1
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice
index c1c8906..e01b969 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_lp.spice
-* Created: Fri Aug 28 09:58:44 2020
+* Created: Wed Sep 2 09:25:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report
new file mode 100644
index 0000000..57c608d
--- /dev/null
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a311oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a311oi_m.sp ('sky130_fd_sc_lp__a311oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice ('sky130_fd_sc_lp__a311oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a311oi_m sky130_fd_sc_lp__a311oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a311oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a311oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice
index a2fbe28..a3dceca 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_m.pex.spice
-* Created: Fri Aug 28 09:58:51 2020
+* Created: Wed Sep 2 09:26:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice
index bcf46a3..acd5e47 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_m.pxi.spice
-* Created: Fri Aug 28 09:58:51 2020
+* Created: Wed Sep 2 09:26:05 2020
*
x_PM_SKY130_FD_SC_LP__A311OI_M%A3 N_A3_c_77_n N_A3_c_84_n N_A3_c_85_n
+ N_A3_M1006_g N_A3_c_78_n N_A3_M1001_g N_A3_c_79_n N_A3_c_80_n A3 A3 A3 A3 A3
diff --git a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice
index ca58b46..3be5c00 100644
--- a/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice
+++ b/cells/a311oi/sky130_fd_sc_lp__a311oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a311oi_m.spice
-* Created: Fri Aug 28 09:58:51 2020
+* Created: Wed Sep 2 09:26:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report
new file mode 100644
index 0000000..a115a58
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_0.sp ('sky130_fd_sc_lp__a31o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_0.spice ('sky130_fd_sc_lp__a31o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_0 sky130_fd_sc_lp__a31o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice
index 1e0fbf7..f920011 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_0.pex.spice
-* Created: Fri Aug 28 09:58:58 2020
+* Created: Wed Sep 2 09:26:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice
index 7429ce6..a55fc19 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_0.pxi.spice
-* Created: Fri Aug 28 09:58:58 2020
+* Created: Wed Sep 2 09:26:12 2020
*
x_PM_SKY130_FD_SC_LP__A31O_0%A_86_241# N_A_86_241#_M1009_d N_A_86_241#_M1007_d
+ N_A_86_241#_M1005_g N_A_86_241#_M1004_g N_A_86_241#_c_70_n N_A_86_241#_c_78_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_0.spice b/cells/a31o/sky130_fd_sc_lp__a31o_0.spice
index 90ea4b9..5cf3422 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_0.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_0.spice
-* Created: Fri Aug 28 09:58:58 2020
+* Created: Wed Sep 2 09:26:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report
new file mode 100644
index 0000000..4d5062b
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_1.sp ('sky130_fd_sc_lp__a31o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_1.spice ('sky130_fd_sc_lp__a31o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_1 sky130_fd_sc_lp__a31o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice
index 86efb77..20747e0 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_1.pex.spice
-* Created: Fri Aug 28 09:59:05 2020
+* Created: Wed Sep 2 09:26:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice
index 4aaf966..0fa53dc 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_1.pxi.spice
-* Created: Fri Aug 28 09:59:05 2020
+* Created: Wed Sep 2 09:26:18 2020
*
x_PM_SKY130_FD_SC_LP__A31O_1%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1006_d
+ N_A_80_21#_M1004_g N_A_80_21#_M1001_g N_A_80_21#_c_54_n N_A_80_21#_c_55_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_1.spice b/cells/a31o/sky130_fd_sc_lp__a31o_1.spice
index 8f3a866..a74a798 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_1.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_1.spice
-* Created: Fri Aug 28 09:59:05 2020
+* Created: Wed Sep 2 09:26:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report
new file mode 100644
index 0000000..9767701
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_2.sp ('sky130_fd_sc_lp__a31o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_2.spice ('sky130_fd_sc_lp__a31o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_2 sky130_fd_sc_lp__a31o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice
index fb6fae8..49b3489 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_2.pex.spice
-* Created: Fri Aug 28 09:59:12 2020
+* Created: Wed Sep 2 09:26:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice
index 8d7615b..fa831d0 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_2.pxi.spice
-* Created: Fri Aug 28 09:59:12 2020
+* Created: Wed Sep 2 09:26:24 2020
*
x_PM_SKY130_FD_SC_LP__A31O_2%A_85_23# N_A_85_23#_M1011_d N_A_85_23#_M1010_d
+ N_A_85_23#_M1008_g N_A_85_23#_M1002_g N_A_85_23#_c_60_n N_A_85_23#_M1009_g
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_2.spice b/cells/a31o/sky130_fd_sc_lp__a31o_2.spice
index c4c9ab1..98231a0 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_2.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_2.spice
-* Created: Fri Aug 28 09:59:12 2020
+* Created: Wed Sep 2 09:26:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report
new file mode 100644
index 0000000..8d82e1c
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_4.sp ('sky130_fd_sc_lp__a31o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_4.spice ('sky130_fd_sc_lp__a31o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_4 sky130_fd_sc_lp__a31o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice
index b4ce02a..c633a04 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_4.pex.spice
-* Created: Fri Aug 28 09:59:19 2020
+* Created: Wed Sep 2 09:26:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice
index 800ecb3..9cf9375 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_4.pxi.spice
-* Created: Fri Aug 28 09:59:19 2020
+* Created: Wed Sep 2 09:26:31 2020
*
x_PM_SKY130_FD_SC_LP__A31O_4%B1 N_B1_M1009_g N_B1_M1011_g N_B1_c_115_n
+ N_B1_M1016_g N_B1_M1022_g N_B1_c_118_n B1 B1 N_B1_c_120_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_4.spice b/cells/a31o/sky130_fd_sc_lp__a31o_4.spice
index c2da5dc..b90c4f6 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_4.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_4.spice
-* Created: Fri Aug 28 09:59:19 2020
+* Created: Wed Sep 2 09:26:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report
new file mode 100644
index 0000000..15823c0
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_lp.sp ('sky130_fd_sc_lp__a31o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice ('sky130_fd_sc_lp__a31o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_lp sky130_fd_sc_lp__a31o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice
index a021451..c206d04 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_lp.pex.spice
-* Created: Fri Aug 28 09:59:32 2020
+* Created: Wed Sep 2 09:26:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice
index 424a0f7..86769cf 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_lp.pxi.spice
-* Created: Fri Aug 28 09:59:32 2020
+* Created: Wed Sep 2 09:26:37 2020
*
x_PM_SKY130_FD_SC_LP__A31O_LP%B1 N_B1_c_73_n N_B1_M1007_g N_B1_c_74_n
+ N_B1_M1003_g N_B1_M1005_g N_B1_c_76_n B1 N_B1_c_78_n
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice b/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice
index 9c9804e..4ef587d 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_lp.spice
-* Created: Fri Aug 28 09:59:32 2020
+* Created: Wed Sep 2 09:26:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report b/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report
new file mode 100644
index 0000000..9fff71d
--- /dev/null
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31o_m.sp ('sky130_fd_sc_lp__a31o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31o/sky130_fd_sc_lp__a31o_m.spice ('sky130_fd_sc_lp__a31o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31o_m sky130_fd_sc_lp__a31o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a31o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice
index 7bdc7bb..72004c1 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_m.pex.spice
-* Created: Fri Aug 28 09:59:43 2020
+* Created: Wed Sep 2 09:26:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice
index 354d95e..10ab630 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_m.pxi.spice
-* Created: Fri Aug 28 09:59:43 2020
+* Created: Wed Sep 2 09:26:43 2020
*
x_PM_SKY130_FD_SC_LP__A31O_M%A_86_172# N_A_86_172#_M1001_d N_A_86_172#_M1007_d
+ N_A_86_172#_c_86_n N_A_86_172#_c_98_n N_A_86_172#_c_99_n N_A_86_172#_M1005_g
diff --git a/cells/a31o/sky130_fd_sc_lp__a31o_m.spice b/cells/a31o/sky130_fd_sc_lp__a31o_m.spice
index 7c298c3..0c47407 100644
--- a/cells/a31o/sky130_fd_sc_lp__a31o_m.spice
+++ b/cells/a31o/sky130_fd_sc_lp__a31o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31o_m.spice
-* Created: Fri Aug 28 09:59:43 2020
+* Created: Wed Sep 2 09:26:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report
new file mode 100644
index 0000000..c10e229
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_0.sp ('sky130_fd_sc_lp__a31oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice ('sky130_fd_sc_lp__a31oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_0 sky130_fd_sc_lp__a31oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice
index 4bc7c1c..b0352f7 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_0.pex.spice
-* Created: Fri Aug 28 09:59:51 2020
+* Created: Wed Sep 2 09:26:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice
index a80937e..a942584 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_0.pxi.spice
-* Created: Fri Aug 28 09:59:51 2020
+* Created: Wed Sep 2 09:26:50 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_0%A3 N_A3_c_55_n N_A3_M1005_g N_A3_c_56_n
+ N_A3_M1002_g N_A3_c_57_n N_A3_c_58_n N_A3_c_63_n A3 A3 A3 N_A3_c_60_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice
index 943cab1..064b41c 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_0.spice
-* Created: Fri Aug 28 09:59:51 2020
+* Created: Wed Sep 2 09:26:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report
new file mode 100644
index 0000000..0e09e10
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_1.sp ('sky130_fd_sc_lp__a31oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice ('sky130_fd_sc_lp__a31oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_1 sky130_fd_sc_lp__a31oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice
index 3a8b1b8..7e5c9f5 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_1.pex.spice
-* Created: Fri Aug 28 09:59:58 2020
+* Created: Wed Sep 2 09:26:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice
index 93cbd4f..376496a 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_1.pxi.spice
-* Created: Fri Aug 28 09:59:58 2020
+* Created: Wed Sep 2 09:26:56 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_1%A3 N_A3_M1003_g N_A3_M1000_g A3 A3 N_A3_c_47_n
+ PM_SKY130_FD_SC_LP__A31OI_1%A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice
index c8c69e5..dd02abf 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_1.spice
-* Created: Fri Aug 28 09:59:58 2020
+* Created: Wed Sep 2 09:26:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report
new file mode 100644
index 0000000..9588e61
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_2.sp ('sky130_fd_sc_lp__a31oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice ('sky130_fd_sc_lp__a31oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:26:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_2 sky130_fd_sc_lp__a31oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice
index 11e181d..184932f 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_2.pex.spice
-* Created: Fri Aug 28 10:00:05 2020
+* Created: Wed Sep 2 09:27:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice
index 8da6964..ddac9ad 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_2.pxi.spice
-* Created: Fri Aug 28 10:00:05 2020
+* Created: Wed Sep 2 09:27:02 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_2%A3 N_A3_c_81_n N_A3_M1009_g N_A3_M1005_g
+ N_A3_c_83_n N_A3_c_84_n N_A3_M1012_g N_A3_M1014_g N_A3_c_86_n A3 N_A3_c_88_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice
index f5b0160..b77750d 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_2.spice
-* Created: Fri Aug 28 10:00:05 2020
+* Created: Wed Sep 2 09:27:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report
new file mode 100644
index 0000000..0aa3ef4
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_4.sp ('sky130_fd_sc_lp__a31oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice ('sky130_fd_sc_lp__a31oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_4 sky130_fd_sc_lp__a31oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice
index 61f3b56..cbffec7 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_4.pex.spice
-* Created: Fri Aug 28 10:00:13 2020
+* Created: Wed Sep 2 09:27:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice
index 2ab50f5..04a9429 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_4.pxi.spice
-* Created: Fri Aug 28 10:00:13 2020
+* Created: Wed Sep 2 09:27:09 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_4%A3 N_A3_M1011_g N_A3_M1010_g N_A3_M1023_g
+ N_A3_M1021_g N_A3_M1027_g N_A3_M1022_g N_A3_M1029_g N_A3_M1030_g A3 A3 A3 A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice
index dcd5fc2..102fdf6 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_4.spice
-* Created: Fri Aug 28 10:00:13 2020
+* Created: Wed Sep 2 09:27:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report
new file mode 100644
index 0000000..99d9e43
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_lp.sp ('sky130_fd_sc_lp__a31oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice ('sky130_fd_sc_lp__a31oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_lp sky130_fd_sc_lp__a31oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice
index 351b9fc..afcee2c 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_lp.pex.spice
-* Created: Fri Aug 28 10:00:20 2020
+* Created: Wed Sep 2 09:27:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice
index 6fa0c9d..df42985 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_lp.pxi.spice
-* Created: Fri Aug 28 10:00:20 2020
+* Created: Wed Sep 2 09:27:15 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_LP%A3 N_A3_M1007_g N_A3_c_63_n N_A3_M1002_g
+ N_A3_c_64_n N_A3_c_65_n N_A3_c_66_n N_A3_c_67_n A3 A3 N_A3_c_68_n N_A3_c_69_n
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice
index 66cb2d5..3813cc8 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_lp.spice
-* Created: Fri Aug 28 10:00:20 2020
+* Created: Wed Sep 2 09:27:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report
new file mode 100644
index 0000000..104e491
--- /dev/null
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a31oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a31oi_m.sp ('sky130_fd_sc_lp__a31oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice ('sky130_fd_sc_lp__a31oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a31oi_m sky130_fd_sc_lp__a31oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a31oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a31oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice
index 2e180bb..7d5cbaf 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_m.pex.spice
-* Created: Fri Aug 28 10:00:34 2020
+* Created: Wed Sep 2 09:27:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice
index 1bd6e28..f21bd56 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_m.pxi.spice
-* Created: Fri Aug 28 10:00:34 2020
+* Created: Wed Sep 2 09:27:21 2020
*
x_PM_SKY130_FD_SC_LP__A31OI_M%A3 N_A3_c_63_n N_A3_c_64_n N_A3_c_65_n N_A3_c_71_n
+ N_A3_c_72_n N_A3_c_73_n N_A3_M1007_g N_A3_c_66_n N_A3_M1006_g N_A3_c_67_n A3
diff --git a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice
index 836a46c..acc5888 100644
--- a/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice
+++ b/cells/a31oi/sky130_fd_sc_lp__a31oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a31oi_m.spice
-* Created: Fri Aug 28 10:00:34 2020
+* Created: Wed Sep 2 09:27:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report
new file mode 100644
index 0000000..0a2a7b5
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_0.sp ('sky130_fd_sc_lp__a32o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_0.spice ('sky130_fd_sc_lp__a32o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_0 sky130_fd_sc_lp__a32o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice
index 9d8b5c8..9fc3635 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_0.pex.spice
-* Created: Fri Aug 28 10:00:47 2020
+* Created: Wed Sep 2 09:27:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice
index bca2b76..d0d6568 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_0.pxi.spice
-* Created: Fri Aug 28 10:00:47 2020
+* Created: Wed Sep 2 09:27:28 2020
*
x_PM_SKY130_FD_SC_LP__A32O_0%A_80_21# N_A_80_21#_M1007_d N_A_80_21#_M1001_d
+ N_A_80_21#_M1005_g N_A_80_21#_M1009_g N_A_80_21#_c_79_n N_A_80_21#_c_88_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_0.spice b/cells/a32o/sky130_fd_sc_lp__a32o_0.spice
index b3c5ac9..be6453e 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_0.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_0.spice
-* Created: Fri Aug 28 10:00:47 2020
+* Created: Wed Sep 2 09:27:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report
new file mode 100644
index 0000000..a8e7294
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_1.sp ('sky130_fd_sc_lp__a32o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_1.spice ('sky130_fd_sc_lp__a32o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_1 sky130_fd_sc_lp__a32o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice
index 4c32106..f297580 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_1.pex.spice
-* Created: Fri Aug 28 10:00:55 2020
+* Created: Wed Sep 2 09:27:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice
index 8c27af8..7dd468c 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_1.pxi.spice
-* Created: Fri Aug 28 10:00:55 2020
+* Created: Wed Sep 2 09:27:34 2020
*
x_PM_SKY130_FD_SC_LP__A32O_1%A_80_21# N_A_80_21#_M1004_d N_A_80_21#_M1003_d
+ N_A_80_21#_c_55_n N_A_80_21#_M1006_g N_A_80_21#_M1005_g N_A_80_21#_c_57_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_1.spice b/cells/a32o/sky130_fd_sc_lp__a32o_1.spice
index 6c2bfab..d317f16 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_1.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_1.spice
-* Created: Fri Aug 28 10:00:55 2020
+* Created: Wed Sep 2 09:27:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report
new file mode 100644
index 0000000..9fa1a26
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_2.sp ('sky130_fd_sc_lp__a32o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_2.spice ('sky130_fd_sc_lp__a32o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_2 sky130_fd_sc_lp__a32o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice
index 8625ad6..370627b 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_2.pex.spice
-* Created: Fri Aug 28 10:01:02 2020
+* Created: Wed Sep 2 09:27:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice
index 4fe68b4..a74d474 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_2.pxi.spice
-* Created: Fri Aug 28 10:01:02 2020
+* Created: Wed Sep 2 09:27:41 2020
*
x_PM_SKY130_FD_SC_LP__A32O_2%A_108_267# N_A_108_267#_M1010_d
+ N_A_108_267#_M1008_d N_A_108_267#_M1005_g N_A_108_267#_M1001_g
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_2.spice b/cells/a32o/sky130_fd_sc_lp__a32o_2.spice
index b2d9087..31acaa4 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_2.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_2.spice
-* Created: Fri Aug 28 10:01:02 2020
+* Created: Wed Sep 2 09:27:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report
new file mode 100644
index 0000000..2b66d9b
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_4.sp ('sky130_fd_sc_lp__a32o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_4.spice ('sky130_fd_sc_lp__a32o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_4 sky130_fd_sc_lp__a32o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice
index 81cd51a..106f11d 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_4.pex.spice
-* Created: Fri Aug 28 10:01:09 2020
+* Created: Wed Sep 2 09:27:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice
index 5fa5c54..819c632 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_4.pxi.spice
-* Created: Fri Aug 28 10:01:09 2020
+* Created: Wed Sep 2 09:27:48 2020
*
x_PM_SKY130_FD_SC_LP__A32O_4%A_101_21# N_A_101_21#_M1015_d N_A_101_21#_M1009_d
+ N_A_101_21#_M1024_d N_A_101_21#_M1003_s N_A_101_21#_M1004_g
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_4.spice b/cells/a32o/sky130_fd_sc_lp__a32o_4.spice
index 52f8779..c410e50 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_4.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_4.spice
-* Created: Fri Aug 28 10:01:09 2020
+* Created: Wed Sep 2 09:27:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report
new file mode 100644
index 0000000..ec77a33
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_lp.sp ('sky130_fd_sc_lp__a32o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice ('sky130_fd_sc_lp__a32o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_lp sky130_fd_sc_lp__a32o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice
index a641692..da571a2 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_lp.pex.spice
-* Created: Fri Aug 28 10:01:16 2020
+* Created: Wed Sep 2 09:27:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice
index 76a3a24..976ec49 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_lp.pxi.spice
-* Created: Fri Aug 28 10:01:16 2020
+* Created: Wed Sep 2 09:27:55 2020
*
x_PM_SKY130_FD_SC_LP__A32O_LP%B2 N_B2_M1006_g N_B2_M1001_g N_B2_c_76_n
+ N_B2_c_77_n N_B2_c_82_n B2 N_B2_c_78_n N_B2_c_79_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice b/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice
index f556eff..7dd8db3 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_lp.spice
-* Created: Fri Aug 28 10:01:16 2020
+* Created: Wed Sep 2 09:27:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report b/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report
new file mode 100644
index 0000000..20c162e
--- /dev/null
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32o_m.sp ('sky130_fd_sc_lp__a32o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32o/sky130_fd_sc_lp__a32o_m.spice ('sky130_fd_sc_lp__a32o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:27:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32o_m sky130_fd_sc_lp__a32o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a32o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A3 A2 A1 B1 B2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice
index a39f461..0425673 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_m.pex.spice
-* Created: Fri Aug 28 10:01:23 2020
+* Created: Wed Sep 2 09:28:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice
index 1cfe5a6..dc21efd 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_m.pxi.spice
-* Created: Fri Aug 28 10:01:23 2020
+* Created: Wed Sep 2 09:28:01 2020
*
x_PM_SKY130_FD_SC_LP__A32O_M%A_84_153# N_A_84_153#_M1007_d N_A_84_153#_M1002_d
+ N_A_84_153#_M1001_g N_A_84_153#_M1006_g N_A_84_153#_c_71_n N_A_84_153#_c_72_n
diff --git a/cells/a32o/sky130_fd_sc_lp__a32o_m.spice b/cells/a32o/sky130_fd_sc_lp__a32o_m.spice
index 7c800ef..695209e 100644
--- a/cells/a32o/sky130_fd_sc_lp__a32o_m.spice
+++ b/cells/a32o/sky130_fd_sc_lp__a32o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32o_m.spice
-* Created: Fri Aug 28 10:01:23 2020
+* Created: Wed Sep 2 09:28:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report
new file mode 100644
index 0000000..20a25e6
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_0.sp ('sky130_fd_sc_lp__a32oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice ('sky130_fd_sc_lp__a32oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_0 sky130_fd_sc_lp__a32oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice
index d93b899..5f21012 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_0.pex.spice
-* Created: Fri Aug 28 10:01:30 2020
+* Created: Wed Sep 2 09:28:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice
index 5b84e7e..02b4a41 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_0.pxi.spice
-* Created: Fri Aug 28 10:01:30 2020
+* Created: Wed Sep 2 09:28:08 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_0%B2 N_B2_M1001_g N_B2_M1005_g N_B2_c_71_n
+ N_B2_c_72_n B2 B2 B2 N_B2_c_74_n PM_SKY130_FD_SC_LP__A32OI_0%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice
index 6cd7de9..2dd2a12 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_0.spice
-* Created: Fri Aug 28 10:01:30 2020
+* Created: Wed Sep 2 09:28:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report
new file mode 100644
index 0000000..44948bc
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_1.sp ('sky130_fd_sc_lp__a32oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice ('sky130_fd_sc_lp__a32oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_1 sky130_fd_sc_lp__a32oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice
index 7bddeb9..6c4f609 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_1.pex.spice
-* Created: Fri Aug 28 10:01:37 2020
+* Created: Wed Sep 2 09:28:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice
index 5b5a7d9..4a0f375 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_1.pxi.spice
-* Created: Fri Aug 28 10:01:37 2020
+* Created: Wed Sep 2 09:28:14 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_1%B2 N_B2_c_50_n N_B2_M1006_g N_B2_M1000_g B2 B2
+ N_B2_c_53_n PM_SKY130_FD_SC_LP__A32OI_1%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice
index ce86ec4..37f0c75 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_1.spice
-* Created: Fri Aug 28 10:01:37 2020
+* Created: Wed Sep 2 09:28:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report
new file mode 100644
index 0000000..9c225a0
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_2.sp ('sky130_fd_sc_lp__a32oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice ('sky130_fd_sc_lp__a32oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_2 sky130_fd_sc_lp__a32oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice
index 84b5856..fc60a52 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_2.pex.spice
-* Created: Fri Aug 28 10:01:53 2020
+* Created: Wed Sep 2 09:28:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice
index 1ea6be7..efb5e47 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_2.pxi.spice
-* Created: Fri Aug 28 10:01:53 2020
+* Created: Wed Sep 2 09:28:21 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_2%B2 N_B2_c_91_n N_B2_M1012_g N_B2_M1005_g
+ N_B2_c_93_n N_B2_M1013_g N_B2_M1011_g N_B2_c_95_n B2 B2 N_B2_c_97_n
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice
index f4b2e60..5b99089 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_2.spice
-* Created: Fri Aug 28 10:01:53 2020
+* Created: Wed Sep 2 09:28:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report
new file mode 100644
index 0000000..773ed4d
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_4.sp ('sky130_fd_sc_lp__a32oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice ('sky130_fd_sc_lp__a32oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_4 sky130_fd_sc_lp__a32oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice
index ae9a31b..5e48cf4 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_4.pex.spice
-* Created: Fri Aug 28 10:02:01 2020
+* Created: Wed Sep 2 09:28:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice
index 2108e89..3d99d5d 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_4.pxi.spice
-* Created: Fri Aug 28 10:02:01 2020
+* Created: Wed Sep 2 09:28:28 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_4%B2 N_B2_c_134_n N_B2_M1002_g N_B2_M1006_g
+ N_B2_c_136_n N_B2_M1013_g N_B2_M1020_g N_B2_c_138_n N_B2_M1016_g N_B2_M1021_g
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice
index 29cf9c2..c0b35b6 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_4.spice
-* Created: Fri Aug 28 10:02:01 2020
+* Created: Wed Sep 2 09:28:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report
new file mode 100644
index 0000000..16cf462
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_lp.sp ('sky130_fd_sc_lp__a32oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice ('sky130_fd_sc_lp__a32oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_lp sky130_fd_sc_lp__a32oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice
index c201716..753d05c 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_lp.pex.spice
-* Created: Fri Aug 28 10:02:08 2020
+* Created: Wed Sep 2 09:28:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice
index 656d27b..1d4ad5b 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_lp.pxi.spice
-* Created: Fri Aug 28 10:02:08 2020
+* Created: Wed Sep 2 09:28:34 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_LP%B2 N_B2_M1008_g N_B2_c_68_n N_B2_M1005_g
+ N_B2_c_69_n B2 B2 N_B2_c_71_n PM_SKY130_FD_SC_LP__A32OI_LP%B2
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice
index a3c8d17..274a18b 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_lp.spice
-* Created: Fri Aug 28 10:02:08 2020
+* Created: Wed Sep 2 09:28:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report
new file mode 100644
index 0000000..589031f
--- /dev/null
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a32oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a32oi_m.sp ('sky130_fd_sc_lp__a32oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice ('sky130_fd_sc_lp__a32oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a32oi_m sky130_fd_sc_lp__a32oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a32oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a32oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SPMP_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SPMP_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A1 A2 A3 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice
index c9bd445..cc968da 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_m.pex.spice
-* Created: Fri Aug 28 10:02:15 2020
+* Created: Wed Sep 2 09:28:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice
index 6b0e149..a7175e2 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_m.pxi.spice
-* Created: Fri Aug 28 10:02:15 2020
+* Created: Wed Sep 2 09:28:41 2020
*
x_PM_SKY130_FD_SC_LP__A32OI_M%B2 N_B2_c_71_n N_B2_c_72_n N_B2_c_73_n
+ N_B2_M1000_g N_B2_M1009_g N_B2_c_75_n N_B2_c_80_n B2 B2 B2 B2 B2 N_B2_c_77_n
diff --git a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice
index ecbf7c6..fd0b9d7 100644
--- a/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice
+++ b/cells/a32oi/sky130_fd_sc_lp__a32oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a32oi_m.spice
-* Created: Fri Aug 28 10:02:15 2020
+* Created: Wed Sep 2 09:28:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report
new file mode 100644
index 0000000..8d77600
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_0.sp ('sky130_fd_sc_lp__a41o_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_0.spice ('sky130_fd_sc_lp__a41o_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_0 sky130_fd_sc_lp__a41o_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice
index 506c887..27263f9 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_0.pex.spice
-* Created: Fri Aug 28 10:02:23 2020
+* Created: Wed Sep 2 09:28:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice
index 1bc7286..9f83fcf 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_0.pxi.spice
-* Created: Fri Aug 28 10:02:23 2020
+* Created: Wed Sep 2 09:28:48 2020
*
x_PM_SKY130_FD_SC_LP__A41O_0%A_80_309# N_A_80_309#_M1006_d N_A_80_309#_M1008_s
+ N_A_80_309#_c_100_n N_A_80_309#_M1001_g N_A_80_309#_M1002_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_0.spice b/cells/a41o/sky130_fd_sc_lp__a41o_0.spice
index af3146a..afc1e24 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_0.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_0.spice
-* Created: Fri Aug 28 10:02:23 2020
+* Created: Wed Sep 2 09:28:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report
new file mode 100644
index 0000000..16cfda2
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_1.sp ('sky130_fd_sc_lp__a41o_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_1.spice ('sky130_fd_sc_lp__a41o_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_1 sky130_fd_sc_lp__a41o_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice
index b2e75dd..64f2803 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_1.pex.spice
-* Created: Fri Aug 28 10:02:30 2020
+* Created: Wed Sep 2 09:28:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice
index 127f848..4b96962 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_1.pxi.spice
-* Created: Fri Aug 28 10:02:30 2020
+* Created: Wed Sep 2 09:28:55 2020
*
x_PM_SKY130_FD_SC_LP__A41O_1%A_113_237# N_A_113_237#_M1010_d
+ N_A_113_237#_M1011_s N_A_113_237#_M1008_g N_A_113_237#_c_62_n
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_1.spice b/cells/a41o/sky130_fd_sc_lp__a41o_1.spice
index 0c60f0f..40371d2 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_1.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_1.spice
-* Created: Fri Aug 28 10:02:30 2020
+* Created: Wed Sep 2 09:28:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report
new file mode 100644
index 0000000..17a329b
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_2.sp ('sky130_fd_sc_lp__a41o_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_2.spice ('sky130_fd_sc_lp__a41o_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:28:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_2 sky130_fd_sc_lp__a41o_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice
index a98f4e5..b97adef 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_2.pex.spice
-* Created: Fri Aug 28 10:02:38 2020
+* Created: Wed Sep 2 09:29:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice
index bf2bb64..682cf42 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_2.pxi.spice
-* Created: Fri Aug 28 10:02:38 2020
+* Created: Wed Sep 2 09:29:01 2020
*
x_PM_SKY130_FD_SC_LP__A41O_2%A_90_53# N_A_90_53#_M1002_s N_A_90_53#_M1003_d
+ N_A_90_53#_M1005_s N_A_90_53#_c_79_n N_A_90_53#_M1008_g N_A_90_53#_M1004_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_2.spice b/cells/a41o/sky130_fd_sc_lp__a41o_2.spice
index 29cd873..8033149 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_2.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_2.spice
-* Created: Fri Aug 28 10:02:38 2020
+* Created: Wed Sep 2 09:29:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report
new file mode 100644
index 0000000..932a300
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_4.sp ('sky130_fd_sc_lp__a41o_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_4.spice ('sky130_fd_sc_lp__a41o_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_4 sky130_fd_sc_lp__a41o_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice
index f3d1c6a..6d509b9 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_4.pex.spice
-* Created: Fri Aug 28 10:02:54 2020
+* Created: Wed Sep 2 09:29:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice
index cdb082d..c6a7bb8 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_4.pxi.spice
-* Created: Fri Aug 28 10:02:54 2020
+* Created: Wed Sep 2 09:29:08 2020
*
x_PM_SKY130_FD_SC_LP__A41O_4%A_100_23# N_A_100_23#_M1013_d N_A_100_23#_M1017_s
+ N_A_100_23#_M1007_d N_A_100_23#_M1002_g N_A_100_23#_M1000_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_4.spice b/cells/a41o/sky130_fd_sc_lp__a41o_4.spice
index 396442e..5279ea3 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_4.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_4.spice
-* Created: Fri Aug 28 10:02:54 2020
+* Created: Wed Sep 2 09:29:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report
new file mode 100644
index 0000000..7534753
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_lp.sp ('sky130_fd_sc_lp__a41o_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice ('sky130_fd_sc_lp__a41o_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_lp sky130_fd_sc_lp__a41o_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A4 A3 A2 A1 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice
index 3f43698..172082f 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_lp.pex.spice
-* Created: Fri Aug 28 10:03:02 2020
+* Created: Wed Sep 2 09:29:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice
index 6ab654c..e465b09 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_lp.pxi.spice
-* Created: Fri Aug 28 10:03:02 2020
+* Created: Wed Sep 2 09:29:15 2020
*
x_PM_SKY130_FD_SC_LP__A41O_LP%A4 N_A4_M1002_g N_A4_M1010_g N_A4_c_82_n
+ N_A4_c_83_n A4 N_A4_c_84_n N_A4_c_85_n PM_SKY130_FD_SC_LP__A41O_LP%A4
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice b/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice
index 52aeb3f..b0b56c7 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_lp.spice
-* Created: Fri Aug 28 10:03:02 2020
+* Created: Wed Sep 2 09:29:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report b/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report
new file mode 100644
index 0000000..5f2501d
--- /dev/null
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41o_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41o_m.sp ('sky130_fd_sc_lp__a41o_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41o/sky130_fd_sc_lp__a41o_m.spice ('sky130_fd_sc_lp__a41o_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41o_m sky130_fd_sc_lp__a41o_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41o_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a41o_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice
index d03ca9e..3b81360 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_m.pex.spice
-* Created: Fri Aug 28 10:03:09 2020
+* Created: Wed Sep 2 09:29:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice
index a937403..45fee84 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_m.pxi.spice
-* Created: Fri Aug 28 10:03:09 2020
+* Created: Wed Sep 2 09:29:21 2020
*
x_PM_SKY130_FD_SC_LP__A41O_M%A_80_153# N_A_80_153#_M1004_d N_A_80_153#_M1002_s
+ N_A_80_153#_c_93_n N_A_80_153#_M1009_g N_A_80_153#_c_87_n N_A_80_153#_M1010_g
diff --git a/cells/a41o/sky130_fd_sc_lp__a41o_m.spice b/cells/a41o/sky130_fd_sc_lp__a41o_m.spice
index 53e91e9..898d8d8 100644
--- a/cells/a41o/sky130_fd_sc_lp__a41o_m.spice
+++ b/cells/a41o/sky130_fd_sc_lp__a41o_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41o_m.spice
-* Created: Fri Aug 28 10:03:09 2020
+* Created: Wed Sep 2 09:29:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report
new file mode 100644
index 0000000..5c416e3
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_0.sp ('sky130_fd_sc_lp__a41oi_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice ('sky130_fd_sc_lp__a41oi_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_0 sky130_fd_sc_lp__a41oi_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_0
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice
index 5c24aa4..8ce4e3c 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_0.pex.spice
-* Created: Fri Aug 28 10:03:16 2020
+* Created: Wed Sep 2 09:29:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice
index 4156809..212f4f1 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_0.pxi.spice
-* Created: Fri Aug 28 10:03:16 2020
+* Created: Wed Sep 2 09:29:28 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_0%B1 N_B1_M1006_g N_B1_c_72_n N_B1_M1001_g
+ N_B1_c_77_n B1 B1 N_B1_c_74_n PM_SKY130_FD_SC_LP__A41OI_0%B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice
index bf35b9e..a84b18f 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_0.spice
-* Created: Fri Aug 28 10:03:16 2020
+* Created: Wed Sep 2 09:29:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report
new file mode 100644
index 0000000..d3baf16
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_1.sp ('sky130_fd_sc_lp__a41oi_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice ('sky130_fd_sc_lp__a41oi_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_1 sky130_fd_sc_lp__a41oi_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_1
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice
index cc35acf..537efdc 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_1.pex.spice
-* Created: Fri Aug 28 10:03:23 2020
+* Created: Wed Sep 2 09:29:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice
index 2b37251..fd81372 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_1.pxi.spice
-* Created: Fri Aug 28 10:03:23 2020
+* Created: Wed Sep 2 09:29:34 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_1%B1 N_B1_c_54_n N_B1_M1007_g N_B1_M1001_g
+ N_B1_c_56_n N_B1_c_57_n B1 PM_SKY130_FD_SC_LP__A41OI_1%B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice
index 635817c..0b14355 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_1.spice
-* Created: Fri Aug 28 10:03:23 2020
+* Created: Wed Sep 2 09:29:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report
new file mode 100644
index 0000000..cc95920
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_2.sp ('sky130_fd_sc_lp__a41oi_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice ('sky130_fd_sc_lp__a41oi_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_2 sky130_fd_sc_lp__a41oi_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_2
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice
index 087a3d6..8c3c208 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_2.pex.spice
-* Created: Fri Aug 28 10:03:30 2020
+* Created: Wed Sep 2 09:29:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice
index e603ba9..b4f3dbe 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_2.pxi.spice
-* Created: Fri Aug 28 10:03:30 2020
+* Created: Wed Sep 2 09:29:41 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_2%B1 N_B1_c_94_n N_B1_M1011_g N_B1_M1001_g
+ N_B1_c_96_n N_B1_M1012_g N_B1_M1007_g B1 B1 N_B1_c_99_n
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice
index d65f819..17cb724 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_2.spice
-* Created: Fri Aug 28 10:03:30 2020
+* Created: Wed Sep 2 09:29:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report
new file mode 100644
index 0000000..12b3dbb
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_4.sp ('sky130_fd_sc_lp__a41oi_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice ('sky130_fd_sc_lp__a41oi_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_4 sky130_fd_sc_lp__a41oi_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_4
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice
index dd597dc..3af9b5f 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_4.pex.spice
-* Created: Fri Aug 28 10:03:38 2020
+* Created: Wed Sep 2 09:29:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice
index ccf15ad..305cdc4 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_4.pxi.spice
-* Created: Fri Aug 28 10:03:38 2020
+* Created: Wed Sep 2 09:29:48 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_4%B1 N_B1_c_156_n N_B1_M1014_g N_B1_M1007_g
+ N_B1_c_158_n N_B1_M1021_g N_B1_M1013_g N_B1_c_160_n N_B1_M1022_g N_B1_M1023_g
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice
index 6e5b36d..ac478ba 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_4.spice
-* Created: Fri Aug 28 10:03:38 2020
+* Created: Wed Sep 2 09:29:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report
new file mode 100644
index 0000000..7cd11bf
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_lp.sp ('sky130_fd_sc_lp__a41oi_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice ('sky130_fd_sc_lp__a41oi_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_lp sky130_fd_sc_lp__a41oi_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A4 A3 A2 A1 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice
index 6b1f40b..86f1eec 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_lp.pex.spice
-* Created: Fri Aug 28 10:03:45 2020
+* Created: Wed Sep 2 09:29:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice
index cc6ac1b..1e32970 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_lp.pxi.spice
-* Created: Fri Aug 28 10:03:45 2020
+* Created: Wed Sep 2 09:29:55 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_LP%A4 N_A4_M1003_g N_A4_M1010_g A4 A4 N_A4_c_72_n
+ PM_SKY130_FD_SC_LP__A41OI_LP%A4
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice
index 5a11503..e616511 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_lp.spice
-* Created: Fri Aug 28 10:03:45 2020
+* Created: Wed Sep 2 09:29:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report
new file mode 100644
index 0000000..ff2f2fa
--- /dev/null
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__a41oi_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__a41oi_m.sp ('sky130_fd_sc_lp__a41oi_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice ('sky130_fd_sc_lp__a41oi_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:29:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__a41oi_m sky130_fd_sc_lp__a41oi_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__a41oi_m
+SOURCE CELL NAME: sky130_fd_sc_lp__a41oi_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 SMN4 (6 pins)
+ 1 1 SPMP_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 SMN4
+ 1 1 0 0 SPMP_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 A3 A4 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice
index b443735..974d4bd 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_m.pex.spice
-* Created: Fri Aug 28 10:04:01 2020
+* Created: Wed Sep 2 09:30:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice
index 103bdf0..fc389b8 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_m.pxi.spice
-* Created: Fri Aug 28 10:04:01 2020
+* Created: Wed Sep 2 09:30:01 2020
*
x_PM_SKY130_FD_SC_LP__A41OI_M%B1 N_B1_c_80_n N_B1_c_81_n N_B1_M1007_g
+ N_B1_M1008_g N_B1_c_83_n N_B1_c_84_n N_B1_c_89_n N_B1_c_90_n N_B1_c_91_n B1 B1
diff --git a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice
index 8b81e11..062fdcc 100644
--- a/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice
+++ b/cells/a41oi/sky130_fd_sc_lp__a41oi_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__a41oi_m.spice
-* Created: Fri Aug 28 10:04:01 2020
+* Created: Wed Sep 2 09:30:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report
new file mode 100644
index 0000000..a6ba7fc
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_0.sp ('sky130_fd_sc_lp__and2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_0.spice ('sky130_fd_sc_lp__and2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_0 sky130_fd_sc_lp__and2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice
index bbbc53c..e109219 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_0.pex.spice
-* Created: Fri Aug 28 10:04:09 2020
+* Created: Wed Sep 2 09:30:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice
index e8df69c..4d1ba2e 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_0.pxi.spice
-* Created: Fri Aug 28 10:04:09 2020
+* Created: Wed Sep 2 09:30:08 2020
*
x_PM_SKY130_FD_SC_LP__AND2_0%A N_A_c_47_n N_A_M1003_g N_A_M1000_g N_A_c_53_n A A
+ A N_A_c_50_n PM_SKY130_FD_SC_LP__AND2_0%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_0.spice b/cells/and2/sky130_fd_sc_lp__and2_0.spice
index 0168806..3bfac15 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_0.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_0.spice
-* Created: Fri Aug 28 10:04:09 2020
+* Created: Wed Sep 2 09:30:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report
new file mode 100644
index 0000000..dc08c04
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_1.sp ('sky130_fd_sc_lp__and2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_1.spice ('sky130_fd_sc_lp__and2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_1 sky130_fd_sc_lp__and2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_1.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_1.pex.spice
index e9b5ac0..30dd45d 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_1.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_1.pex.spice
-* Created: Fri Aug 28 10:04:15 2020
+* Created: Wed Sep 2 09:30:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_1.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_1.pxi.spice
index e8a384b..a28f3a8 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_1.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_1.pxi.spice
-* Created: Fri Aug 28 10:04:15 2020
+* Created: Wed Sep 2 09:30:14 2020
*
x_PM_SKY130_FD_SC_LP__AND2_1%A N_A_M1005_g N_A_M1000_g N_A_c_42_n N_A_c_43_n A A
+ PM_SKY130_FD_SC_LP__AND2_1%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_1.spice b/cells/and2/sky130_fd_sc_lp__and2_1.spice
index c03e18f..be66845 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_1.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_1.spice
-* Created: Fri Aug 28 10:04:15 2020
+* Created: Wed Sep 2 09:30:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_2.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_2.lvs.report
new file mode 100644
index 0000000..44b51a3
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_2.sp ('sky130_fd_sc_lp__and2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_2.spice ('sky130_fd_sc_lp__and2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_2 sky130_fd_sc_lp__and2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_2.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_2.pex.spice
index b2a15cb..d41507c 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_2.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_2.pex.spice
-* Created: Fri Aug 28 10:04:22 2020
+* Created: Wed Sep 2 09:30:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_2.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_2.pxi.spice
index 8acc49b..175815c 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_2.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_2.pxi.spice
-* Created: Fri Aug 28 10:04:22 2020
+* Created: Wed Sep 2 09:30:21 2020
*
x_PM_SKY130_FD_SC_LP__AND2_2%A N_A_c_55_n N_A_M1006_g N_A_c_51_n N_A_M1003_g
+ N_A_c_52_n A A N_A_c_53_n N_A_c_54_n PM_SKY130_FD_SC_LP__AND2_2%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_2.spice b/cells/and2/sky130_fd_sc_lp__and2_2.spice
index 6856f48..5eba05d 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_2.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_2.spice
-* Created: Fri Aug 28 10:04:22 2020
+* Created: Wed Sep 2 09:30:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_4.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_4.lvs.report
new file mode 100644
index 0000000..03a26b9
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_4.sp ('sky130_fd_sc_lp__and2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_4.spice ('sky130_fd_sc_lp__and2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_4 sky130_fd_sc_lp__and2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_4.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_4.pex.spice
index 007fb8d..aff8a41 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_4.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_4.pex.spice
-* Created: Fri Aug 28 10:04:30 2020
+* Created: Wed Sep 2 09:30:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_4.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_4.pxi.spice
index 83dd808..0278f4d 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_4.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_4.pxi.spice
-* Created: Fri Aug 28 10:04:30 2020
+* Created: Wed Sep 2 09:30:27 2020
*
x_PM_SKY130_FD_SC_LP__AND2_4%A N_A_c_64_n N_A_M1004_g N_A_c_65_n N_A_M1011_g A
+ N_A_c_67_n PM_SKY130_FD_SC_LP__AND2_4%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_4.spice b/cells/and2/sky130_fd_sc_lp__and2_4.spice
index 0c72def..180ad12 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_4.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_4.spice
-* Created: Fri Aug 28 10:04:30 2020
+* Created: Wed Sep 2 09:30:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_lp.lvs.report
new file mode 100644
index 0000000..5915622
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_lp.sp ('sky130_fd_sc_lp__and2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_lp.spice ('sky130_fd_sc_lp__and2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_lp sky130_fd_sc_lp__and2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_lp.pex.spice
index 85d3c17..95ec673 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp.pex.spice
-* Created: Fri Aug 28 10:04:44 2020
+* Created: Wed Sep 2 09:30:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_lp.pxi.spice
index 667a033..834a2b7 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp.pxi.spice
-* Created: Fri Aug 28 10:04:44 2020
+* Created: Wed Sep 2 09:30:40 2020
*
x_PM_SKY130_FD_SC_LP__AND2_LP%B N_B_M1008_g N_B_M1002_g N_B_M1005_g N_B_c_53_n
+ N_B_c_59_n B B B N_B_c_55_n PM_SKY130_FD_SC_LP__AND2_LP%B
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp.spice b/cells/and2/sky130_fd_sc_lp__and2_lp.spice
index db41cab..6676626 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp.spice
-* Created: Fri Aug 28 10:04:44 2020
+* Created: Wed Sep 2 09:30:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp2.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_lp2.lvs.report
new file mode 100644
index 0000000..9cb77d1
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp2.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_lp2.sp ('sky130_fd_sc_lp__and2_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_lp2.spice ('sky130_fd_sc_lp__and2_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_lp2 sky130_fd_sc_lp__and2_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp2.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_lp2.pex.spice
index 3841f46..53b1582 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp2.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp2.pex.spice
-* Created: Fri Aug 28 10:04:37 2020
+* Created: Wed Sep 2 09:30:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp2.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_lp2.pxi.spice
index 3d1542b..8379345 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp2.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp2.pxi.spice
-* Created: Fri Aug 28 10:04:37 2020
+* Created: Wed Sep 2 09:30:34 2020
*
x_PM_SKY130_FD_SC_LP__AND2_LP2%A_99_21# N_A_99_21#_M1002_d N_A_99_21#_M1004_d
+ N_A_99_21#_c_43_n N_A_99_21#_M1001_g N_A_99_21#_M1000_g N_A_99_21#_M1006_g
diff --git a/cells/and2/sky130_fd_sc_lp__and2_lp2.spice b/cells/and2/sky130_fd_sc_lp__and2_lp2.spice
index df9284b..464138f 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_lp2.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_lp2.spice
-* Created: Fri Aug 28 10:04:37 2020
+* Created: Wed Sep 2 09:30:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2/sky130_fd_sc_lp__and2_m.lvs.report b/cells/and2/sky130_fd_sc_lp__and2_m.lvs.report
new file mode 100644
index 0000000..8820307
--- /dev/null
+++ b/cells/and2/sky130_fd_sc_lp__and2_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2_m.sp ('sky130_fd_sc_lp__and2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2/sky130_fd_sc_lp__and2_m.spice ('sky130_fd_sc_lp__and2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2_m sky130_fd_sc_lp__and2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2/sky130_fd_sc_lp__and2_m.pex.spice b/cells/and2/sky130_fd_sc_lp__and2_m.pex.spice
index cd3294b..bbcd59e 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_m.pex.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_m.pex.spice
-* Created: Fri Aug 28 10:04:51 2020
+* Created: Wed Sep 2 09:30:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2/sky130_fd_sc_lp__and2_m.pxi.spice b/cells/and2/sky130_fd_sc_lp__and2_m.pxi.spice
index 9e27674..667084d 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_m.pxi.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_m.pxi.spice
-* Created: Fri Aug 28 10:04:51 2020
+* Created: Wed Sep 2 09:30:47 2020
*
x_PM_SKY130_FD_SC_LP__AND2_M%A N_A_M1004_g N_A_c_37_n N_A_M1003_g A A
+ PM_SKY130_FD_SC_LP__AND2_M%A
diff --git a/cells/and2/sky130_fd_sc_lp__and2_m.spice b/cells/and2/sky130_fd_sc_lp__and2_m.spice
index 4bcfbee..596d5ab 100644
--- a/cells/and2/sky130_fd_sc_lp__and2_m.spice
+++ b/cells/and2/sky130_fd_sc_lp__and2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2_m.spice
-* Created: Fri Aug 28 10:04:51 2020
+* Created: Wed Sep 2 09:30:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_1.lvs.report b/cells/and2b/sky130_fd_sc_lp__and2b_1.lvs.report
new file mode 100644
index 0000000..65c7b84
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2b_1.sp ('sky130_fd_sc_lp__and2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2b/sky130_fd_sc_lp__and2b_1.spice ('sky130_fd_sc_lp__and2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2b_1 sky130_fd_sc_lp__and2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_1.pex.spice b/cells/and2b/sky130_fd_sc_lp__and2b_1.pex.spice
index 981dbbb..5fcb683 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_1.pex.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_1.pex.spice
-* Created: Fri Aug 28 10:05:07 2020
+* Created: Wed Sep 2 09:30:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_1.pxi.spice b/cells/and2b/sky130_fd_sc_lp__and2b_1.pxi.spice
index 02f487e..5df32a4 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_1.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_1.pxi.spice
-* Created: Fri Aug 28 10:05:07 2020
+* Created: Wed Sep 2 09:30:54 2020
*
x_PM_SKY130_FD_SC_LP__AND2B_1%A_N N_A_N_c_51_n N_A_N_M1003_g N_A_N_M1007_g A_N
+ N_A_N_c_54_n PM_SKY130_FD_SC_LP__AND2B_1%A_N
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_1.spice b/cells/and2b/sky130_fd_sc_lp__and2b_1.spice
index 7394a42..7ac790e 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_1.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_1.spice
-* Created: Fri Aug 28 10:05:07 2020
+* Created: Wed Sep 2 09:30:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_2.lvs.report b/cells/and2b/sky130_fd_sc_lp__and2b_2.lvs.report
new file mode 100644
index 0000000..f96bbb0
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2b_2.sp ('sky130_fd_sc_lp__and2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2b/sky130_fd_sc_lp__and2b_2.spice ('sky130_fd_sc_lp__and2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:30:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2b_2 sky130_fd_sc_lp__and2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_2.pex.spice b/cells/and2b/sky130_fd_sc_lp__and2b_2.pex.spice
index add48d1..aaba830 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_2.pex.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_2.pex.spice
-* Created: Fri Aug 28 10:05:15 2020
+* Created: Wed Sep 2 09:31:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_2.pxi.spice b/cells/and2b/sky130_fd_sc_lp__and2b_2.pxi.spice
index 0ef4aa4..d59e8d9 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_2.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_2.pxi.spice
-* Created: Fri Aug 28 10:05:15 2020
+* Created: Wed Sep 2 09:31:01 2020
*
x_PM_SKY130_FD_SC_LP__AND2B_2%A_N N_A_N_M1006_g N_A_N_M1004_g A_N A_N
+ N_A_N_c_61_n N_A_N_c_62_n PM_SKY130_FD_SC_LP__AND2B_2%A_N
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_2.spice b/cells/and2b/sky130_fd_sc_lp__and2b_2.spice
index 7f707e8..39b8650 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_2.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_2.spice
-* Created: Fri Aug 28 10:05:15 2020
+* Created: Wed Sep 2 09:31:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_4.lvs.report b/cells/and2b/sky130_fd_sc_lp__and2b_4.lvs.report
new file mode 100644
index 0000000..6b9fadf
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2b_4.sp ('sky130_fd_sc_lp__and2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2b/sky130_fd_sc_lp__and2b_4.spice ('sky130_fd_sc_lp__and2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2b_4 sky130_fd_sc_lp__and2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_4.pex.spice b/cells/and2b/sky130_fd_sc_lp__and2b_4.pex.spice
index 4c33306..671f879 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_4.pex.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_4.pex.spice
-* Created: Fri Aug 28 10:05:22 2020
+* Created: Wed Sep 2 09:31:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_4.pxi.spice b/cells/and2b/sky130_fd_sc_lp__and2b_4.pxi.spice
index 1498796..403e316 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_4.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_4.pxi.spice
-* Created: Fri Aug 28 10:05:22 2020
+* Created: Wed Sep 2 09:31:07 2020
*
x_PM_SKY130_FD_SC_LP__AND2B_4%A_N N_A_N_M1004_g N_A_N_M1006_g A_N A_N A_N
+ N_A_N_c_73_n N_A_N_c_74_n PM_SKY130_FD_SC_LP__AND2B_4%A_N
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_4.spice b/cells/and2b/sky130_fd_sc_lp__and2b_4.spice
index 5d29b5e..e4ae2f2 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_4.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_4.spice
-* Created: Fri Aug 28 10:05:22 2020
+* Created: Wed Sep 2 09:31:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_lp.lvs.report b/cells/and2b/sky130_fd_sc_lp__and2b_lp.lvs.report
new file mode 100644
index 0000000..54f835b
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2b_lp.sp ('sky130_fd_sc_lp__and2b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2b/sky130_fd_sc_lp__and2b_lp.spice ('sky130_fd_sc_lp__and2b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2b_lp sky130_fd_sc_lp__and2b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and2b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A_N X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_lp.pex.spice b/cells/and2b/sky130_fd_sc_lp__and2b_lp.pex.spice
index f4496ac..aeea51a 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_lp.pex.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_lp.pex.spice
-* Created: Fri Aug 28 10:05:29 2020
+* Created: Wed Sep 2 09:31:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_lp.pxi.spice b/cells/and2b/sky130_fd_sc_lp__and2b_lp.pxi.spice
index 3c718c8..b6c6db5 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_lp.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_lp.pxi.spice
-* Created: Fri Aug 28 10:05:29 2020
+* Created: Wed Sep 2 09:31:14 2020
*
x_PM_SKY130_FD_SC_LP__AND2B_LP%A_108_127# N_A_108_127#_M1004_d
+ N_A_108_127#_M1000_d N_A_108_127#_c_53_n N_A_108_127#_M1006_g
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_lp.spice b/cells/and2b/sky130_fd_sc_lp__and2b_lp.spice
index bb4dc7f..9b33016 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_lp.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_lp.spice
-* Created: Fri Aug 28 10:05:29 2020
+* Created: Wed Sep 2 09:31:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_m.lvs.report b/cells/and2b/sky130_fd_sc_lp__and2b_m.lvs.report
new file mode 100644
index 0000000..48dfe48
--- /dev/null
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and2b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and2b_m.sp ('sky130_fd_sc_lp__and2b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and2b/sky130_fd_sc_lp__and2b_m.spice ('sky130_fd_sc_lp__and2b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and2b_m sky130_fd_sc_lp__and2b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and2b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and2b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_m.pex.spice b/cells/and2b/sky130_fd_sc_lp__and2b_m.pex.spice
index 53a3b15..e115e06 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_m.pex.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_m.pex.spice
-* Created: Fri Aug 28 10:05:36 2020
+* Created: Wed Sep 2 09:31:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_m.pxi.spice b/cells/and2b/sky130_fd_sc_lp__and2b_m.pxi.spice
index d9431cb..556b65f 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_m.pxi.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_m.pxi.spice
-* Created: Fri Aug 28 10:05:36 2020
+* Created: Wed Sep 2 09:31:20 2020
*
x_PM_SKY130_FD_SC_LP__AND2B_M%A_N N_A_N_c_55_n N_A_N_M1007_g N_A_N_c_56_n
+ N_A_N_M1000_g A_N A_N PM_SKY130_FD_SC_LP__AND2B_M%A_N
diff --git a/cells/and2b/sky130_fd_sc_lp__and2b_m.spice b/cells/and2b/sky130_fd_sc_lp__and2b_m.spice
index 6488703..1691d3e 100644
--- a/cells/and2b/sky130_fd_sc_lp__and2b_m.spice
+++ b/cells/and2b/sky130_fd_sc_lp__and2b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and2b_m.spice
-* Created: Fri Aug 28 10:05:36 2020
+* Created: Wed Sep 2 09:31:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_0.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_0.lvs.report
new file mode 100644
index 0000000..7f5b28e
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_0.sp ('sky130_fd_sc_lp__and3_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_0.spice ('sky130_fd_sc_lp__and3_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_0 sky130_fd_sc_lp__and3_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_0
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_0.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_0.pex.spice
index f7e2547..fc5e4d8 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_0.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_0.pex.spice
-* Created: Fri Aug 28 10:05:43 2020
+* Created: Wed Sep 2 09:31:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_0.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_0.pxi.spice
index 2848820..23b823e 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_0.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_0.pxi.spice
-* Created: Fri Aug 28 10:05:43 2020
+* Created: Wed Sep 2 09:31:27 2020
*
x_PM_SKY130_FD_SC_LP__AND3_0%A N_A_c_66_n N_A_M1005_g N_A_M1007_g N_A_c_67_n
+ N_A_c_68_n N_A_c_73_n A A A N_A_c_70_n N_A_c_71_n PM_SKY130_FD_SC_LP__AND3_0%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_0.spice b/cells/and3/sky130_fd_sc_lp__and3_0.spice
index fdba831..0e0c2d2 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_0.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_0.spice
-* Created: Fri Aug 28 10:05:43 2020
+* Created: Wed Sep 2 09:31:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_1.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_1.lvs.report
new file mode 100644
index 0000000..5f8b79b
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_1.sp ('sky130_fd_sc_lp__and3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_1.spice ('sky130_fd_sc_lp__and3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_1 sky130_fd_sc_lp__and3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_1.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_1.pex.spice
index 02f3c7e..0a65730 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_1.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_1.pex.spice
-* Created: Fri Aug 28 10:05:51 2020
+* Created: Wed Sep 2 09:31:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_1.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_1.pxi.spice
index 8db0433..843b2c2 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_1.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_1.pxi.spice
-* Created: Fri Aug 28 10:05:51 2020
+* Created: Wed Sep 2 09:31:33 2020
*
x_PM_SKY130_FD_SC_LP__AND3_1%A N_A_M1005_g N_A_M1002_g A N_A_c_56_n
+ PM_SKY130_FD_SC_LP__AND3_1%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_1.spice b/cells/and3/sky130_fd_sc_lp__and3_1.spice
index 2e8fb43..ce759ac 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_1.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_1.spice
-* Created: Fri Aug 28 10:05:51 2020
+* Created: Wed Sep 2 09:31:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_2.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_2.lvs.report
new file mode 100644
index 0000000..25b020b
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_2.sp ('sky130_fd_sc_lp__and3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_2.spice ('sky130_fd_sc_lp__and3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_2 sky130_fd_sc_lp__and3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_2.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_2.pex.spice
index 2dbb040..ad61667 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_2.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_2.pex.spice
-* Created: Fri Aug 28 10:05:58 2020
+* Created: Wed Sep 2 09:31:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_2.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_2.pxi.spice
index c7e880d..2c7e6a6 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_2.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_2.pxi.spice
-* Created: Fri Aug 28 10:05:58 2020
+* Created: Wed Sep 2 09:31:40 2020
*
x_PM_SKY130_FD_SC_LP__AND3_2%A N_A_c_66_n N_A_M1000_g N_A_c_61_n N_A_M1008_g
+ N_A_c_62_n N_A_c_63_n A N_A_c_64_n N_A_c_65_n PM_SKY130_FD_SC_LP__AND3_2%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_2.spice b/cells/and3/sky130_fd_sc_lp__and3_2.spice
index cce885b..02d4eef 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_2.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_2.spice
-* Created: Fri Aug 28 10:05:58 2020
+* Created: Wed Sep 2 09:31:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_4.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_4.lvs.report
new file mode 100644
index 0000000..d53820d
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_4.sp ('sky130_fd_sc_lp__and3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_4.spice ('sky130_fd_sc_lp__and3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_4 sky130_fd_sc_lp__and3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_4.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_4.pex.spice
index dabe5f1..3b940cc 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_4.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_4.pex.spice
-* Created: Fri Aug 28 10:06:14 2020
+* Created: Wed Sep 2 09:31:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_4.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_4.pxi.spice
index f4c80e3..2a4a9d6 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_4.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_4.pxi.spice
-* Created: Fri Aug 28 10:06:14 2020
+* Created: Wed Sep 2 09:31:46 2020
*
x_PM_SKY130_FD_SC_LP__AND3_4%A N_A_M1003_g N_A_M1000_g A A N_A_c_76_n N_A_c_77_n
+ PM_SKY130_FD_SC_LP__AND3_4%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_4.spice b/cells/and3/sky130_fd_sc_lp__and3_4.spice
index 627ed5b..71595fc 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_4.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_4.spice
-* Created: Fri Aug 28 10:06:14 2020
+* Created: Wed Sep 2 09:31:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_lp.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_lp.lvs.report
new file mode 100644
index 0000000..ee0dccb
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_lp.sp ('sky130_fd_sc_lp__and3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_lp.spice ('sky130_fd_sc_lp__and3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_lp sky130_fd_sc_lp__and3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_lp.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_lp.pex.spice
index 154df8c..59f8b96 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_lp.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_lp.pex.spice
-* Created: Fri Aug 28 10:06:22 2020
+* Created: Wed Sep 2 09:31:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_lp.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_lp.pxi.spice
index 5248aa0..753f5cd 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_lp.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_lp.pxi.spice
-* Created: Fri Aug 28 10:06:22 2020
+* Created: Wed Sep 2 09:31:52 2020
*
x_PM_SKY130_FD_SC_LP__AND3_LP%A N_A_c_63_n N_A_c_64_n N_A_c_65_n N_A_M1003_g
+ N_A_M1006_g A A N_A_c_68_n N_A_c_69_n PM_SKY130_FD_SC_LP__AND3_LP%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_lp.spice b/cells/and3/sky130_fd_sc_lp__and3_lp.spice
index a137545..de3ed7d 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_lp.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_lp.spice
-* Created: Fri Aug 28 10:06:22 2020
+* Created: Wed Sep 2 09:31:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3/sky130_fd_sc_lp__and3_m.lvs.report b/cells/and3/sky130_fd_sc_lp__and3_m.lvs.report
new file mode 100644
index 0000000..4752751
--- /dev/null
+++ b/cells/and3/sky130_fd_sc_lp__and3_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3_m.sp ('sky130_fd_sc_lp__and3_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3/sky130_fd_sc_lp__and3_m.spice ('sky130_fd_sc_lp__and3_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:31:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3_m sky130_fd_sc_lp__and3_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and3_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3/sky130_fd_sc_lp__and3_m.pex.spice b/cells/and3/sky130_fd_sc_lp__and3_m.pex.spice
index 3c2dab1..afb5530 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_m.pex.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_m.pex.spice
-* Created: Fri Aug 28 10:06:30 2020
+* Created: Wed Sep 2 09:31:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3/sky130_fd_sc_lp__and3_m.pxi.spice b/cells/and3/sky130_fd_sc_lp__and3_m.pxi.spice
index a0adf7d..928fa0d 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_m.pxi.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_m.pxi.spice
-* Created: Fri Aug 28 10:06:30 2020
+* Created: Wed Sep 2 09:31:59 2020
*
x_PM_SKY130_FD_SC_LP__AND3_M%A N_A_M1004_g N_A_M1006_g A A N_A_c_57_n
+ PM_SKY130_FD_SC_LP__AND3_M%A
diff --git a/cells/and3/sky130_fd_sc_lp__and3_m.spice b/cells/and3/sky130_fd_sc_lp__and3_m.spice
index 5c48082..3279146 100644
--- a/cells/and3/sky130_fd_sc_lp__and3_m.spice
+++ b/cells/and3/sky130_fd_sc_lp__and3_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3_m.spice
-* Created: Fri Aug 28 10:06:30 2020
+* Created: Wed Sep 2 09:31:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_1.lvs.report b/cells/and3b/sky130_fd_sc_lp__and3b_1.lvs.report
new file mode 100644
index 0000000..e6db995
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3b_1.sp ('sky130_fd_sc_lp__and3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3b/sky130_fd_sc_lp__and3b_1.spice ('sky130_fd_sc_lp__and3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3b_1 sky130_fd_sc_lp__and3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_1.pex.spice b/cells/and3b/sky130_fd_sc_lp__and3b_1.pex.spice
index a6a3b7f..be9e013 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_1.pex.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_1.pex.spice
-* Created: Fri Aug 28 10:06:37 2020
+* Created: Wed Sep 2 09:32:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_1.pxi.spice b/cells/and3b/sky130_fd_sc_lp__and3b_1.pxi.spice
index e729bf9..ba3c59a 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_1.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_1.pxi.spice
-* Created: Fri Aug 28 10:06:37 2020
+* Created: Wed Sep 2 09:32:06 2020
*
x_PM_SKY130_FD_SC_LP__AND3B_1%A_N N_A_N_c_69_n N_A_N_M1003_g N_A_N_M1006_g
+ N_A_N_c_72_n A_N A_N A_N A_N N_A_N_c_74_n PM_SKY130_FD_SC_LP__AND3B_1%A_N
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_1.spice b/cells/and3b/sky130_fd_sc_lp__and3b_1.spice
index 3573bd6..79a82af 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_1.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_1.spice
-* Created: Fri Aug 28 10:06:37 2020
+* Created: Wed Sep 2 09:32:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_2.lvs.report b/cells/and3b/sky130_fd_sc_lp__and3b_2.lvs.report
new file mode 100644
index 0000000..8eec31b
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3b_2.sp ('sky130_fd_sc_lp__and3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3b/sky130_fd_sc_lp__and3b_2.spice ('sky130_fd_sc_lp__and3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3b_2 sky130_fd_sc_lp__and3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_2.pex.spice b/cells/and3b/sky130_fd_sc_lp__and3b_2.pex.spice
index d9d7eea..423a79c 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_2.pex.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_2.pex.spice
-* Created: Fri Aug 28 10:06:44 2020
+* Created: Wed Sep 2 09:32:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_2.pxi.spice b/cells/and3b/sky130_fd_sc_lp__and3b_2.pxi.spice
index 8efbb2d..adc31ae 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_2.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_2.pxi.spice
-* Created: Fri Aug 28 10:06:44 2020
+* Created: Wed Sep 2 09:32:13 2020
*
x_PM_SKY130_FD_SC_LP__AND3B_2%A_N N_A_N_M1005_g N_A_N_M1008_g A_N A_N
+ N_A_N_c_67_n N_A_N_c_68_n PM_SKY130_FD_SC_LP__AND3B_2%A_N
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_2.spice b/cells/and3b/sky130_fd_sc_lp__and3b_2.spice
index b3e5f80..1902a22 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_2.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_2.spice
-* Created: Fri Aug 28 10:06:44 2020
+* Created: Wed Sep 2 09:32:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_4.lvs.report b/cells/and3b/sky130_fd_sc_lp__and3b_4.lvs.report
new file mode 100644
index 0000000..9ba485d
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3b_4.sp ('sky130_fd_sc_lp__and3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3b/sky130_fd_sc_lp__and3b_4.spice ('sky130_fd_sc_lp__and3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3b_4 sky130_fd_sc_lp__and3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_4.pex.spice b/cells/and3b/sky130_fd_sc_lp__and3b_4.pex.spice
index aefce0a..118c165 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_4.pex.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_4.pex.spice
-* Created: Fri Aug 28 10:06:52 2020
+* Created: Wed Sep 2 09:32:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_4.pxi.spice b/cells/and3b/sky130_fd_sc_lp__and3b_4.pxi.spice
index 3218c32..d94f803 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_4.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_4.pxi.spice
-* Created: Fri Aug 28 10:06:52 2020
+* Created: Wed Sep 2 09:32:19 2020
*
x_PM_SKY130_FD_SC_LP__AND3B_4%A_N N_A_N_M1015_g N_A_N_M1009_g A_N A_N A_N A_N
+ A_N N_A_N_c_86_n N_A_N_c_87_n PM_SKY130_FD_SC_LP__AND3B_4%A_N
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_4.spice b/cells/and3b/sky130_fd_sc_lp__and3b_4.spice
index 051869a..3eed96e 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_4.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_4.spice
-* Created: Fri Aug 28 10:06:52 2020
+* Created: Wed Sep 2 09:32:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_lp.lvs.report b/cells/and3b/sky130_fd_sc_lp__and3b_lp.lvs.report
new file mode 100644
index 0000000..1a8732b
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3b_lp.sp ('sky130_fd_sc_lp__and3b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3b/sky130_fd_sc_lp__and3b_lp.spice ('sky130_fd_sc_lp__and3b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3b_lp sky130_fd_sc_lp__and3b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and3b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_lp.pex.spice b/cells/and3b/sky130_fd_sc_lp__and3b_lp.pex.spice
index cfba858..5281cfc 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_lp.pex.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_lp.pex.spice
-* Created: Fri Aug 28 10:06:59 2020
+* Created: Wed Sep 2 09:32:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_lp.pxi.spice b/cells/and3b/sky130_fd_sc_lp__and3b_lp.pxi.spice
index 64c065d..25c109a 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_lp.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_lp.pxi.spice
-* Created: Fri Aug 28 10:06:59 2020
+* Created: Wed Sep 2 09:32:25 2020
*
x_PM_SKY130_FD_SC_LP__AND3B_LP%A_N N_A_N_c_81_n N_A_N_M1005_g N_A_N_M1009_g
+ N_A_N_c_83_n N_A_N_c_84_n N_A_N_M1011_g N_A_N_c_85_n N_A_N_c_86_n A_N A_N
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_lp.spice b/cells/and3b/sky130_fd_sc_lp__and3b_lp.spice
index 8f6fa97..aae9b03 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_lp.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_lp.spice
-* Created: Fri Aug 28 10:06:59 2020
+* Created: Wed Sep 2 09:32:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_m.lvs.report b/cells/and3b/sky130_fd_sc_lp__and3b_m.lvs.report
new file mode 100644
index 0000000..0e3ed8c
--- /dev/null
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and3b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and3b_m.sp ('sky130_fd_sc_lp__and3b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and3b/sky130_fd_sc_lp__and3b_m.spice ('sky130_fd_sc_lp__and3b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and3b_m sky130_fd_sc_lp__and3b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and3b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and3b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_m.pex.spice b/cells/and3b/sky130_fd_sc_lp__and3b_m.pex.spice
index f21dc63..2540814 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_m.pex.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_m.pex.spice
-* Created: Fri Aug 28 10:07:15 2020
+* Created: Wed Sep 2 09:32:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_m.pxi.spice b/cells/and3b/sky130_fd_sc_lp__and3b_m.pxi.spice
index 03962a6..679d1fa 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_m.pxi.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_m.pxi.spice
-* Created: Fri Aug 28 10:07:15 2020
+* Created: Wed Sep 2 09:32:32 2020
*
x_PM_SKY130_FD_SC_LP__AND3B_M%A_N N_A_N_c_69_n N_A_N_M1006_g N_A_N_M1008_g
+ N_A_N_c_72_n A_N A_N A_N A_N A_N N_A_N_c_74_n PM_SKY130_FD_SC_LP__AND3B_M%A_N
diff --git a/cells/and3b/sky130_fd_sc_lp__and3b_m.spice b/cells/and3b/sky130_fd_sc_lp__and3b_m.spice
index d27191c..640eb5b 100644
--- a/cells/and3b/sky130_fd_sc_lp__and3b_m.spice
+++ b/cells/and3b/sky130_fd_sc_lp__and3b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and3b_m.spice
-* Created: Fri Aug 28 10:07:15 2020
+* Created: Wed Sep 2 09:32:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_0.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_0.lvs.report
new file mode 100644
index 0000000..f8842f4
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_0.sp ('sky130_fd_sc_lp__and4_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_0.spice ('sky130_fd_sc_lp__and4_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_0 sky130_fd_sc_lp__and4_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_0
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_0.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_0.pex.spice
index 2ac7568..1802f23 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_0.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_0.pex.spice
-* Created: Fri Aug 28 10:07:23 2020
+* Created: Wed Sep 2 09:32:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_0.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_0.pxi.spice
index cc3e78c..5c3fe44 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_0.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_0.pxi.spice
-* Created: Fri Aug 28 10:07:23 2020
+* Created: Wed Sep 2 09:32:39 2020
*
x_PM_SKY130_FD_SC_LP__AND4_0%A N_A_M1009_g N_A_M1002_g N_A_c_71_n N_A_c_72_n
+ N_A_c_73_n A A A A N_A_c_75_n PM_SKY130_FD_SC_LP__AND4_0%A
diff --git a/cells/and4/sky130_fd_sc_lp__and4_0.spice b/cells/and4/sky130_fd_sc_lp__and4_0.spice
index 105ab2b..708fecd 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_0.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_0.spice
-* Created: Fri Aug 28 10:07:23 2020
+* Created: Wed Sep 2 09:32:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_1.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_1.lvs.report
new file mode 100644
index 0000000..8c0b986
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_1.sp ('sky130_fd_sc_lp__and4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_1.spice ('sky130_fd_sc_lp__and4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_1 sky130_fd_sc_lp__and4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_1.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_1.pex.spice
index 8cacdca..4b7a868 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_1.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_1.pex.spice
-* Created: Fri Aug 28 10:07:30 2020
+* Created: Wed Sep 2 09:32:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_1.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_1.pxi.spice
index db6b905..b38221d 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_1.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_1.pxi.spice
-* Created: Fri Aug 28 10:07:30 2020
+* Created: Wed Sep 2 09:32:45 2020
*
x_PM_SKY130_FD_SC_LP__AND4_1%A N_A_c_61_n N_A_M1001_g N_A_M1008_g N_A_c_64_n A A
+ A N_A_c_66_n PM_SKY130_FD_SC_LP__AND4_1%A
diff --git a/cells/and4/sky130_fd_sc_lp__and4_1.spice b/cells/and4/sky130_fd_sc_lp__and4_1.spice
index d34c707..278d708 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_1.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_1.spice
-* Created: Fri Aug 28 10:07:30 2020
+* Created: Wed Sep 2 09:32:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_2.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_2.lvs.report
new file mode 100644
index 0000000..0d8ab16
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_2.sp ('sky130_fd_sc_lp__and4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_2.spice ('sky130_fd_sc_lp__and4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_2 sky130_fd_sc_lp__and4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_2.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_2.pex.spice
index 3c4b82f..d6f60ec 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_2.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_2.pex.spice
-* Created: Fri Aug 28 10:07:38 2020
+* Created: Wed Sep 2 09:32:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_2.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_2.pxi.spice
index 565eddf..d7981d7 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_2.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_2.pxi.spice
-* Created: Fri Aug 28 10:07:38 2020
+* Created: Wed Sep 2 09:32:52 2020
*
x_PM_SKY130_FD_SC_LP__AND4_2%A N_A_c_67_n N_A_M1010_g N_A_M1009_g N_A_c_69_n A A
+ N_A_c_70_n N_A_c_71_n PM_SKY130_FD_SC_LP__AND4_2%A
diff --git a/cells/and4/sky130_fd_sc_lp__and4_2.spice b/cells/and4/sky130_fd_sc_lp__and4_2.spice
index 945c2e5..5029820 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_2.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_2.spice
-* Created: Fri Aug 28 10:07:38 2020
+* Created: Wed Sep 2 09:32:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_4.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_4.lvs.report
new file mode 100644
index 0000000..9471555
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_4.sp ('sky130_fd_sc_lp__and4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_4.spice ('sky130_fd_sc_lp__and4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:32:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_4 sky130_fd_sc_lp__and4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_4.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_4.pex.spice
index 09019f5..0d907d7 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_4.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_4.pex.spice
-* Created: Fri Aug 28 10:07:45 2020
+* Created: Wed Sep 2 09:32:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_4.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_4.pxi.spice
index b81ff2a..a2ad66d 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_4.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_4.pxi.spice
-* Created: Fri Aug 28 10:07:45 2020
+* Created: Wed Sep 2 09:32:59 2020
*
x_PM_SKY130_FD_SC_LP__AND4_4%A N_A_c_80_n N_A_M1009_g N_A_c_81_n N_A_M1000_g A A
+ PM_SKY130_FD_SC_LP__AND4_4%A
diff --git a/cells/and4/sky130_fd_sc_lp__and4_4.spice b/cells/and4/sky130_fd_sc_lp__and4_4.spice
index d286d99..a1f3b69 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_4.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_4.spice
-* Created: Fri Aug 28 10:07:45 2020
+* Created: Wed Sep 2 09:32:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_lp.lvs.report
new file mode 100644
index 0000000..056627a
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_lp.sp ('sky130_fd_sc_lp__and4_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_lp.spice ('sky130_fd_sc_lp__and4_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_lp sky130_fd_sc_lp__and4_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 6 6 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMN4
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_lp.pex.spice
index 916f355..ac22ee7 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp.pex.spice
-* Created: Fri Aug 28 10:08:01 2020
+* Created: Wed Sep 2 09:33:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_lp.pxi.spice
index c80f13c..53a03f4 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp.pxi.spice
-* Created: Fri Aug 28 10:08:01 2020
+* Created: Wed Sep 2 09:33:12 2020
*
x_PM_SKY130_FD_SC_LP__AND4_LP%D N_D_M1005_g N_D_c_88_n N_D_c_89_n N_D_M1004_g
+ N_D_M1000_g N_D_c_95_n D D D N_D_c_92_n PM_SKY130_FD_SC_LP__AND4_LP%D
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp.spice b/cells/and4/sky130_fd_sc_lp__and4_lp.spice
index fcf7cbe..91a26bb 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp.spice
-* Created: Fri Aug 28 10:08:01 2020
+* Created: Wed Sep 2 09:33:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp2.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_lp2.lvs.report
new file mode 100644
index 0000000..c0a163c
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_lp2.sp ('sky130_fd_sc_lp__and4_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_lp2.spice ('sky130_fd_sc_lp__and4_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_lp2 sky130_fd_sc_lp__and4_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp2.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_lp2.pex.spice
index b6dff34..07f43c1 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp2.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp2.pex.spice
-* Created: Fri Aug 28 10:07:53 2020
+* Created: Wed Sep 2 09:33:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp2.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_lp2.pxi.spice
index 9402b72..1452c68 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp2.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp2.pxi.spice
-* Created: Fri Aug 28 10:07:53 2020
+* Created: Wed Sep 2 09:33:05 2020
*
x_PM_SKY130_FD_SC_LP__AND4_LP2%A_84_21# N_A_84_21#_M1000_d N_A_84_21#_M1009_d
+ N_A_84_21#_M1007_d N_A_84_21#_c_74_n N_A_84_21#_M1005_g N_A_84_21#_M1010_g
diff --git a/cells/and4/sky130_fd_sc_lp__and4_lp2.spice b/cells/and4/sky130_fd_sc_lp__and4_lp2.spice
index fed46a0..8cb0f58 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_lp2.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_lp2.spice
-* Created: Fri Aug 28 10:07:53 2020
+* Created: Wed Sep 2 09:33:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4/sky130_fd_sc_lp__and4_m.lvs.report b/cells/and4/sky130_fd_sc_lp__and4_m.lvs.report
new file mode 100644
index 0000000..5e16d63
--- /dev/null
+++ b/cells/and4/sky130_fd_sc_lp__and4_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4_m.sp ('sky130_fd_sc_lp__and4_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4/sky130_fd_sc_lp__and4_m.spice ('sky130_fd_sc_lp__and4_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4_m sky130_fd_sc_lp__and4_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and4_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4/sky130_fd_sc_lp__and4_m.pex.spice b/cells/and4/sky130_fd_sc_lp__and4_m.pex.spice
index 3672859..b35c1a5 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_m.pex.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_m.pex.spice
-* Created: Fri Aug 28 10:08:17 2020
+* Created: Wed Sep 2 09:33:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4/sky130_fd_sc_lp__and4_m.pxi.spice b/cells/and4/sky130_fd_sc_lp__and4_m.pxi.spice
index f6549f0..c086592 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_m.pxi.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_m.pxi.spice
-* Created: Fri Aug 28 10:08:17 2020
+* Created: Wed Sep 2 09:33:19 2020
*
x_PM_SKY130_FD_SC_LP__AND4_M%A N_A_c_70_n N_A_M1002_g N_A_M1001_g N_A_c_66_n
+ N_A_c_67_n A A A N_A_c_69_n PM_SKY130_FD_SC_LP__AND4_M%A
diff --git a/cells/and4/sky130_fd_sc_lp__and4_m.spice b/cells/and4/sky130_fd_sc_lp__and4_m.spice
index 016e9be..21f5ccc 100644
--- a/cells/and4/sky130_fd_sc_lp__and4_m.spice
+++ b/cells/and4/sky130_fd_sc_lp__and4_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4_m.spice
-* Created: Fri Aug 28 10:08:17 2020
+* Created: Wed Sep 2 09:33:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_1.lvs.report b/cells/and4b/sky130_fd_sc_lp__and4b_1.lvs.report
new file mode 100644
index 0000000..b169ecd
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4b_1.sp ('sky130_fd_sc_lp__and4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4b/sky130_fd_sc_lp__and4b_1.spice ('sky130_fd_sc_lp__and4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4b_1 sky130_fd_sc_lp__and4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_1.pex.spice b/cells/and4b/sky130_fd_sc_lp__and4b_1.pex.spice
index 9f356e5..ef89328 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_1.pex.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_1.pex.spice
-* Created: Fri Aug 28 10:08:25 2020
+* Created: Wed Sep 2 09:33:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_1.pxi.spice b/cells/and4b/sky130_fd_sc_lp__and4b_1.pxi.spice
index c5e5986..6a9df5e 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_1.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_1.pxi.spice
-* Created: Fri Aug 28 10:08:25 2020
+* Created: Wed Sep 2 09:33:27 2020
*
x_PM_SKY130_FD_SC_LP__AND4B_1%A_N N_A_N_M1005_g N_A_N_M1010_g N_A_N_c_87_n
+ N_A_N_c_88_n A_N N_A_N_c_89_n N_A_N_c_90_n PM_SKY130_FD_SC_LP__AND4B_1%A_N
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_1.spice b/cells/and4b/sky130_fd_sc_lp__and4b_1.spice
index 68039f5..4a296f3 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_1.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_1.spice
-* Created: Fri Aug 28 10:08:25 2020
+* Created: Wed Sep 2 09:33:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_2.lvs.report b/cells/and4b/sky130_fd_sc_lp__and4b_2.lvs.report
new file mode 100644
index 0000000..c2aa954
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4b_2.sp ('sky130_fd_sc_lp__and4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4b/sky130_fd_sc_lp__and4b_2.spice ('sky130_fd_sc_lp__and4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4b_2 sky130_fd_sc_lp__and4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_2.pex.spice b/cells/and4b/sky130_fd_sc_lp__and4b_2.pex.spice
index 6281f87..e2ea9f7 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_2.pex.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_2.pex.spice
-* Created: Fri Aug 28 10:08:33 2020
+* Created: Wed Sep 2 09:33:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_2.pxi.spice b/cells/and4b/sky130_fd_sc_lp__and4b_2.pxi.spice
index f7559c8..57bfd0e 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_2.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_2.pxi.spice
-* Created: Fri Aug 28 10:08:33 2020
+* Created: Wed Sep 2 09:33:34 2020
*
x_PM_SKY130_FD_SC_LP__AND4B_2%A_N N_A_N_M1008_g N_A_N_M1012_g N_A_N_c_82_n
+ N_A_N_c_83_n A_N A_N N_A_N_c_85_n N_A_N_c_86_n PM_SKY130_FD_SC_LP__AND4B_2%A_N
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_2.spice b/cells/and4b/sky130_fd_sc_lp__and4b_2.spice
index b00d76f..f986532 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_2.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_2.spice
-* Created: Fri Aug 28 10:08:33 2020
+* Created: Wed Sep 2 09:33:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_4.lvs.report b/cells/and4b/sky130_fd_sc_lp__and4b_4.lvs.report
new file mode 100644
index 0000000..4385281
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4b_4.sp ('sky130_fd_sc_lp__and4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4b/sky130_fd_sc_lp__and4b_4.spice ('sky130_fd_sc_lp__and4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4b_4 sky130_fd_sc_lp__and4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_4.pex.spice b/cells/and4b/sky130_fd_sc_lp__and4b_4.pex.spice
index 223575d..80654d8 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_4.pex.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_4.pex.spice
-* Created: Fri Aug 28 10:08:40 2020
+* Created: Wed Sep 2 09:33:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_4.pxi.spice b/cells/and4b/sky130_fd_sc_lp__and4b_4.pxi.spice
index b11c7e5..bb45bb7 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_4.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_4.pxi.spice
-* Created: Fri Aug 28 10:08:40 2020
+* Created: Wed Sep 2 09:33:40 2020
*
x_PM_SKY130_FD_SC_LP__AND4B_4%A_N N_A_N_M1017_g N_A_N_M1010_g A_N A_N A_N A_N
+ A_N N_A_N_c_90_n N_A_N_c_91_n PM_SKY130_FD_SC_LP__AND4B_4%A_N
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_4.spice b/cells/and4b/sky130_fd_sc_lp__and4b_4.spice
index c036a7e..aa52680 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_4.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_4.spice
-* Created: Fri Aug 28 10:08:40 2020
+* Created: Wed Sep 2 09:33:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_lp.lvs.report b/cells/and4b/sky130_fd_sc_lp__and4b_lp.lvs.report
new file mode 100644
index 0000000..624a248
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4b_lp.sp ('sky130_fd_sc_lp__and4b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4b/sky130_fd_sc_lp__and4b_lp.spice ('sky130_fd_sc_lp__and4b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4b_lp sky130_fd_sc_lp__and4b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and4b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A_N X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_lp.pex.spice b/cells/and4b/sky130_fd_sc_lp__and4b_lp.pex.spice
index acc88fc..e1f4409 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_lp.pex.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_lp.pex.spice
-* Created: Fri Aug 28 10:08:48 2020
+* Created: Wed Sep 2 09:33:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_lp.pxi.spice b/cells/and4b/sky130_fd_sc_lp__and4b_lp.pxi.spice
index 8606c84..38bdc4a 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_lp.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_lp.pxi.spice
-* Created: Fri Aug 28 10:08:48 2020
+* Created: Wed Sep 2 09:33:47 2020
*
x_PM_SKY130_FD_SC_LP__AND4B_LP%A_84_21# N_A_84_21#_M1010_d N_A_84_21#_M1013_d
+ N_A_84_21#_M1011_d N_A_84_21#_c_95_n N_A_84_21#_M1006_g N_A_84_21#_M1004_g
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_lp.spice b/cells/and4b/sky130_fd_sc_lp__and4b_lp.spice
index bac7259..b67a1e8 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_lp.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_lp.spice
-* Created: Fri Aug 28 10:08:48 2020
+* Created: Wed Sep 2 09:33:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_m.lvs.report b/cells/and4b/sky130_fd_sc_lp__and4b_m.lvs.report
new file mode 100644
index 0000000..f444e2c
--- /dev/null
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4b_m.sp ('sky130_fd_sc_lp__and4b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4b/sky130_fd_sc_lp__and4b_m.spice ('sky130_fd_sc_lp__and4b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4b_m sky130_fd_sc_lp__and4b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and4b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_m.pex.spice b/cells/and4b/sky130_fd_sc_lp__and4b_m.pex.spice
index b800bce..22cfcc9 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_m.pex.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_m.pex.spice
-* Created: Fri Aug 28 10:08:56 2020
+* Created: Wed Sep 2 09:33:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_m.pxi.spice b/cells/and4b/sky130_fd_sc_lp__and4b_m.pxi.spice
index 26f074f..5471814 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_m.pxi.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_m.pxi.spice
-* Created: Fri Aug 28 10:08:56 2020
+* Created: Wed Sep 2 09:33:54 2020
*
x_PM_SKY130_FD_SC_LP__AND4B_M%A_N N_A_N_M1007_g N_A_N_c_84_n N_A_N_c_85_n
+ N_A_N_c_86_n N_A_N_M1008_g N_A_N_c_81_n A_N N_A_N_c_82_n N_A_N_c_83_n
diff --git a/cells/and4b/sky130_fd_sc_lp__and4b_m.spice b/cells/and4b/sky130_fd_sc_lp__and4b_m.spice
index 2099425..7e1c1ca 100644
--- a/cells/and4b/sky130_fd_sc_lp__and4b_m.spice
+++ b/cells/and4b/sky130_fd_sc_lp__and4b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4b_m.spice
-* Created: Fri Aug 28 10:08:56 2020
+* Created: Wed Sep 2 09:33:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.lvs.report b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.lvs.report
new file mode 100644
index 0000000..77cefa3
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4bb_1.sp ('sky130_fd_sc_lp__and4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4bb/sky130_fd_sc_lp__and4bb_1.spice ('sky130_fd_sc_lp__and4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:33:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4bb_1 sky130_fd_sc_lp__and4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4bb_1
+SOURCE CELL NAME: sky130_fd_sc_lp__and4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pex.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pex.spice
index 42c5be0..6c1edf4 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_1.pex.spice
-* Created: Fri Aug 28 10:09:03 2020
+* Created: Wed Sep 2 09:34:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pxi.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pxi.spice
index 97e64ca..eb08ebe 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_1.pxi.spice
-* Created: Fri Aug 28 10:09:03 2020
+* Created: Wed Sep 2 09:34:01 2020
*
x_PM_SKY130_FD_SC_LP__AND4BB_1%A_N N_A_N_M1009_g N_A_N_M1003_g N_A_N_c_99_n A_N
+ A_N N_A_N_c_100_n N_A_N_c_101_n A_N PM_SKY130_FD_SC_LP__AND4BB_1%A_N
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.spice
index 9815f53..90b7ca9 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_1.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_1.spice
-* Created: Fri Aug 28 10:09:03 2020
+* Created: Wed Sep 2 09:34:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.lvs.report b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.lvs.report
new file mode 100644
index 0000000..d641633
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4bb_2.sp ('sky130_fd_sc_lp__and4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4bb/sky130_fd_sc_lp__and4bb_2.spice ('sky130_fd_sc_lp__and4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4bb_2 sky130_fd_sc_lp__and4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4bb_2
+SOURCE CELL NAME: sky130_fd_sc_lp__and4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C D B_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pex.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pex.spice
index a3a6862..ef9c917 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_2.pex.spice
-* Created: Fri Aug 28 10:09:20 2020
+* Created: Wed Sep 2 09:34:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pxi.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pxi.spice
index 5b8b80d..11db55d 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_2.pxi.spice
-* Created: Fri Aug 28 10:09:20 2020
+* Created: Wed Sep 2 09:34:08 2020
*
x_PM_SKY130_FD_SC_LP__AND4BB_2%A_N N_A_N_M1013_g N_A_N_c_100_n N_A_N_M1009_g A_N
+ N_A_N_c_101_n PM_SKY130_FD_SC_LP__AND4BB_2%A_N
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.spice
index 2d9be3b..91b7e4c 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_2.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_2.spice
-* Created: Fri Aug 28 10:09:20 2020
+* Created: Wed Sep 2 09:34:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.lvs.report b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.lvs.report
new file mode 100644
index 0000000..850a7c1
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4bb_4.sp ('sky130_fd_sc_lp__and4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4bb/sky130_fd_sc_lp__and4bb_4.spice ('sky130_fd_sc_lp__and4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4bb_4 sky130_fd_sc_lp__and4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4bb_4
+SOURCE CELL NAME: sky130_fd_sc_lp__and4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N D C A_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pex.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pex.spice
index f0eb7ee..9eb5916 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_4.pex.spice
-* Created: Fri Aug 28 10:09:28 2020
+* Created: Wed Sep 2 09:34:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pxi.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pxi.spice
index 28b1255..0a03f7a 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_4.pxi.spice
-* Created: Fri Aug 28 10:09:28 2020
+* Created: Wed Sep 2 09:34:15 2020
*
x_PM_SKY130_FD_SC_LP__AND4BB_4%B_N N_B_N_M1001_g N_B_N_M1012_g B_N B_N B_N B_N
+ B_N N_B_N_c_110_n N_B_N_c_111_n PM_SKY130_FD_SC_LP__AND4BB_4%B_N
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.spice
index 414acbb..3e2e23b 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_4.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_4.spice
-* Created: Fri Aug 28 10:09:28 2020
+* Created: Wed Sep 2 09:34:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.lvs.report b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.lvs.report
new file mode 100644
index 0000000..5adc150
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4bb_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4bb_lp.sp ('sky130_fd_sc_lp__and4bb_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.spice ('sky130_fd_sc_lp__and4bb_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4bb_lp sky130_fd_sc_lp__and4bb_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4bb_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__and4bb_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 18 17
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pex.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pex.spice
index 8048b45..54f313c 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_lp.pex.spice
-* Created: Fri Aug 28 10:09:35 2020
+* Created: Wed Sep 2 09:34:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pxi.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pxi.spice
index dd84fdd..8da9f04 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_lp.pxi.spice
-* Created: Fri Aug 28 10:09:35 2020
+* Created: Wed Sep 2 09:34:21 2020
*
x_PM_SKY130_FD_SC_LP__AND4BB_LP%A_N N_A_N_c_109_n N_A_N_M1009_g N_A_N_M1012_g
+ N_A_N_c_111_n N_A_N_M1002_g A_N N_A_N_c_113_n
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.spice
index 300e569..b8a71bb 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_lp.spice
-* Created: Fri Aug 28 10:09:35 2020
+* Created: Wed Sep 2 09:34:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.lvs.report b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.lvs.report
new file mode 100644
index 0000000..b306fc1
--- /dev/null
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__and4bb_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__and4bb_m.sp ('sky130_fd_sc_lp__and4bb_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/and4bb/sky130_fd_sc_lp__and4bb_m.spice ('sky130_fd_sc_lp__and4bb_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__and4bb_m sky130_fd_sc_lp__and4bb_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__and4bb_m
+SOURCE CELL NAME: sky130_fd_sc_lp__and4bb_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pex.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pex.spice
index ae646a9..4e1f3a7 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pex.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_m.pex.spice
-* Created: Fri Aug 28 10:09:42 2020
+* Created: Wed Sep 2 09:34:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pxi.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pxi.spice
index 3dbe9ff..a8a4dff 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pxi.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_m.pxi.spice
-* Created: Fri Aug 28 10:09:42 2020
+* Created: Wed Sep 2 09:34:28 2020
*
x_PM_SKY130_FD_SC_LP__AND4BB_M%A_N N_A_N_M1000_g N_A_N_M1010_g N_A_N_c_94_n
+ N_A_N_c_95_n N_A_N_c_96_n A_N A_N N_A_N_c_98_n
diff --git a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.spice b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.spice
index c7464ed..2f0e4f1 100644
--- a/cells/and4bb/sky130_fd_sc_lp__and4bb_m.spice
+++ b/cells/and4bb/sky130_fd_sc_lp__and4bb_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__and4bb_m.spice
-* Created: Fri Aug 28 10:09:42 2020
+* Created: Wed Sep 2 09:34:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_0.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_0.lvs.report
new file mode 100644
index 0000000..a7d5076
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_0.sp ('sky130_fd_sc_lp__buf_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_0.spice ('sky130_fd_sc_lp__buf_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_0 sky130_fd_sc_lp__buf_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_0
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_0.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_0.pex.spice
index 4dc42c7..af881b4 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_0.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_0.pex.spice
-* Created: Fri Aug 28 10:09:49 2020
+* Created: Wed Sep 2 09:34:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_0.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_0.pxi.spice
index 60ebcae..7779b55 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_0.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_0.pxi.spice
-* Created: Fri Aug 28 10:09:49 2020
+* Created: Wed Sep 2 09:34:35 2020
*
x_PM_SKY130_FD_SC_LP__BUF_0%A_70_157# N_A_70_157#_M1000_d N_A_70_157#_M1002_d
+ N_A_70_157#_M1003_g N_A_70_157#_M1001_g N_A_70_157#_c_42_n N_A_70_157#_c_43_n
diff --git a/cells/buf/sky130_fd_sc_lp__buf_0.spice b/cells/buf/sky130_fd_sc_lp__buf_0.spice
index 7b0dcd4..a894a42 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_0.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_0.spice
-* Created: Fri Aug 28 10:09:49 2020
+* Created: Wed Sep 2 09:34:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_1.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_1.lvs.report
new file mode 100644
index 0000000..7d29018
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_1.sp ('sky130_fd_sc_lp__buf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_1.spice ('sky130_fd_sc_lp__buf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_1 sky130_fd_sc_lp__buf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_1
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_1.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_1.pex.spice
index 08f256f..9c177d1 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_1.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_1.pex.spice
-* Created: Fri Aug 28 10:10:04 2020
+* Created: Wed Sep 2 09:34:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_1.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_1.pxi.spice
index ddaa99e..929d21b 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_1.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_1.pxi.spice
-* Created: Fri Aug 28 10:10:04 2020
+* Created: Wed Sep 2 09:34:49 2020
*
x_PM_SKY130_FD_SC_LP__BUF_1%A_70_237# N_A_70_237#_M1002_d N_A_70_237#_M1000_d
+ N_A_70_237#_M1001_g N_A_70_237#_M1003_g N_A_70_237#_c_36_n N_A_70_237#_c_37_n
diff --git a/cells/buf/sky130_fd_sc_lp__buf_1.spice b/cells/buf/sky130_fd_sc_lp__buf_1.spice
index df6059a..a9c05e6 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_1.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_1.spice
-* Created: Fri Aug 28 10:10:04 2020
+* Created: Wed Sep 2 09:34:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_16.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_16.lvs.report
new file mode 100644
index 0000000..df18a6c
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_16.sp ('sky130_fd_sc_lp__buf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_16.spice ('sky130_fd_sc_lp__buf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_16 sky130_fd_sc_lp__buf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_16
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 44 layout mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+ 44 source mos transistors were reduced to 4.
+ 40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_16.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_16.pex.spice
index 79ff84f..c4319c2 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_16.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_16.pex.spice
-* Created: Fri Aug 28 10:09:57 2020
+* Created: Wed Sep 2 09:34:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_16.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_16.pxi.spice
index a54f407..c569a91 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_16.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_16.pxi.spice
-* Created: Fri Aug 28 10:09:57 2020
+* Created: Wed Sep 2 09:34:42 2020
*
x_PM_SKY130_FD_SC_LP__BUF_16%A N_A_M1005_g N_A_M1000_g N_A_M1009_g N_A_M1008_g
+ N_A_M1023_g N_A_M1015_g N_A_M1028_g N_A_M1021_g N_A_M1036_g N_A_M1033_g
diff --git a/cells/buf/sky130_fd_sc_lp__buf_16.spice b/cells/buf/sky130_fd_sc_lp__buf_16.spice
index 227eee2..aefb466 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_16.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_16.spice
-* Created: Fri Aug 28 10:09:57 2020
+* Created: Wed Sep 2 09:34:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_2.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_2.lvs.report
new file mode 100644
index 0000000..c1ef892
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_2.sp ('sky130_fd_sc_lp__buf_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_2.spice ('sky130_fd_sc_lp__buf_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_2 sky130_fd_sc_lp__buf_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_2
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_2.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_2.pex.spice
index b2e3fd8..00246d7 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_2.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_2.pex.spice
-* Created: Fri Aug 28 10:10:18 2020
+* Created: Wed Sep 2 09:34:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_2.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_2.pxi.spice
index 650a7a7..57f32cd 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_2.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_2.pxi.spice
-* Created: Fri Aug 28 10:10:18 2020
+* Created: Wed Sep 2 09:34:55 2020
*
x_PM_SKY130_FD_SC_LP__BUF_2%A_90_21# N_A_90_21#_M1004_d N_A_90_21#_M1002_d
+ N_A_90_21#_M1000_g N_A_90_21#_c_44_n N_A_90_21#_M1001_g N_A_90_21#_c_39_n
diff --git a/cells/buf/sky130_fd_sc_lp__buf_2.spice b/cells/buf/sky130_fd_sc_lp__buf_2.spice
index ad6fd05..d430593 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_2.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_2.spice
-* Created: Fri Aug 28 10:10:18 2020
+* Created: Wed Sep 2 09:34:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_4.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_4.lvs.report
new file mode 100644
index 0000000..e72b6f8
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_4.sp ('sky130_fd_sc_lp__buf_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_4.spice ('sky130_fd_sc_lp__buf_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:34:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_4 sky130_fd_sc_lp__buf_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_4
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_4.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_4.pex.spice
index ab4245f..254266f 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_4.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_4.pex.spice
-* Created: Fri Aug 28 10:10:27 2020
+* Created: Wed Sep 2 09:35:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_4.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_4.pxi.spice
index f7f94c1..62953a0 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_4.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_4.pxi.spice
-* Created: Fri Aug 28 10:10:27 2020
+* Created: Wed Sep 2 09:35:02 2020
*
x_PM_SKY130_FD_SC_LP__BUF_4%A_122_23# N_A_122_23#_M1001_d N_A_122_23#_M1000_d
+ N_A_122_23#_M1002_g N_A_122_23#_M1004_g N_A_122_23#_M1003_g
diff --git a/cells/buf/sky130_fd_sc_lp__buf_4.spice b/cells/buf/sky130_fd_sc_lp__buf_4.spice
index eb7b87a..043587c 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_4.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_4.spice
-* Created: Fri Aug 28 10:10:27 2020
+* Created: Wed Sep 2 09:35:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_8.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_8.lvs.report
new file mode 100644
index 0000000..f0c1d01
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_8.sp ('sky130_fd_sc_lp__buf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_8.spice ('sky130_fd_sc_lp__buf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_8 sky130_fd_sc_lp__buf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_8
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_8.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_8.pex.spice
index cdcf985..34a921c 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_8.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_8.pex.spice
-* Created: Fri Aug 28 10:10:34 2020
+* Created: Wed Sep 2 09:35:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_8.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_8.pxi.spice
index 7a0f0ea..42064a3 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_8.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_8.pxi.spice
-* Created: Fri Aug 28 10:10:34 2020
+* Created: Wed Sep 2 09:35:09 2020
*
x_PM_SKY130_FD_SC_LP__BUF_8%A N_A_M1006_g N_A_M1000_g N_A_M1012_g N_A_M1007_g
+ N_A_M1021_g N_A_M1020_g N_A_c_126_p A A N_A_c_116_n N_A_c_117_n A N_A_c_118_n
diff --git a/cells/buf/sky130_fd_sc_lp__buf_8.spice b/cells/buf/sky130_fd_sc_lp__buf_8.spice
index e5e8f64..366f236 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_8.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_8.spice
-* Created: Fri Aug 28 10:10:34 2020
+* Created: Wed Sep 2 09:35:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_lp.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_lp.lvs.report
new file mode 100644
index 0000000..6fef387
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_lp.sp ('sky130_fd_sc_lp__buf_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_lp.spice ('sky130_fd_sc_lp__buf_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_lp sky130_fd_sc_lp__buf_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_lp.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_lp.pex.spice
index d14174a..2907ffa 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_lp.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_lp.pex.spice
-* Created: Fri Aug 28 10:10:42 2020
+* Created: Wed Sep 2 09:35:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_lp.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_lp.pxi.spice
index 404a361..95f27cb 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_lp.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_lp.pxi.spice
-* Created: Fri Aug 28 10:10:42 2020
+* Created: Wed Sep 2 09:35:16 2020
*
x_PM_SKY130_FD_SC_LP__BUF_LP%A_94_31# N_A_94_31#_M1003_d N_A_94_31#_M1001_d
+ N_A_94_31#_M1000_g N_A_94_31#_c_35_n N_A_94_31#_M1004_g N_A_94_31#_M1005_g
diff --git a/cells/buf/sky130_fd_sc_lp__buf_lp.spice b/cells/buf/sky130_fd_sc_lp__buf_lp.spice
index 5eb326e..aebf2ee 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_lp.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_lp.spice
-* Created: Fri Aug 28 10:10:42 2020
+* Created: Wed Sep 2 09:35:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buf/sky130_fd_sc_lp__buf_m.lvs.report b/cells/buf/sky130_fd_sc_lp__buf_m.lvs.report
new file mode 100644
index 0000000..345a367
--- /dev/null
+++ b/cells/buf/sky130_fd_sc_lp__buf_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buf_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buf_m.sp ('sky130_fd_sc_lp__buf_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buf/sky130_fd_sc_lp__buf_m.spice ('sky130_fd_sc_lp__buf_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buf_m sky130_fd_sc_lp__buf_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buf_m
+SOURCE CELL NAME: sky130_fd_sc_lp__buf_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buf/sky130_fd_sc_lp__buf_m.pex.spice b/cells/buf/sky130_fd_sc_lp__buf_m.pex.spice
index 250ebdb..409bd7c 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_m.pex.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_m.pex.spice
-* Created: Fri Aug 28 10:10:50 2020
+* Created: Wed Sep 2 09:35:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buf/sky130_fd_sc_lp__buf_m.pxi.spice b/cells/buf/sky130_fd_sc_lp__buf_m.pxi.spice
index d5bff47..3f0f6c7 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_m.pxi.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_m.pxi.spice
-* Created: Fri Aug 28 10:10:50 2020
+* Created: Wed Sep 2 09:35:22 2020
*
x_PM_SKY130_FD_SC_LP__BUF_M%A_47_178# N_A_47_178#_M1002_d N_A_47_178#_M1001_d
+ N_A_47_178#_c_34_n N_A_47_178#_c_35_n N_A_47_178#_M1000_g N_A_47_178#_M1003_g
diff --git a/cells/buf/sky130_fd_sc_lp__buf_m.spice b/cells/buf/sky130_fd_sc_lp__buf_m.spice
index 1a65219..277b7c2 100644
--- a/cells/buf/sky130_fd_sc_lp__buf_m.spice
+++ b/cells/buf/sky130_fd_sc_lp__buf_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buf_m.spice
-* Created: Fri Aug 28 10:10:50 2020
+* Created: Wed Sep 2 09:35:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.lvs.report b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.lvs.report
new file mode 100644
index 0000000..477b336
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufbuf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufbuf_16.sp ('sky130_fd_sc_lp__bufbuf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.spice ('sky130_fd_sc_lp__bufbuf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufbuf_16 sky130_fd_sc_lp__bufbuf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufbuf_16
+SOURCE CELL NAME: sky130_fd_sc_lp__bufbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 26 26 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pex.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pex.spice
index 2a69661..0169d15 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_16.pex.spice
-* Created: Fri Aug 28 10:10:58 2020
+* Created: Wed Sep 2 09:35:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pxi.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pxi.spice
index 369810b..758d053 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_16.pxi.spice
-* Created: Fri Aug 28 10:10:58 2020
+* Created: Wed Sep 2 09:35:29 2020
*
x_PM_SKY130_FD_SC_LP__BUFBUF_16%A N_A_M1018_g N_A_M1051_g A N_A_c_242_n
+ N_A_c_243_n PM_SKY130_FD_SC_LP__BUFBUF_16%A
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.spice
index 58cc430..c7142c0 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_16.spice
-* Created: Fri Aug 28 10:10:58 2020
+* Created: Wed Sep 2 09:35:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.lvs.report b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.lvs.report
new file mode 100644
index 0000000..6a80d71
--- /dev/null
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufbuf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufbuf_8.sp ('sky130_fd_sc_lp__bufbuf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.spice ('sky130_fd_sc_lp__bufbuf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufbuf_8 sky130_fd_sc_lp__bufbuf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufbuf_8
+SOURCE CELL NAME: sky130_fd_sc_lp__bufbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pex.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pex.spice
index 46b8515..93031b8 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pex.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_8.pex.spice
-* Created: Fri Aug 28 10:11:06 2020
+* Created: Wed Sep 2 09:35:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pxi.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pxi.spice
index d1e17f1..b5a58f5 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pxi.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_8.pxi.spice
-* Created: Fri Aug 28 10:11:06 2020
+* Created: Wed Sep 2 09:35:35 2020
*
x_PM_SKY130_FD_SC_LP__BUFBUF_8%A_117_265# N_A_117_265#_M1004_d
+ N_A_117_265#_M1018_d N_A_117_265#_M1000_d N_A_117_265#_M1025_d
diff --git a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.spice b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.spice
index 84a7fc1..956230f 100644
--- a/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.spice
+++ b/cells/bufbuf/sky130_fd_sc_lp__bufbuf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufbuf_8.spice
-* Created: Fri Aug 28 10:11:06 2020
+* Created: Wed Sep 2 09:35:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.lvs.report b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.lvs.report
new file mode 100644
index 0000000..52aedf4
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufinv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufinv_16.sp ('sky130_fd_sc_lp__bufinv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufinv/sky130_fd_sc_lp__bufinv_16.spice ('sky130_fd_sc_lp__bufinv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufinv_16 sky130_fd_sc_lp__bufinv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufinv_16
+SOURCE CELL NAME: sky130_fd_sc_lp__bufinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 25 25 MN (4 pins)
+ 25 25 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 51 50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 6.
+ 44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pex.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pex.spice
index 07d9123..045dc1a 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_16.pex.spice
-* Created: Fri Aug 28 10:11:20 2020
+* Created: Wed Sep 2 09:35:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pxi.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pxi.spice
index 2a4391f..26a49d0 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_16.pxi.spice
-* Created: Fri Aug 28 10:11:20 2020
+* Created: Wed Sep 2 09:35:42 2020
*
x_PM_SKY130_FD_SC_LP__BUFINV_16%A N_A_M1006_g N_A_M1008_g N_A_M1017_g
+ N_A_M1022_g N_A_M1040_g N_A_M1026_g A A A N_A_c_202_n N_A_c_203_n N_A_c_204_n
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.spice
index 940c5d1..ff0db66 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_16.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_16.spice
-* Created: Fri Aug 28 10:11:20 2020
+* Created: Wed Sep 2 09:35:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.lvs.report b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.lvs.report
new file mode 100644
index 0000000..138b22b
--- /dev/null
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufinv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufinv_8.sp ('sky130_fd_sc_lp__bufinv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufinv/sky130_fd_sc_lp__bufinv_8.spice ('sky130_fd_sc_lp__bufinv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufinv_8 sky130_fd_sc_lp__bufinv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufinv_8
+SOURCE CELL NAME: sky130_fd_sc_lp__bufinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 22 layout mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+ 22 source mos transistors were reduced to 4.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pex.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pex.spice
index 78f10aa..98126a1 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pex.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_8.pex.spice
-* Created: Fri Aug 28 10:11:30 2020
+* Created: Wed Sep 2 09:35:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pxi.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pxi.spice
index 8f018c7..e1abac0 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pxi.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_8.pxi.spice
-* Created: Fri Aug 28 10:11:30 2020
+* Created: Wed Sep 2 09:35:48 2020
*
x_PM_SKY130_FD_SC_LP__BUFINV_8%A_82_23# N_A_82_23#_M1002_d N_A_82_23#_M1008_d
+ N_A_82_23#_M1001_s N_A_82_23#_M1010_s N_A_82_23#_M1004_g N_A_82_23#_M1000_g
diff --git a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.spice b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.spice
index 1f4cb2e..a4f8686 100644
--- a/cells/bufinv/sky130_fd_sc_lp__bufinv_8.spice
+++ b/cells/bufinv/sky130_fd_sc_lp__bufinv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufinv_8.spice
-* Created: Fri Aug 28 10:11:30 2020
+* Created: Wed Sep 2 09:35:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.lvs.report b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.lvs.report
new file mode 100644
index 0000000..f1750d5
--- /dev/null
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufkapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufkapwr_1.sp ('sky130_fd_sc_lp__bufkapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.spice ('sky130_fd_sc_lp__bufkapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufkapwr_1 sky130_fd_sc_lp__bufkapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufkapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__bufkapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X KAPWR VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pex.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pex.spice
index a4dc0fb..c858164 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pex.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_1.pex.spice
-* Created: Fri Aug 28 10:11:38 2020
+* Created: Wed Sep 2 09:35:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pxi.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pxi.spice
index 13b3ec3..e3b1daf 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pxi.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_1.pxi.spice
-* Created: Fri Aug 28 10:11:38 2020
+* Created: Wed Sep 2 09:35:55 2020
*
x_PM_SKY130_FD_SC_LP__BUFKAPWR_1%A_69_161# N_A_69_161#_M1002_d
+ N_A_69_161#_M1000_d N_A_69_161#_M1001_g N_A_69_161#_M1003_g N_A_69_161#_c_33_n
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.spice
index 2eb72ba..c759a1c 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_1.spice
-* Created: Fri Aug 28 10:11:38 2020
+* Created: Wed Sep 2 09:35:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.lvs.report b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.lvs.report
new file mode 100644
index 0000000..a6cbaf2
--- /dev/null
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufkapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufkapwr_2.sp ('sky130_fd_sc_lp__bufkapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.spice ('sky130_fd_sc_lp__bufkapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:35:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufkapwr_2 sky130_fd_sc_lp__bufkapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufkapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__bufkapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pex.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pex.spice
index 69ff20f..963614d 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pex.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_2.pex.spice
-* Created: Fri Aug 28 10:11:45 2020
+* Created: Wed Sep 2 09:36:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pxi.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pxi.spice
index c75f695..2540613 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pxi.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_2.pxi.spice
-* Created: Fri Aug 28 10:11:45 2020
+* Created: Wed Sep 2 09:36:01 2020
*
x_PM_SKY130_FD_SC_LP__BUFKAPWR_2%A N_A_M1002_g N_A_M1005_g A N_A_c_38_n
+ N_A_c_39_n PM_SKY130_FD_SC_LP__BUFKAPWR_2%A
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.spice
index f3a569f..03f6e56 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_2.spice
-* Created: Fri Aug 28 10:11:45 2020
+* Created: Wed Sep 2 09:36:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.lvs.report b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.lvs.report
new file mode 100644
index 0000000..5e0da02
--- /dev/null
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufkapwr_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufkapwr_4.sp ('sky130_fd_sc_lp__bufkapwr_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.spice ('sky130_fd_sc_lp__bufkapwr_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufkapwr_4 sky130_fd_sc_lp__bufkapwr_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufkapwr_4
+SOURCE CELL NAME: sky130_fd_sc_lp__bufkapwr_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pex.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pex.spice
index 487ad78..9d2df9d 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pex.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_4.pex.spice
-* Created: Fri Aug 28 10:11:53 2020
+* Created: Wed Sep 2 09:36:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pxi.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pxi.spice
index 56f0f25..8ee140a 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pxi.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_4.pxi.spice
-* Created: Fri Aug 28 10:11:53 2020
+* Created: Wed Sep 2 09:36:08 2020
*
x_PM_SKY130_FD_SC_LP__BUFKAPWR_4%A N_A_M1004_g N_A_M1009_g A N_A_c_51_n
+ N_A_c_52_n PM_SKY130_FD_SC_LP__BUFKAPWR_4%A
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.spice
index 6c72ed2..684eda2 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_4.spice
-* Created: Fri Aug 28 10:11:53 2020
+* Created: Wed Sep 2 09:36:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.lvs.report b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.lvs.report
new file mode 100644
index 0000000..b8472ae
--- /dev/null
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bufkapwr_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bufkapwr_8.sp ('sky130_fd_sc_lp__bufkapwr_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.spice ('sky130_fd_sc_lp__bufkapwr_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bufkapwr_8 sky130_fd_sc_lp__bufkapwr_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bufkapwr_8
+SOURCE CELL NAME: sky130_fd_sc_lp__bufkapwr_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pex.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pex.spice
index 855ea88..83a707d 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pex.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_8.pex.spice
-* Created: Fri Aug 28 10:12:00 2020
+* Created: Wed Sep 2 09:36:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pxi.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pxi.spice
index 2c51f79..99233c6 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pxi.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_8.pxi.spice
-* Created: Fri Aug 28 10:12:00 2020
+* Created: Wed Sep 2 09:36:14 2020
*
x_PM_SKY130_FD_SC_LP__BUFKAPWR_8%A N_A_M1005_g N_A_M1006_g N_A_M1011_g
+ N_A_M1018_g A A N_A_c_89_n PM_SKY130_FD_SC_LP__BUFKAPWR_8%A
diff --git a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.spice b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.spice
index 798840b..5b247d9 100644
--- a/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.spice
+++ b/cells/bufkapwr/sky130_fd_sc_lp__bufkapwr_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bufkapwr_8.spice
-* Created: Fri Aug 28 10:12:00 2020
+* Created: Wed Sep 2 09:36:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_0.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_0.lvs.report
new file mode 100644
index 0000000..466b410
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_0.sp ('sky130_fd_sc_lp__buflp_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_0.spice ('sky130_fd_sc_lp__buflp_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_0 sky130_fd_sc_lp__buflp_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_0
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_0.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_0.pex.spice
index 3f08c5c..3955f26 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_0.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_0.pex.spice
-* Created: Fri Aug 28 10:12:08 2020
+* Created: Wed Sep 2 09:36:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_0.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_0.pxi.spice
index b5bd377..e105f32 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_0.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_0.pxi.spice
-* Created: Fri Aug 28 10:12:08 2020
+* Created: Wed Sep 2 09:36:21 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_0%A N_A_M1007_g N_A_M1006_g N_A_M1003_g N_A_M1000_g
+ A A A A N_A_c_41_n PM_SKY130_FD_SC_LP__BUFLP_0%A
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_0.spice b/cells/buflp/sky130_fd_sc_lp__buflp_0.spice
index c86a12a..8acbc55 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_0.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_0.spice
-* Created: Fri Aug 28 10:12:08 2020
+* Created: Wed Sep 2 09:36:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_1.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_1.lvs.report
new file mode 100644
index 0000000..0a91e0c
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_1.sp ('sky130_fd_sc_lp__buflp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_1.spice ('sky130_fd_sc_lp__buflp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_1 sky130_fd_sc_lp__buflp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_1.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_1.pex.spice
index 3f58b9e..cd29a88 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_1.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_1.pex.spice
-* Created: Fri Aug 28 10:12:22 2020
+* Created: Wed Sep 2 09:36:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_1.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_1.pxi.spice
index 0cf9ad8..63b0ba8 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_1.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_1.pxi.spice
-* Created: Fri Aug 28 10:12:22 2020
+* Created: Wed Sep 2 09:36:27 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_1%A_86_21# N_A_86_21#_M1004_d N_A_86_21#_M1001_d
+ N_A_86_21#_M1003_g N_A_86_21#_M1002_g N_A_86_21#_c_38_n N_A_86_21#_M1000_g
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_1.spice b/cells/buflp/sky130_fd_sc_lp__buflp_1.spice
index 92b2c57..86f7325 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_1.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_1.spice
-* Created: Fri Aug 28 10:12:22 2020
+* Created: Wed Sep 2 09:36:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_2.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_2.lvs.report
new file mode 100644
index 0000000..d73c7ae
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_2.sp ('sky130_fd_sc_lp__buflp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_2.spice ('sky130_fd_sc_lp__buflp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_2 sky130_fd_sc_lp__buflp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_2.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_2.pex.spice
index 4712da1..c4a83bb 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_2.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_2.pex.spice
-* Created: Fri Aug 28 10:12:31 2020
+* Created: Wed Sep 2 09:36:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_2.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_2.pxi.spice
index 9cc31ff..e164def 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_2.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_2.pxi.spice
-* Created: Fri Aug 28 10:12:31 2020
+* Created: Wed Sep 2 09:36:34 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_2%A_98_21# N_A_98_21#_M1010_d N_A_98_21#_M1011_d
+ N_A_98_21#_M1003_g N_A_98_21#_M1001_g N_A_98_21#_c_60_n N_A_98_21#_M1005_g
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_2.spice b/cells/buflp/sky130_fd_sc_lp__buflp_2.spice
index e916ca5..31365bf 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_2.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_2.spice
-* Created: Fri Aug 28 10:12:31 2020
+* Created: Wed Sep 2 09:36:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_4.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_4.lvs.report
new file mode 100644
index 0000000..98e9153
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_4.sp ('sky130_fd_sc_lp__buflp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_4.spice ('sky130_fd_sc_lp__buflp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_4 sky130_fd_sc_lp__buflp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_4.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_4.pex.spice
index 3aa0e4f..d0a9d58 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_4.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_4.pex.spice
-* Created: Fri Aug 28 10:12:39 2020
+* Created: Wed Sep 2 09:36:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_4.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_4.pxi.spice
index a7fb6a9..ca0ec60 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_4.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_4.pxi.spice
-* Created: Fri Aug 28 10:12:39 2020
+* Created: Wed Sep 2 09:36:40 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_4%A_84_21# N_A_84_21#_M1006_d N_A_84_21#_M1008_d
+ N_A_84_21#_M1003_g N_A_84_21#_M1000_g N_A_84_21#_M1004_g N_A_84_21#_M1011_g
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_4.spice b/cells/buflp/sky130_fd_sc_lp__buflp_4.spice
index 4dfdf15..aaa92ad 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_4.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_4.spice
-* Created: Fri Aug 28 10:12:39 2020
+* Created: Wed Sep 2 09:36:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_8.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_8.lvs.report
new file mode 100644
index 0000000..90efab8
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_8.sp ('sky130_fd_sc_lp__buflp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_8.spice ('sky130_fd_sc_lp__buflp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_8 sky130_fd_sc_lp__buflp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_8
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 44 layout mos transistors were reduced to 8.
+ 36 mos transistors were deleted by parallel reduction.
+ 44 source mos transistors were reduced to 8.
+ 36 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_8.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_8.pex.spice
index bcb5864..3b8a04d 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_8.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_8.pex.spice
-* Created: Fri Aug 28 10:12:46 2020
+* Created: Wed Sep 2 09:36:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_8.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_8.pxi.spice
index 03b8c8b..2553123 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_8.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_8.pxi.spice
-* Created: Fri Aug 28 10:12:46 2020
+* Created: Wed Sep 2 09:36:47 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_8%A N_A_c_152_n N_A_M1003_g N_A_M1020_g N_A_c_154_n
+ N_A_M1006_g N_A_M1026_g N_A_M1041_g N_A_c_157_n N_A_M1008_g N_A_M1009_g
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_8.spice b/cells/buflp/sky130_fd_sc_lp__buflp_8.spice
index 1f7a777..a0ad73b 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_8.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_8.spice
-* Created: Fri Aug 28 10:12:46 2020
+* Created: Wed Sep 2 09:36:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_m.lvs.report b/cells/buflp/sky130_fd_sc_lp__buflp_m.lvs.report
new file mode 100644
index 0000000..1e490fc
--- /dev/null
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__buflp_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__buflp_m.sp ('sky130_fd_sc_lp__buflp_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/buflp/sky130_fd_sc_lp__buflp_m.spice ('sky130_fd_sc_lp__buflp_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__buflp_m sky130_fd_sc_lp__buflp_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__buflp_m
+SOURCE CELL NAME: sky130_fd_sc_lp__buflp_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_m.pex.spice b/cells/buflp/sky130_fd_sc_lp__buflp_m.pex.spice
index 8d5a8f4..1737da3 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_m.pex.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_m.pex.spice
-* Created: Fri Aug 28 10:12:53 2020
+* Created: Wed Sep 2 09:36:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_m.pxi.spice b/cells/buflp/sky130_fd_sc_lp__buflp_m.pxi.spice
index 283c24f..1d45fc8 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_m.pxi.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_m.pxi.spice
-* Created: Fri Aug 28 10:12:53 2020
+* Created: Wed Sep 2 09:36:53 2020
*
x_PM_SKY130_FD_SC_LP__BUFLP_M%A_90_94# N_A_90_94#_M1005_d N_A_90_94#_M1006_d
+ N_A_90_94#_M1004_g N_A_90_94#_M1003_g N_A_90_94#_M1001_g N_A_90_94#_M1007_g
diff --git a/cells/buflp/sky130_fd_sc_lp__buflp_m.spice b/cells/buflp/sky130_fd_sc_lp__buflp_m.spice
index b865796..890b003 100644
--- a/cells/buflp/sky130_fd_sc_lp__buflp_m.spice
+++ b/cells/buflp/sky130_fd_sc_lp__buflp_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__buflp_m.spice
-* Created: Fri Aug 28 10:12:53 2020
+* Created: Wed Sep 2 09:36:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.lvs.report b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.lvs.report
new file mode 100644
index 0000000..b6c8d8c
--- /dev/null
+++ b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busdriver_20.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busdriver_20.sp ('sky130_fd_sc_lp__busdriver_20')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busdriver/sky130_fd_sc_lp__busdriver_20.spice ('sky130_fd_sc_lp__busdriver_20')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:36:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busdriver_20 sky130_fd_sc_lp__busdriver_20
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busdriver_20
+SOURCE CELL NAME: sky130_fd_sc_lp__busdriver_20
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 36 36 MN (4 pins)
+ 54 54 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 91 90
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 90 layout mos transistors were reduced to 10.
+ 80 mos transistors were deleted by parallel reduction.
+ 90 source mos transistors were reduced to 10.
+ 80 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pex.spice b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pex.spice
index fc429ee..e527a84 100644
--- a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pex.spice
+++ b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver_20.pex.spice
-* Created: Fri Aug 28 10:13:01 2020
+* Created: Wed Sep 2 09:37:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pxi.spice b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pxi.spice
index 50543eb..0d53b00 100644
--- a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pxi.spice
+++ b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver_20.pxi.spice
-* Created: Fri Aug 28 10:13:01 2020
+* Created: Wed Sep 2 09:37:00 2020
*
x_PM_SKY130_FD_SC_LP__BUSDRIVER_20%TE_B N_TE_B_c_388_n N_TE_B_M1018_g
+ N_TE_B_M1059_g N_TE_B_c_390_n N_TE_B_c_391_n N_TE_B_M1021_g N_TE_B_M1088_g
diff --git a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.spice b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.spice
index 3ab7506..ec0f7b5 100644
--- a/cells/busdriver/sky130_fd_sc_lp__busdriver_20.spice
+++ b/cells/busdriver/sky130_fd_sc_lp__busdriver_20.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver_20.spice
-* Created: Fri Aug 28 10:13:01 2020
+* Created: Wed Sep 2 09:37:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.lvs.report b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.lvs.report
new file mode 100644
index 0000000..d4cac62
--- /dev/null
+++ b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busdriver2_20.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busdriver2_20.sp ('sky130_fd_sc_lp__busdriver2_20')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.spice ('sky130_fd_sc_lp__busdriver2_20')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busdriver2_20 sky130_fd_sc_lp__busdriver2_20
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busdriver2_20
+SOURCE CELL NAME: sky130_fd_sc_lp__busdriver2_20
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 36 36 MN (4 pins)
+ 54 54 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 91 90
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 90 layout mos transistors were reduced to 10.
+ 80 mos transistors were deleted by parallel reduction.
+ 90 source mos transistors were reduced to 10.
+ 80 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pex.spice b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pex.spice
index c714e20..61929b5 100644
--- a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pex.spice
+++ b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver2_20.pex.spice
-* Created: Fri Aug 28 10:13:08 2020
+* Created: Wed Sep 2 09:37:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pxi.spice b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pxi.spice
index eb1b5d3..c6aa15a 100644
--- a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pxi.spice
+++ b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver2_20.pxi.spice
-* Created: Fri Aug 28 10:13:08 2020
+* Created: Wed Sep 2 09:37:06 2020
*
x_PM_SKY130_FD_SC_LP__BUSDRIVER2_20%TE_B N_TE_B_c_389_n N_TE_B_M1020_g
+ N_TE_B_M1004_g N_TE_B_c_391_n N_TE_B_c_392_n N_TE_B_M1024_g N_TE_B_M1007_g
diff --git a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.spice b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.spice
index 2919814..3c4fb92 100644
--- a/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.spice
+++ b/cells/busdriver2/sky130_fd_sc_lp__busdriver2_20.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdriver2_20.spice
-* Created: Fri Aug 28 10:13:08 2020
+* Created: Wed Sep 2 09:37:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.lvs.report b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.lvs.report
new file mode 100644
index 0000000..9890120
--- /dev/null
+++ b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busdrivernovlp_20.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busdrivernovlp_20.sp ('sky130_fd_sc_lp__busdrivernovlp_20')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.spice ('sky130_fd_sc_lp__busdrivernovlp_20')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busdrivernovlp_20 sky130_fd_sc_lp__busdrivernovlp_20
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busdrivernovlp_20
+SOURCE CELL NAME: sky130_fd_sc_lp__busdrivernovlp_20
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 27 27 MN (4 pins)
+ 33 33 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 61 60
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 16 16
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 16 16 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 10.
+ 40 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 10.
+ 40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pex.spice b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pex.spice
index e101476..de1155d 100644
--- a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pex.spice
+++ b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp_20.pex.spice
-* Created: Fri Aug 28 10:13:23 2020
+* Created: Wed Sep 2 09:37:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pxi.spice b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pxi.spice
index ec351c4..0af98a7 100644
--- a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pxi.spice
+++ b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp_20.pxi.spice
-* Created: Fri Aug 28 10:13:23 2020
+* Created: Wed Sep 2 09:37:13 2020
*
x_PM_SKY130_FD_SC_LP__BUSDRIVERNOVLP_20%TE_B N_TE_B_M1048_g N_TE_B_c_376_n
+ N_TE_B_M1039_g N_TE_B_c_377_n N_TE_B_c_378_n N_TE_B_c_379_n N_TE_B_c_380_n
diff --git a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.spice b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.spice
index 177f133..da6c425 100644
--- a/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.spice
+++ b/cells/busdrivernovlp/sky130_fd_sc_lp__busdrivernovlp_20.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp_20.spice
-* Created: Fri Aug 28 10:13:23 2020
+* Created: Wed Sep 2 09:37:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.lvs.report b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.lvs.report
new file mode 100644
index 0000000..87c683f
--- /dev/null
+++ b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busdrivernovlp2_20.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busdrivernovlp2_20.sp ('sky130_fd_sc_lp__busdrivernovlp2_20')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.spice ('sky130_fd_sc_lp__busdrivernovlp2_20')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busdrivernovlp2_20 sky130_fd_sc_lp__busdrivernovlp2_20
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busdrivernovlp2_20
+SOURCE CELL NAME: sky130_fd_sc_lp__busdrivernovlp2_20
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 27 27 MN (4 pins)
+ 33 33 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 61 60
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 16 16
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PSHORT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 16 16 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 10.
+ 40 mos transistors were deleted by parallel reduction.
+ 50 source mos transistors were reduced to 10.
+ 40 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pex.spice b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pex.spice
index 657abf0..bb5d5de 100644
--- a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pex.spice
+++ b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp2_20.pex.spice
-* Created: Fri Aug 28 10:13:32 2020
+* Created: Wed Sep 2 09:37:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pxi.spice b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pxi.spice
index 9cedafe..67f2245 100644
--- a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pxi.spice
+++ b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp2_20.pxi.spice
-* Created: Fri Aug 28 10:13:32 2020
+* Created: Wed Sep 2 09:37:20 2020
*
x_PM_SKY130_FD_SC_LP__BUSDRIVERNOVLP2_20%TE_B N_TE_B_M1052_g N_TE_B_c_376_n
+ N_TE_B_M1041_g N_TE_B_c_377_n N_TE_B_c_378_n N_TE_B_c_379_n N_TE_B_c_380_n
diff --git a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.spice b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.spice
index 629dd68..6f102c3 100644
--- a/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.spice
+++ b/cells/busdrivernovlp2/sky130_fd_sc_lp__busdrivernovlp2_20.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlp2_20.spice
-* Created: Fri Aug 28 10:13:32 2020
+* Created: Wed Sep 2 09:37:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.lvs.report b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.lvs.report
new file mode 100644
index 0000000..290c5a0
--- /dev/null
+++ b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busdrivernovlpsleep_20.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busdrivernovlpsleep_20.sp ('sky130_fd_sc_lp__busdrivernovlpsleep_20')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.spice ('sky130_fd_sc_lp__busdrivernovlpsleep_20')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busdrivernovlpsleep_20 sky130_fd_sc_lp__busdrivernovlpsleep_20
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busdrivernovlpsleep_20
+SOURCE CELL NAME: sky130_fd_sc_lp__busdrivernovlpsleep_20
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 33 33 MN (4 pins)
+ 41 41 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 75 74
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 58 layout mos transistors were reduced to 14.
+ 44 mos transistors were deleted by parallel reduction.
+ 58 source mos transistors were reduced to 14.
+ 44 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP TE_B A VPWR KAPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pex.spice b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pex.spice
index 82c62fb..d49ce4a 100644
--- a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pex.spice
+++ b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlpsleep_20.pex.spice
-* Created: Fri Aug 28 10:13:39 2020
+* Created: Wed Sep 2 09:37:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pxi.spice b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pxi.spice
index a75fda3..6527e11 100644
--- a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pxi.spice
+++ b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlpsleep_20.pxi.spice
-* Created: Fri Aug 28 10:13:39 2020
+* Created: Wed Sep 2 09:37:27 2020
*
x_PM_SKY130_FD_SC_LP__BUSDRIVERNOVLPSLEEP_20%SLEEP N_SLEEP_M1030_g
+ N_SLEEP_M1026_g N_SLEEP_M1002_g N_SLEEP_M1006_g N_SLEEP_M1013_g
diff --git a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.spice b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.spice
index 1fd9323..181c298 100644
--- a/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.spice
+++ b/cells/busdrivernovlpsleep/sky130_fd_sc_lp__busdrivernovlpsleep_20.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busdrivernovlpsleep_20.spice
-* Created: Fri Aug 28 10:13:39 2020
+* Created: Wed Sep 2 09:37:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bushold/sky130_fd_sc_lp__bushold_1.lvs.report b/cells/bushold/sky130_fd_sc_lp__bushold_1.lvs.report
new file mode 100644
index 0000000..15aa639
--- /dev/null
+++ b/cells/bushold/sky130_fd_sc_lp__bushold_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bushold_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bushold_1.sp ('sky130_fd_sc_lp__bushold_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bushold/sky130_fd_sc_lp__bushold_1.spice ('sky130_fd_sc_lp__bushold_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bushold_1 sky130_fd_sc_lp__bushold_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bushold_1
+SOURCE CELL NAME: sky130_fd_sc_lp__bushold_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB X RESET VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bushold/sky130_fd_sc_lp__bushold_1.pex.spice b/cells/bushold/sky130_fd_sc_lp__bushold_1.pex.spice
index 6d2b4cc..fd5ca5b 100644
--- a/cells/bushold/sky130_fd_sc_lp__bushold_1.pex.spice
+++ b/cells/bushold/sky130_fd_sc_lp__bushold_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold_1.pex.spice
-* Created: Fri Aug 28 10:13:46 2020
+* Created: Wed Sep 2 09:37:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bushold/sky130_fd_sc_lp__bushold_1.pxi.spice b/cells/bushold/sky130_fd_sc_lp__bushold_1.pxi.spice
index 621b3b5..ccf183a 100644
--- a/cells/bushold/sky130_fd_sc_lp__bushold_1.pxi.spice
+++ b/cells/bushold/sky130_fd_sc_lp__bushold_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold_1.pxi.spice
-* Created: Fri Aug 28 10:13:46 2020
+* Created: Wed Sep 2 09:37:34 2020
*
x_PM_SKY130_FD_SC_LP__BUSHOLD_1%X N_X_M1003_d N_X_M1001_d N_X_M1005_g
+ N_X_M1002_g N_X_c_56_n N_X_c_57_n N_X_c_52_n N_X_c_53_n N_X_c_54_n N_X_c_60_n
diff --git a/cells/bushold/sky130_fd_sc_lp__bushold_1.spice b/cells/bushold/sky130_fd_sc_lp__bushold_1.spice
index 1ad7f2c..a763b67 100644
--- a/cells/bushold/sky130_fd_sc_lp__bushold_1.spice
+++ b/cells/bushold/sky130_fd_sc_lp__bushold_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold_1.spice
-* Created: Fri Aug 28 10:13:46 2020
+* Created: Wed Sep 2 09:37:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.lvs.report b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.lvs.report
new file mode 100644
index 0000000..fc4574b
--- /dev/null
+++ b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__bushold0_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__bushold0_1.sp ('sky130_fd_sc_lp__bushold0_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/bushold0/sky130_fd_sc_lp__bushold0_1.spice ('sky130_fd_sc_lp__bushold0_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__bushold0_1 sky130_fd_sc_lp__bushold0_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__bushold0_1
+SOURCE CELL NAME: sky130_fd_sc_lp__bushold0_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB X RESET VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pex.spice b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pex.spice
index cbcbbc6..3efb8e4 100644
--- a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pex.spice
+++ b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold0_1.pex.spice
-* Created: Fri Aug 28 10:13:54 2020
+* Created: Wed Sep 2 09:37:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pxi.spice b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pxi.spice
index eddb60c..247af4d 100644
--- a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pxi.spice
+++ b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold0_1.pxi.spice
-* Created: Fri Aug 28 10:13:54 2020
+* Created: Wed Sep 2 09:37:40 2020
*
x_PM_SKY130_FD_SC_LP__BUSHOLD0_1%X N_X_M1000_d N_X_M1001_d N_X_M1005_g
+ N_X_M1003_g N_X_c_60_n N_X_c_61_n N_X_c_52_n N_X_c_53_n N_X_c_64_n N_X_c_65_n
diff --git a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.spice b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.spice
index 9c68308..c9e8379 100644
--- a/cells/bushold0/sky130_fd_sc_lp__bushold0_1.spice
+++ b/cells/bushold0/sky130_fd_sc_lp__bushold0_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__bushold0_1.spice
-* Created: Fri Aug 28 10:13:54 2020
+* Created: Wed Sep 2 09:37:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.lvs.report b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.lvs.report
new file mode 100644
index 0000000..9812965
--- /dev/null
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busreceiver_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busreceiver_0.sp ('sky130_fd_sc_lp__busreceiver_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.spice ('sky130_fd_sc_lp__busreceiver_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busreceiver_0 sky130_fd_sc_lp__busreceiver_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busreceiver_0
+SOURCE CELL NAME: sky130_fd_sc_lp__busreceiver_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pex.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pex.spice
index 590f479..0f36c81 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pex.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_0.pex.spice
-* Created: Fri Aug 28 10:14:01 2020
+* Created: Wed Sep 2 09:37:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pxi.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pxi.spice
index dac4f9d..9f63303 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pxi.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_0.pxi.spice
-* Created: Fri Aug 28 10:14:01 2020
+* Created: Wed Sep 2 09:37:47 2020
*
x_PM_SKY130_FD_SC_LP__BUSRECEIVER_0%A_70_157# N_A_70_157#_M1000_d
+ N_A_70_157#_M1002_d N_A_70_157#_M1003_g N_A_70_157#_M1001_g N_A_70_157#_c_42_n
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.spice
index 91b4069..9588324 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_0.spice
-* Created: Fri Aug 28 10:14:01 2020
+* Created: Wed Sep 2 09:37:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.lvs.report b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.lvs.report
new file mode 100644
index 0000000..1e6b58a
--- /dev/null
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busreceiver_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busreceiver_1.sp ('sky130_fd_sc_lp__busreceiver_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.spice ('sky130_fd_sc_lp__busreceiver_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busreceiver_1 sky130_fd_sc_lp__busreceiver_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busreceiver_1
+SOURCE CELL NAME: sky130_fd_sc_lp__busreceiver_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pex.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pex.spice
index cd9cce5..229934a 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pex.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_1.pex.spice
-* Created: Fri Aug 28 10:14:08 2020
+* Created: Wed Sep 2 09:37:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pxi.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pxi.spice
index ffea8d2..3daaed9 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pxi.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_1.pxi.spice
-* Created: Fri Aug 28 10:14:08 2020
+* Created: Wed Sep 2 09:37:54 2020
*
x_PM_SKY130_FD_SC_LP__BUSRECEIVER_1%A_70_237# N_A_70_237#_M1002_d
+ N_A_70_237#_M1000_d N_A_70_237#_M1001_g N_A_70_237#_M1003_g N_A_70_237#_c_36_n
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.spice
index 159f492..8750a9f 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_1.spice
-* Created: Fri Aug 28 10:14:08 2020
+* Created: Wed Sep 2 09:37:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.lvs.report b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.lvs.report
new file mode 100644
index 0000000..a09e714
--- /dev/null
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__busreceiver_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__busreceiver_m.sp ('sky130_fd_sc_lp__busreceiver_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.spice ('sky130_fd_sc_lp__busreceiver_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:37:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__busreceiver_m sky130_fd_sc_lp__busreceiver_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__busreceiver_m
+SOURCE CELL NAME: sky130_fd_sc_lp__busreceiver_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pex.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pex.spice
index f14eed9..ee12526 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pex.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_m.pex.spice
-* Created: Fri Aug 28 10:14:15 2020
+* Created: Wed Sep 2 09:38:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pxi.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pxi.spice
index a2f98a6..a84c96e 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pxi.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_m.pxi.spice
-* Created: Fri Aug 28 10:14:15 2020
+* Created: Wed Sep 2 09:38:01 2020
*
x_PM_SKY130_FD_SC_LP__BUSRECEIVER_M%A_47_178# N_A_47_178#_M1002_d
+ N_A_47_178#_M1001_d N_A_47_178#_c_34_n N_A_47_178#_c_35_n N_A_47_178#_M1000_g
diff --git a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.spice b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.spice
index c99db98..b059088 100644
--- a/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.spice
+++ b/cells/busreceiver/sky130_fd_sc_lp__busreceiver_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__busreceiver_m.spice
-* Created: Fri Aug 28 10:14:15 2020
+* Created: Wed Sep 2 09:38:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.lvs.report
new file mode 100644
index 0000000..3bf27bc
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_0.sp ('sky130_fd_sc_lp__clkbuf_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.spice ('sky130_fd_sc_lp__clkbuf_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_0 sky130_fd_sc_lp__clkbuf_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_0
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pex.spice
index 38ed4bf..edca12d 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_0.pex.spice
-* Created: Fri Aug 28 10:14:30 2020
+* Created: Wed Sep 2 09:38:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pxi.spice
index 8c74a73..e1b6b69 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_0.pxi.spice
-* Created: Fri Aug 28 10:14:30 2020
+* Created: Wed Sep 2 09:38:07 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_0%A_70_157# N_A_70_157#_M1000_d N_A_70_157#_M1003_d
+ N_A_70_157#_M1002_g N_A_70_157#_M1001_g N_A_70_157#_c_42_n N_A_70_157#_c_43_n
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.spice
index 86f57eb..0522b8b 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_0.spice
-* Created: Fri Aug 28 10:14:30 2020
+* Created: Wed Sep 2 09:38:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.lvs.report
new file mode 100644
index 0000000..c1197e7
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_1.sp ('sky130_fd_sc_lp__clkbuf_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.spice ('sky130_fd_sc_lp__clkbuf_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_1 sky130_fd_sc_lp__clkbuf_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pex.spice
index 1f7ebb0..5b99dbc 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_1.pex.spice
-* Created: Fri Aug 28 10:14:48 2020
+* Created: Wed Sep 2 09:38:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pxi.spice
index cc190e3..c78cef4 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_1.pxi.spice
-* Created: Fri Aug 28 10:14:48 2020
+* Created: Wed Sep 2 09:38:20 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_1%A_69_161# N_A_69_161#_M1002_d N_A_69_161#_M1000_d
+ N_A_69_161#_M1001_g N_A_69_161#_M1003_g N_A_69_161#_c_35_n N_A_69_161#_c_36_n
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.spice
index 6170709..0fc5402 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_1.spice
-* Created: Fri Aug 28 10:14:48 2020
+* Created: Wed Sep 2 09:38:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.lvs.report
new file mode 100644
index 0000000..8cfa117
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_16.sp ('sky130_fd_sc_lp__clkbuf_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.spice ('sky130_fd_sc_lp__clkbuf_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_16 sky130_fd_sc_lp__clkbuf_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_16
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 4.
+ 36 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 4.
+ 36 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pex.spice
index 05eeb97..b08836f 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_16.pex.spice
-* Created: Fri Aug 28 10:14:40 2020
+* Created: Wed Sep 2 09:38:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pxi.spice
index 6dbd1f6..5fb0edd 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_16.pxi.spice
-* Created: Fri Aug 28 10:14:40 2020
+* Created: Wed Sep 2 09:38:14 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_16%A N_A_M1011_g N_A_M1004_g N_A_M1026_g
+ N_A_M1021_g N_A_M1029_g N_A_M1025_g N_A_M1030_g N_A_M1035_g A A A N_A_c_177_n
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.spice
index 1246c3d..d264713 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_16.spice
-* Created: Fri Aug 28 10:14:40 2020
+* Created: Wed Sep 2 09:38:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.lvs.report
new file mode 100644
index 0000000..796b93f
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_2.sp ('sky130_fd_sc_lp__clkbuf_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.spice ('sky130_fd_sc_lp__clkbuf_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_2 sky130_fd_sc_lp__clkbuf_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pex.spice
index 03c1d79..1c8997b 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_2.pex.spice
-* Created: Fri Aug 28 10:14:55 2020
+* Created: Wed Sep 2 09:38:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pxi.spice
index e06f05e..b978fd5 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_2.pxi.spice
-* Created: Fri Aug 28 10:14:55 2020
+* Created: Wed Sep 2 09:38:26 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_2%A N_A_M1002_g N_A_M1005_g A N_A_c_41_n N_A_c_42_n
+ PM_SKY130_FD_SC_LP__CLKBUF_2%A
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.spice
index c635c78..7b1c9b3 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_2.spice
-* Created: Fri Aug 28 10:14:55 2020
+* Created: Wed Sep 2 09:38:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.lvs.report
new file mode 100644
index 0000000..213bcf1
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_4.sp ('sky130_fd_sc_lp__clkbuf_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.spice ('sky130_fd_sc_lp__clkbuf_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_4 sky130_fd_sc_lp__clkbuf_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_4
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pex.spice
index d69d989..16a0bcc 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_4.pex.spice
-* Created: Fri Aug 28 10:15:02 2020
+* Created: Wed Sep 2 09:38:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pxi.spice
index 83c9574..78fd7ba 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_4.pxi.spice
-* Created: Fri Aug 28 10:15:02 2020
+* Created: Wed Sep 2 09:38:33 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_4%A N_A_M1004_g N_A_M1009_g A N_A_c_58_n N_A_c_59_n
+ PM_SKY130_FD_SC_LP__CLKBUF_4%A
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.spice
index 8c6481a..1f608de 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_4.spice
-* Created: Fri Aug 28 10:15:02 2020
+* Created: Wed Sep 2 09:38:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.lvs.report
new file mode 100644
index 0000000..7082214
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_8.sp ('sky130_fd_sc_lp__clkbuf_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.spice ('sky130_fd_sc_lp__clkbuf_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_8 sky130_fd_sc_lp__clkbuf_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_8
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 4.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pex.spice
index 12e30a5..393ba2b 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_8.pex.spice
-* Created: Fri Aug 28 10:15:09 2020
+* Created: Wed Sep 2 09:38:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pxi.spice
index 59363e9..a6979a9 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_8.pxi.spice
-* Created: Fri Aug 28 10:15:09 2020
+* Created: Wed Sep 2 09:38:39 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_8%A N_A_M1005_g N_A_M1006_g N_A_M1011_g N_A_M1018_g
+ A A N_A_c_103_n PM_SKY130_FD_SC_LP__CLKBUF_8%A
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.spice
index 139d4aa..1b6e7d4 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_8.spice
-* Created: Fri Aug 28 10:15:09 2020
+* Created: Wed Sep 2 09:38:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.lvs.report b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.lvs.report
new file mode 100644
index 0000000..bf19512
--- /dev/null
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuf_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuf_lp.sp ('sky130_fd_sc_lp__clkbuf_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.spice ('sky130_fd_sc_lp__clkbuf_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuf_lp sky130_fd_sc_lp__clkbuf_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuf_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuf_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pex.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pex.spice
index d715488..5c847cb 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pex.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_lp.pex.spice
-* Created: Fri Aug 28 10:15:16 2020
+* Created: Wed Sep 2 09:38:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pxi.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pxi.spice
index 5304618..eded30c 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pxi.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_lp.pxi.spice
-* Created: Fri Aug 28 10:15:16 2020
+* Created: Wed Sep 2 09:38:46 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUF_LP%A_94_31# N_A_94_31#_M1003_d N_A_94_31#_M1001_d
+ N_A_94_31#_M1000_g N_A_94_31#_c_35_n N_A_94_31#_M1004_g N_A_94_31#_M1005_g
diff --git a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.spice b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.spice
index 9764459..c4f4ca5 100644
--- a/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.spice
+++ b/cells/clkbuf/sky130_fd_sc_lp__clkbuf_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuf_lp.spice
-* Created: Fri Aug 28 10:15:16 2020
+* Created: Wed Sep 2 09:38:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.lvs.report b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.lvs.report
new file mode 100644
index 0000000..81985cb
--- /dev/null
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuflp_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuflp_16.sp ('sky130_fd_sc_lp__clkbuflp_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.spice ('sky130_fd_sc_lp__clkbuflp_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuflp_16 sky130_fd_sc_lp__clkbuflp_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuflp_16
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuflp_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 21 21
+
+ Instances: 28 28 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 51 50
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 50 layout mos transistors were reduced to 6. 12 connecting nets were deleted.
+ 20 mos transistors were deleted by parallel reduction.
+ 24 mos transistors and 12 connecting nets were deleted by split-gate reduction.
+ 50 source mos transistors were reduced to 6. 12 connecting nets were deleted.
+ 20 mos transistors were deleted by parallel reduction.
+ 24 mos transistors and 12 connecting nets were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pex.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pex.spice
index 0e9f213..22c9954 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pex.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_16.pex.spice
-* Created: Fri Aug 28 10:15:35 2020
+* Created: Wed Sep 2 09:38:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pxi.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pxi.spice
index 883cbdc..7430d6a 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pxi.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_16.pxi.spice
-* Created: Fri Aug 28 10:15:35 2020
+* Created: Wed Sep 2 09:38:53 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUFLP_16%A N_A_c_166_n N_A_M1018_g N_A_M1005_g
+ N_A_c_168_n N_A_M1002_g N_A_M1016_g N_A_c_170_n N_A_M1007_g N_A_M1025_g
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.spice
index bcae318..3a5ab60 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_16.spice
-* Created: Fri Aug 28 10:15:35 2020
+* Created: Wed Sep 2 09:38:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.lvs.report b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.lvs.report
new file mode 100644
index 0000000..800a53e
--- /dev/null
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuflp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuflp_2.sp ('sky130_fd_sc_lp__clkbuflp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.spice ('sky130_fd_sc_lp__clkbuflp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:38:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuflp_2 sky130_fd_sc_lp__clkbuflp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuflp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuflp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 6 layout mos transistors were reduced to 3. 1 connecting net was deleted.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+ 6 source mos transistors were reduced to 3. 1 connecting net was deleted.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pex.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pex.spice
index 22e1b21..b72dc3b 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pex.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_2.pex.spice
-* Created: Fri Aug 28 10:15:45 2020
+* Created: Wed Sep 2 09:39:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pxi.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pxi.spice
index a2c9f6d..5078ab4 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pxi.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_2.pxi.spice
-* Created: Fri Aug 28 10:15:45 2020
+* Created: Wed Sep 2 09:39:00 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUFLP_2%A N_A_c_41_n N_A_M1003_g N_A_M1001_g N_A_c_43_n
+ N_A_M1000_g A A N_A_c_45_n PM_SKY130_FD_SC_LP__CLKBUFLP_2%A
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.spice
index ec0b553..84d0e16 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_2.spice
-* Created: Fri Aug 28 10:15:45 2020
+* Created: Wed Sep 2 09:39:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.lvs.report b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.lvs.report
new file mode 100644
index 0000000..27ea2a8
--- /dev/null
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuflp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuflp_4.sp ('sky130_fd_sc_lp__clkbuflp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.spice ('sky130_fd_sc_lp__clkbuflp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuflp_4 sky130_fd_sc_lp__clkbuflp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuflp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuflp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 4. 1 connecting net was deleted.
+ 4 mos transistors were deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+ 10 source mos transistors were reduced to 4. 1 connecting net was deleted.
+ 4 mos transistors were deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pex.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pex.spice
index 523cbaa..59e4121 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pex.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_4.pex.spice
-* Created: Fri Aug 28 10:15:53 2020
+* Created: Wed Sep 2 09:39:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pxi.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pxi.spice
index 3f2ce3d..0ce8116 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pxi.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_4.pxi.spice
-* Created: Fri Aug 28 10:15:53 2020
+* Created: Wed Sep 2 09:39:07 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUFLP_4%A N_A_M1006_g N_A_M1005_g N_A_M1000_g
+ N_A_M1010_g A A N_A_c_65_n PM_SKY130_FD_SC_LP__CLKBUFLP_4%A
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.spice
index 5ac2a36..54f8021 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_4.spice
-* Created: Fri Aug 28 10:15:53 2020
+* Created: Wed Sep 2 09:39:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.lvs.report b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.lvs.report
new file mode 100644
index 0000000..752ae70
--- /dev/null
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkbuflp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkbuflp_8.sp ('sky130_fd_sc_lp__clkbuflp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.spice ('sky130_fd_sc_lp__clkbuflp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkbuflp_8 sky130_fd_sc_lp__clkbuflp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkbuflp_8
+SOURCE CELL NAME: sky130_fd_sc_lp__clkbuflp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6. 4 connecting nets were deleted.
+ 10 mos transistors were deleted by parallel reduction.
+ 8 mos transistors and 4 connecting nets were deleted by split-gate reduction.
+ 24 source mos transistors were reduced to 6. 4 connecting nets were deleted.
+ 10 mos transistors were deleted by parallel reduction.
+ 8 mos transistors and 4 connecting nets were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pex.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pex.spice
index 731583f..09d417c 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pex.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_8.pex.spice
-* Created: Fri Aug 28 10:16:00 2020
+* Created: Wed Sep 2 09:39:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pxi.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pxi.spice
index 0a38478..086af2d 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pxi.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_8.pxi.spice
-* Created: Fri Aug 28 10:16:00 2020
+* Created: Wed Sep 2 09:39:13 2020
*
x_PM_SKY130_FD_SC_LP__CLKBUFLP_8%A N_A_M1009_g N_A_M1007_g N_A_M1001_g
+ N_A_M1015_g N_A_M1017_g N_A_M1021_g N_A_M1011_g N_A_M1022_g A A N_A_c_101_n
diff --git a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.spice b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.spice
index 9e29ea0..fba9a7a 100644
--- a/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.spice
+++ b/cells/clkbuflp/sky130_fd_sc_lp__clkbuflp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkbuflp_8.spice
-* Created: Fri Aug 28 10:16:00 2020
+* Created: Wed Sep 2 09:39:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.lvs.report b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.lvs.report
new file mode 100644
index 0000000..6fa62d2
--- /dev/null
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s15_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s15_1.sp ('sky130_fd_sc_lp__clkdlybuf4s15_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.spice ('sky130_fd_sc_lp__clkdlybuf4s15_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s15_1 sky130_fd_sc_lp__clkdlybuf4s15_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s15_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s15_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pex.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pex.spice
index 4275311..0bd46ed 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pex.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_1.pex.spice
-* Created: Fri Aug 28 10:16:08 2020
+* Created: Wed Sep 2 09:39:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pxi.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pxi.spice
index b1c08a9..b3ae881 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pxi.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_1.pxi.spice
-* Created: Fri Aug 28 10:16:08 2020
+* Created: Wed Sep 2 09:39:20 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S15_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_64_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S15_1%A
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.spice
index ae5f4a9..c6270b1 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_1.spice
-* Created: Fri Aug 28 10:16:08 2020
+* Created: Wed Sep 2 09:39:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.lvs.report b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.lvs.report
new file mode 100644
index 0000000..dbf7529
--- /dev/null
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s15_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s15_2.sp ('sky130_fd_sc_lp__clkdlybuf4s15_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.spice ('sky130_fd_sc_lp__clkdlybuf4s15_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s15_2 sky130_fd_sc_lp__clkdlybuf4s15_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s15_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s15_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pex.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pex.spice
index 080aed3..b3d299a 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pex.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_2.pex.spice
-* Created: Fri Aug 28 10:16:16 2020
+* Created: Wed Sep 2 09:39:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pxi.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pxi.spice
index 39eb159..c62dd74 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pxi.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_2.pxi.spice
-* Created: Fri Aug 28 10:16:16 2020
+* Created: Wed Sep 2 09:39:27 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S15_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_69_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S15_2%A
diff --git a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.spice b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.spice
index 5e24231..a9a642b 100644
--- a/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.spice
+++ b/cells/clkdlybuf4s15/sky130_fd_sc_lp__clkdlybuf4s15_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s15_2.spice
-* Created: Fri Aug 28 10:16:16 2020
+* Created: Wed Sep 2 09:39:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.lvs.report b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.lvs.report
new file mode 100644
index 0000000..12dabaf
--- /dev/null
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s18_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s18_1.sp ('sky130_fd_sc_lp__clkdlybuf4s18_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.spice ('sky130_fd_sc_lp__clkdlybuf4s18_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s18_1 sky130_fd_sc_lp__clkdlybuf4s18_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s18_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s18_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pex.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pex.spice
index 4190923..5a1017a 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pex.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_1.pex.spice
-* Created: Fri Aug 28 10:16:31 2020
+* Created: Wed Sep 2 09:39:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pxi.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pxi.spice
index dc963c7..3afc87f 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pxi.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_1.pxi.spice
-* Created: Fri Aug 28 10:16:31 2020
+* Created: Wed Sep 2 09:39:33 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S18_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_62_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S18_1%A
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.spice
index 6c2c43a..3db7057 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_1.spice
-* Created: Fri Aug 28 10:16:31 2020
+* Created: Wed Sep 2 09:39:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.lvs.report b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.lvs.report
new file mode 100644
index 0000000..bbd5be5
--- /dev/null
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s18_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s18_2.sp ('sky130_fd_sc_lp__clkdlybuf4s18_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.spice ('sky130_fd_sc_lp__clkdlybuf4s18_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s18_2 sky130_fd_sc_lp__clkdlybuf4s18_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s18_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s18_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pex.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pex.spice
index 3baa746..61bbd96 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pex.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_2.pex.spice
-* Created: Fri Aug 28 10:16:40 2020
+* Created: Wed Sep 2 09:39:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pxi.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pxi.spice
index 78ba904..345d530 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pxi.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_2.pxi.spice
-* Created: Fri Aug 28 10:16:40 2020
+* Created: Wed Sep 2 09:39:40 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S18_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_67_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S18_2%A
diff --git a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.spice b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.spice
index 79eafe0..375b5bf 100644
--- a/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.spice
+++ b/cells/clkdlybuf4s18/sky130_fd_sc_lp__clkdlybuf4s18_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s18_2.spice
-* Created: Fri Aug 28 10:16:40 2020
+* Created: Wed Sep 2 09:39:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.lvs.report b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.lvs.report
new file mode 100644
index 0000000..0bf1a94
--- /dev/null
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s25_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s25_1.sp ('sky130_fd_sc_lp__clkdlybuf4s25_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.spice ('sky130_fd_sc_lp__clkdlybuf4s25_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s25_1 sky130_fd_sc_lp__clkdlybuf4s25_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s25_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s25_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pex.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pex.spice
index 1c6d102..45d211a 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pex.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_1.pex.spice
-* Created: Fri Aug 28 10:16:50 2020
+* Created: Wed Sep 2 09:39:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pxi.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pxi.spice
index f556529..f95403a 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pxi.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_1.pxi.spice
-* Created: Fri Aug 28 10:16:50 2020
+* Created: Wed Sep 2 09:39:46 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S25_1%A N_A_M1003_g N_A_M1007_g A A N_A_c_62_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S25_1%A
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.spice
index 37d98c4..a271b04 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_1.spice
-* Created: Fri Aug 28 10:16:50 2020
+* Created: Wed Sep 2 09:39:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.lvs.report b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.lvs.report
new file mode 100644
index 0000000..99a6f2d
--- /dev/null
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s25_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s25_2.sp ('sky130_fd_sc_lp__clkdlybuf4s25_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.spice ('sky130_fd_sc_lp__clkdlybuf4s25_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s25_2 sky130_fd_sc_lp__clkdlybuf4s25_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s25_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s25_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pex.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pex.spice
index 98a2a38..8972d55 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pex.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_2.pex.spice
-* Created: Fri Aug 28 10:16:58 2020
+* Created: Wed Sep 2 09:39:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pxi.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pxi.spice
index 3605e95..34018d0 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pxi.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_2.pxi.spice
-* Created: Fri Aug 28 10:16:58 2020
+* Created: Wed Sep 2 09:39:53 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S25_2%A N_A_M1004_g N_A_M1009_g A A N_A_c_67_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S25_2%A
diff --git a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.spice b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.spice
index 60f7f94..759e7f0 100644
--- a/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.spice
+++ b/cells/clkdlybuf4s25/sky130_fd_sc_lp__clkdlybuf4s25_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s25_2.spice
-* Created: Fri Aug 28 10:16:58 2020
+* Created: Wed Sep 2 09:39:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.lvs.report b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.lvs.report
new file mode 100644
index 0000000..1bc35f1
--- /dev/null
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s50_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s50_1.sp ('sky130_fd_sc_lp__clkdlybuf4s50_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.spice ('sky130_fd_sc_lp__clkdlybuf4s50_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:39:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s50_1 sky130_fd_sc_lp__clkdlybuf4s50_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s50_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s50_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pex.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pex.spice
index 14a6065..bf0a487 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pex.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_1.pex.spice
-* Created: Fri Aug 28 10:17:05 2020
+* Created: Wed Sep 2 09:39:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pxi.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pxi.spice
index a98f05e..57ac9b6 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pxi.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_1.pxi.spice
-* Created: Fri Aug 28 10:17:05 2020
+* Created: Wed Sep 2 09:39:59 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S50_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_61_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S50_1%A
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.spice
index 3472c6c..73c6c65 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_1.spice
-* Created: Fri Aug 28 10:17:05 2020
+* Created: Wed Sep 2 09:39:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.lvs.report b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.lvs.report
new file mode 100644
index 0000000..6f05687
--- /dev/null
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkdlybuf4s50_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkdlybuf4s50_2.sp ('sky130_fd_sc_lp__clkdlybuf4s50_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.spice ('sky130_fd_sc_lp__clkdlybuf4s50_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkdlybuf4s50_2 sky130_fd_sc_lp__clkdlybuf4s50_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkdlybuf4s50_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkdlybuf4s50_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pex.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pex.spice
index 374e71c..7737eb6 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pex.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_2.pex.spice
-* Created: Fri Aug 28 10:17:13 2020
+* Created: Wed Sep 2 09:40:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pxi.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pxi.spice
index fab3962..d81811b 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pxi.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_2.pxi.spice
-* Created: Fri Aug 28 10:17:13 2020
+* Created: Wed Sep 2 09:40:06 2020
*
x_PM_SKY130_FD_SC_LP__CLKDLYBUF4S50_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_66_n
+ PM_SKY130_FD_SC_LP__CLKDLYBUF4S50_2%A
diff --git a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.spice b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.spice
index de1a4f0..a26a815 100644
--- a/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.spice
+++ b/cells/clkdlybuf4s50/sky130_fd_sc_lp__clkdlybuf4s50_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkdlybuf4s50_2.spice
-* Created: Fri Aug 28 10:17:13 2020
+* Created: Wed Sep 2 09:40:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.lvs.report
new file mode 100644
index 0000000..2c0a263
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_0.sp ('sky130_fd_sc_lp__clkinv_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_0.spice ('sky130_fd_sc_lp__clkinv_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_0 sky130_fd_sc_lp__clkinv_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_0
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pex.spice
index 6702823..4452b64 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_0.pex.spice
-* Created: Fri Aug 28 10:17:21 2020
+* Created: Wed Sep 2 09:40:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pxi.spice
index 5a2e3da..f6f0cc1 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_0.pxi.spice
-* Created: Fri Aug 28 10:17:21 2020
+* Created: Wed Sep 2 09:40:13 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_0%A N_A_M1000_g N_A_M1001_g A A A A N_A_c_22_n
+ PM_SKY130_FD_SC_LP__CLKINV_0%A
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.spice
index 9fcbfdb..3eaea89 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_0.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_0.spice
-* Created: Fri Aug 28 10:17:21 2020
+* Created: Wed Sep 2 09:40:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.lvs.report
new file mode 100644
index 0000000..94dbbbb
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_1.sp ('sky130_fd_sc_lp__clkinv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_1.spice ('sky130_fd_sc_lp__clkinv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_1 sky130_fd_sc_lp__clkinv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_1
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pex.spice
index 320aafb..ee40d2e 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_1.pex.spice
-* Created: Fri Aug 28 10:17:44 2020
+* Created: Wed Sep 2 09:40:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pxi.spice
index fd07154..6641643 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_1.pxi.spice
-* Created: Fri Aug 28 10:17:44 2020
+* Created: Wed Sep 2 09:40:26 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_1%A N_A_M1000_g N_A_M1001_g N_A_c_27_n N_A_M1002_g
+ A A A PM_SKY130_FD_SC_LP__CLKINV_1%A
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.spice
index 3de74b1..5583cd3 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_1.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_1.spice
-* Created: Fri Aug 28 10:17:44 2020
+* Created: Wed Sep 2 09:40:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.lvs.report
new file mode 100644
index 0000000..3f912bc
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_16.sp ('sky130_fd_sc_lp__clkinv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_16.spice ('sky130_fd_sc_lp__clkinv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_16 sky130_fd_sc_lp__clkinv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_16
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 16 16 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 2.
+ 38 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 2.
+ 38 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pex.spice
index 9f3007e..e5c000e 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_16.pex.spice
-* Created: Fri Aug 28 10:17:35 2020
+* Created: Wed Sep 2 09:40:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pxi.spice
index 1665e9f..a6929a8 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_16.pxi.spice
-* Created: Fri Aug 28 10:17:35 2020
+* Created: Wed Sep 2 09:40:19 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_16%A N_A_M1000_g N_A_M1001_g N_A_M1002_g
+ N_A_M1003_g N_A_M1006_g N_A_M1004_g N_A_M1007_g N_A_M1005_g N_A_M1008_g
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.spice
index 698ae3c..fcbb3d9 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_16.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_16.spice
-* Created: Fri Aug 28 10:17:35 2020
+* Created: Wed Sep 2 09:40:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.lvs.report
new file mode 100644
index 0000000..5999063
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_2.sp ('sky130_fd_sc_lp__clkinv_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_2.spice ('sky130_fd_sc_lp__clkinv_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_2 sky130_fd_sc_lp__clkinv_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 6 5
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 5 layout mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+ 5 source mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pex.spice
index 0a2b446..cf90850 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_2.pex.spice
-* Created: Fri Aug 28 10:17:54 2020
+* Created: Wed Sep 2 09:40:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pxi.spice
index 55f4737..3870f24 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_2.pxi.spice
-* Created: Fri Aug 28 10:17:54 2020
+* Created: Wed Sep 2 09:40:32 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_2%A N_A_M1001_g N_A_M1002_g N_A_M1000_g N_A_M1004_g
+ N_A_M1003_g A A N_A_c_36_n N_A_c_37_n PM_SKY130_FD_SC_LP__CLKINV_2%A
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.spice
index ca7f024..8be9c61 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_2.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_2.spice
-* Created: Fri Aug 28 10:17:54 2020
+* Created: Wed Sep 2 09:40:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.lvs.report
new file mode 100644
index 0000000..df26853
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_4.sp ('sky130_fd_sc_lp__clkinv_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_4.spice ('sky130_fd_sc_lp__clkinv_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_4 sky130_fd_sc_lp__clkinv_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_4
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pex.spice
index 42e4a94..7e4747b 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_4.pex.spice
-* Created: Fri Aug 28 10:18:01 2020
+* Created: Wed Sep 2 09:40:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pxi.spice
index 9a4f05d..bda3be7 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_4.pxi.spice
-* Created: Fri Aug 28 10:18:01 2020
+* Created: Wed Sep 2 09:40:39 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_4%A N_A_M1001_g N_A_M1000_g N_A_M1002_g N_A_M1004_g
+ N_A_M1003_g N_A_M1007_g N_A_M1005_g N_A_M1008_g N_A_M1006_g N_A_M1009_g A A A
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.spice
index 290f966..6099ca9 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_4.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_4.spice
-* Created: Fri Aug 28 10:18:01 2020
+* Created: Wed Sep 2 09:40:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.lvs.report
new file mode 100644
index 0000000..faeef89
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_8.sp ('sky130_fd_sc_lp__clkinv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_8.spice ('sky130_fd_sc_lp__clkinv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_8 sky130_fd_sc_lp__clkinv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_8
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pex.spice
index b02924a..8db817e 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_8.pex.spice
-* Created: Fri Aug 28 10:18:09 2020
+* Created: Wed Sep 2 09:40:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pxi.spice
index b207999..64ba240 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_8.pxi.spice
-* Created: Fri Aug 28 10:18:09 2020
+* Created: Wed Sep 2 09:40:45 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_8%A N_A_M1000_g N_A_M1003_g N_A_M1001_g N_A_M1005_g
+ N_A_M1002_g N_A_M1007_g N_A_M1004_g N_A_M1008_g N_A_M1006_g N_A_M1010_g
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.spice
index aa446bd..cc5a3b9 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_8.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_8.spice
-* Created: Fri Aug 28 10:18:09 2020
+* Created: Wed Sep 2 09:40:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.lvs.report
new file mode 100644
index 0000000..70f356e
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_lp.sp ('sky130_fd_sc_lp__clkinv_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.spice ('sky130_fd_sc_lp__clkinv_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_lp sky130_fd_sc_lp__clkinv_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pex.spice
index 561041b..06945d0 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp.pex.spice
-* Created: Fri Aug 28 10:18:25 2020
+* Created: Wed Sep 2 09:40:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pxi.spice
index f44d938..bf136c7 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp.pxi.spice
-* Created: Fri Aug 28 10:18:25 2020
+* Created: Wed Sep 2 09:40:58 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_LP%A N_A_M1000_g N_A_M1001_g N_A_c_29_n N_A_M1002_g
+ N_A_M1003_g N_A_c_32_n N_A_c_38_n N_A_c_33_n A A A N_A_c_35_n
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.spice
index e48ad35..10193a0 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp.spice
-* Created: Fri Aug 28 10:18:25 2020
+* Created: Wed Sep 2 09:40:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.lvs.report b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.lvs.report
new file mode 100644
index 0000000..a7b2ce6
--- /dev/null
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinv_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinv_lp2.sp ('sky130_fd_sc_lp__clkinv_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.spice ('sky130_fd_sc_lp__clkinv_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:40:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinv_lp2 sky130_fd_sc_lp__clkinv_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinv_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinv_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pex.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pex.spice
index b9c2867..d450a9f 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pex.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp2.pex.spice
-* Created: Fri Aug 28 10:18:17 2020
+* Created: Wed Sep 2 09:40:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pxi.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pxi.spice
index ad624fd..3ca4a8b 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pxi.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp2.pxi.spice
-* Created: Fri Aug 28 10:18:17 2020
+* Created: Wed Sep 2 09:40:51 2020
*
x_PM_SKY130_FD_SC_LP__CLKINV_LP2%A N_A_M1000_g N_A_M1001_g N_A_M1002_g A A
+ N_A_c_27_n PM_SKY130_FD_SC_LP__CLKINV_LP2%A
diff --git a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.spice b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.spice
index 9461e2a..91310f3 100644
--- a/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.spice
+++ b/cells/clkinv/sky130_fd_sc_lp__clkinv_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinv_lp2.spice
-* Created: Fri Aug 28 10:18:17 2020
+* Created: Wed Sep 2 09:40:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.lvs.report b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.lvs.report
new file mode 100644
index 0000000..c32e687
--- /dev/null
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinvlp_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinvlp_16.sp ('sky130_fd_sc_lp__clkinvlp_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.spice ('sky130_fd_sc_lp__clkinvlp_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinvlp_16 sky130_fd_sc_lp__clkinvlp_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinvlp_16
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinvlp_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 16 16
+
+ Instances: 20 20 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 3. 9 connecting nets were deleted.
+ 15 mos transistors were deleted by parallel reduction.
+ 18 mos transistors and 9 connecting nets were deleted by split-gate reduction.
+ 36 source mos transistors were reduced to 3. 9 connecting nets were deleted.
+ 15 mos transistors were deleted by parallel reduction.
+ 18 mos transistors and 9 connecting nets were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pex.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pex.spice
index c008c57..6a86743 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pex.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_16.pex.spice
-* Created: Fri Aug 28 10:18:39 2020
+* Created: Wed Sep 2 09:41:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pxi.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pxi.spice
index 05946d5..33d14d8 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pxi.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_16.pxi.spice
-* Created: Fri Aug 28 10:18:39 2020
+* Created: Wed Sep 2 09:41:05 2020
*
x_PM_SKY130_FD_SC_LP__CLKINVLP_16%A N_A_M1025_g N_A_M1000_g N_A_M1001_g
+ N_A_M1002_g N_A_M1005_g N_A_M1003_g N_A_M1004_g N_A_M1010_g N_A_M1007_g
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.spice
index f229d21..cc6cdb0 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_16.spice
-* Created: Fri Aug 28 10:18:39 2020
+* Created: Wed Sep 2 09:41:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.lvs.report b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.lvs.report
new file mode 100644
index 0000000..8a2a002
--- /dev/null
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinvlp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinvlp_2.sp ('sky130_fd_sc_lp__clkinvlp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.spice ('sky130_fd_sc_lp__clkinvlp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinvlp_2 sky130_fd_sc_lp__clkinvlp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinvlp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinvlp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pex.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pex.spice
index 5a61aef..ba961fe 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pex.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_2.pex.spice
-* Created: Fri Aug 28 10:18:48 2020
+* Created: Wed Sep 2 09:41:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pxi.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pxi.spice
index d831747..e8b6f84 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pxi.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_2.pxi.spice
-* Created: Fri Aug 28 10:18:48 2020
+* Created: Wed Sep 2 09:41:12 2020
*
x_PM_SKY130_FD_SC_LP__CLKINVLP_2%A N_A_M1000_g N_A_c_27_n N_A_M1001_g N_A_c_28_n
+ N_A_M1002_g N_A_M1003_g A A N_A_c_30_n PM_SKY130_FD_SC_LP__CLKINVLP_2%A
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.spice
index bc3c936..72ca97e 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_2.spice
-* Created: Fri Aug 28 10:18:48 2020
+* Created: Wed Sep 2 09:41:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.lvs.report b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.lvs.report
new file mode 100644
index 0000000..95cec24
--- /dev/null
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinvlp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinvlp_4.sp ('sky130_fd_sc_lp__clkinvlp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.spice ('sky130_fd_sc_lp__clkinvlp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinvlp_4 sky130_fd_sc_lp__clkinvlp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinvlp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinvlp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 3. 1 connecting net was deleted.
+ 3 mos transistors were deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+ 8 source mos transistors were reduced to 3. 1 connecting net was deleted.
+ 3 mos transistors were deleted by parallel reduction.
+ 2 mos transistors and 1 connecting net were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pex.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pex.spice
index 13a0fcd..43affbf 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pex.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_4.pex.spice
-* Created: Fri Aug 28 10:18:58 2020
+* Created: Wed Sep 2 09:41:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pxi.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pxi.spice
index 2803733..6ddb525 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pxi.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_4.pxi.spice
-* Created: Fri Aug 28 10:18:58 2020
+* Created: Wed Sep 2 09:41:19 2020
*
x_PM_SKY130_FD_SC_LP__CLKINVLP_4%A N_A_M1007_g N_A_M1000_g N_A_M1001_g
+ N_A_M1002_g N_A_M1003_g N_A_M1004_g N_A_M1006_g N_A_M1005_g A A N_A_c_48_n
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.spice
index 3b0038d..a75ef75 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_4.spice
-* Created: Fri Aug 28 10:18:58 2020
+* Created: Wed Sep 2 09:41:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.lvs.report b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.lvs.report
new file mode 100644
index 0000000..526c383
--- /dev/null
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__clkinvlp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__clkinvlp_8.sp ('sky130_fd_sc_lp__clkinvlp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.spice ('sky130_fd_sc_lp__clkinvlp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__clkinvlp_8 sky130_fd_sc_lp__clkinvlp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__clkinvlp_8
+SOURCE CELL NAME: sky130_fd_sc_lp__clkinvlp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 10 10
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 3. 3 connecting nets were deleted.
+ 7 mos transistors were deleted by parallel reduction.
+ 6 mos transistors and 3 connecting nets were deleted by split-gate reduction.
+ 16 source mos transistors were reduced to 3. 3 connecting nets were deleted.
+ 7 mos transistors were deleted by parallel reduction.
+ 6 mos transistors and 3 connecting nets were deleted by split-gate reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pex.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pex.spice
index c7ee686..fd8e032 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pex.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_8.pex.spice
-* Created: Fri Aug 28 10:19:06 2020
+* Created: Wed Sep 2 09:41:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pxi.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pxi.spice
index 2109bd8..29379b9 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pxi.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_8.pxi.spice
-* Created: Fri Aug 28 10:19:06 2020
+* Created: Wed Sep 2 09:41:26 2020
*
x_PM_SKY130_FD_SC_LP__CLKINVLP_8%A N_A_M1014_g N_A_M1000_g N_A_M1001_g
+ N_A_M1002_g N_A_M1004_g N_A_M1005_g N_A_M1003_g N_A_M1013_g N_A_M1006_g
diff --git a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.spice b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.spice
index bcb3541..305e473 100644
--- a/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.spice
+++ b/cells/clkinvlp/sky130_fd_sc_lp__clkinvlp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__clkinvlp_8.spice
-* Created: Fri Aug 28 10:19:06 2020
+* Created: Wed Sep 2 09:41:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/conb/sky130_fd_sc_lp__conb_0.lvs.report b/cells/conb/sky130_fd_sc_lp__conb_0.lvs.report
new file mode 100644
index 0000000..05b73c3
--- /dev/null
+++ b/cells/conb/sky130_fd_sc_lp__conb_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__conb_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__conb_0.sp ('sky130_fd_sc_lp__conb_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/conb/sky130_fd_sc_lp__conb_0.spice ('sky130_fd_sc_lp__conb_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__conb_0 sky130_fd_sc_lp__conb_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__conb_0
+SOURCE CELL NAME: sky130_fd_sc_lp__conb_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB HI LO VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/conb/sky130_fd_sc_lp__conb_0.pex.spice b/cells/conb/sky130_fd_sc_lp__conb_0.pex.spice
index 1388e5c..68cc42d 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_0.pex.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_0.pex.spice
-* Created: Fri Aug 28 10:19:14 2020
+* Created: Wed Sep 2 09:41:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/conb/sky130_fd_sc_lp__conb_0.pxi.spice b/cells/conb/sky130_fd_sc_lp__conb_0.pxi.spice
index 837d3ba..b1d5b8f 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_0.pxi.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_0.pxi.spice
-* Created: Fri Aug 28 10:19:14 2020
+* Created: Wed Sep 2 09:41:33 2020
*
x_PM_SKY130_FD_SC_LP__CONB_0%HI N_HI_M1002_d N_HI_M1001_g N_HI_M1002_g
+ N_HI_c_37_n N_HI_c_42_n HI HI HI N_HI_c_39_n N_HI_c_45_n
diff --git a/cells/conb/sky130_fd_sc_lp__conb_0.spice b/cells/conb/sky130_fd_sc_lp__conb_0.spice
index 96de7a5..1052855 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_0.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_0.spice
-* Created: Fri Aug 28 10:19:14 2020
+* Created: Wed Sep 2 09:41:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/conb/sky130_fd_sc_lp__conb_1.lvs.report b/cells/conb/sky130_fd_sc_lp__conb_1.lvs.report
new file mode 100644
index 0000000..c5a4d15
--- /dev/null
+++ b/cells/conb/sky130_fd_sc_lp__conb_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__conb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__conb_1.sp ('sky130_fd_sc_lp__conb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/conb/sky130_fd_sc_lp__conb_1.spice ('sky130_fd_sc_lp__conb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__conb_1 sky130_fd_sc_lp__conb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__conb_1
+SOURCE CELL NAME: sky130_fd_sc_lp__conb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB HI LO VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/conb/sky130_fd_sc_lp__conb_1.pex.spice b/cells/conb/sky130_fd_sc_lp__conb_1.pex.spice
index 853ca96..35a4560 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_1.pex.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_1.pex.spice
-* Created: Fri Aug 28 10:19:22 2020
+* Created: Wed Sep 2 09:41:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/conb/sky130_fd_sc_lp__conb_1.pxi.spice b/cells/conb/sky130_fd_sc_lp__conb_1.pxi.spice
index 5b209da..d822450 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_1.pxi.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_1.pxi.spice
-* Created: Fri Aug 28 10:19:22 2020
+* Created: Wed Sep 2 09:41:39 2020
*
x_PM_SKY130_FD_SC_LP__CONB_1%HI N_HI_M1002_d N_HI_M1001_g N_HI_M1002_g
+ N_HI_c_37_n N_HI_c_42_n HI HI HI N_HI_c_39_n N_HI_c_45_n
diff --git a/cells/conb/sky130_fd_sc_lp__conb_1.spice b/cells/conb/sky130_fd_sc_lp__conb_1.spice
index ae4c3d1..6e12f4b 100644
--- a/cells/conb/sky130_fd_sc_lp__conb_1.spice
+++ b/cells/conb/sky130_fd_sc_lp__conb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__conb_1.spice
-* Created: Fri Aug 28 10:19:22 2020
+* Created: Wed Sep 2 09:41:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_lp__decap_12.lvs.report b/cells/decap/sky130_fd_sc_lp__decap_12.lvs.report
new file mode 100644
index 0000000..0642a06
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_lp__decap_12.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decap_12.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decap_12.sp ('sky130_fd_sc_lp__decap_12')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decap/sky130_fd_sc_lp__decap_12.spice ('sky130_fd_sc_lp__decap_12')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decap_12 sky130_fd_sc_lp__decap_12
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decap_12
+SOURCE CELL NAME: sky130_fd_sc_lp__decap_12
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_lp__decap_12.pex.spice b/cells/decap/sky130_fd_sc_lp__decap_12.pex.spice
index 8b736df..0e98006 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_12.pex.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_12.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_12.pex.spice
-* Created: Fri Aug 28 10:19:30 2020
+* Created: Wed Sep 2 09:41:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_lp__decap_12.pxi.spice b/cells/decap/sky130_fd_sc_lp__decap_12.pxi.spice
index 0b1012d..ecf5399 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_12.pxi.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_12.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_12.pxi.spice
-* Created: Fri Aug 28 10:19:30 2020
+* Created: Wed Sep 2 09:41:46 2020
*
x_PM_SKY130_FD_SC_LP__DECAP_12%VGND N_VGND_M1000_s N_VGND_c_28_n N_VGND_M1001_g
+ N_VGND_c_29_n N_VGND_c_30_n N_VGND_c_31_n N_VGND_c_32_n VGND N_VGND_c_33_n
diff --git a/cells/decap/sky130_fd_sc_lp__decap_12.spice b/cells/decap/sky130_fd_sc_lp__decap_12.spice
index 0eb7901..e97493e 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_12.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_12.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_12.spice
-* Created: Fri Aug 28 10:19:30 2020
+* Created: Wed Sep 2 09:41:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_lp__decap_3.lvs.report b/cells/decap/sky130_fd_sc_lp__decap_3.lvs.report
new file mode 100644
index 0000000..eaf6205
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_lp__decap_3.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decap_3.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decap_3.sp ('sky130_fd_sc_lp__decap_3')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decap/sky130_fd_sc_lp__decap_3.spice ('sky130_fd_sc_lp__decap_3')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decap_3 sky130_fd_sc_lp__decap_3
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decap_3
+SOURCE CELL NAME: sky130_fd_sc_lp__decap_3
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_lp__decap_3.pex.spice b/cells/decap/sky130_fd_sc_lp__decap_3.pex.spice
index 535ae85..8fb5973 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_3.pex.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_3.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_3.pex.spice
-* Created: Fri Aug 28 10:19:45 2020
+* Created: Wed Sep 2 09:41:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_lp__decap_3.pxi.spice b/cells/decap/sky130_fd_sc_lp__decap_3.pxi.spice
index 2396410..841f305 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_3.pxi.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_3.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_3.pxi.spice
-* Created: Fri Aug 28 10:19:45 2020
+* Created: Wed Sep 2 09:41:53 2020
*
x_PM_SKY130_FD_SC_LP__DECAP_3%VGND N_VGND_M1001_s N_VGND_c_21_n N_VGND_M1000_g
+ N_VGND_c_22_n N_VGND_c_23_n N_VGND_c_24_n N_VGND_c_25_n N_VGND_c_26_n VGND
diff --git a/cells/decap/sky130_fd_sc_lp__decap_3.spice b/cells/decap/sky130_fd_sc_lp__decap_3.spice
index 8b00f0b..98086d9 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_3.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_3.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_3.spice
-* Created: Fri Aug 28 10:19:45 2020
+* Created: Wed Sep 2 09:41:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_lp__decap_4.lvs.report b/cells/decap/sky130_fd_sc_lp__decap_4.lvs.report
new file mode 100644
index 0000000..1748feb
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_lp__decap_4.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decap_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decap_4.sp ('sky130_fd_sc_lp__decap_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decap/sky130_fd_sc_lp__decap_4.spice ('sky130_fd_sc_lp__decap_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:41:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decap_4 sky130_fd_sc_lp__decap_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decap_4
+SOURCE CELL NAME: sky130_fd_sc_lp__decap_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_lp__decap_4.pex.spice b/cells/decap/sky130_fd_sc_lp__decap_4.pex.spice
index 23e48d2..2a33f2a 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_4.pex.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_4.pex.spice
-* Created: Fri Aug 28 10:19:54 2020
+* Created: Wed Sep 2 09:42:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_lp__decap_4.pxi.spice b/cells/decap/sky130_fd_sc_lp__decap_4.pxi.spice
index 556e602..7080e67 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_4.pxi.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_4.pxi.spice
-* Created: Fri Aug 28 10:19:54 2020
+* Created: Wed Sep 2 09:42:00 2020
*
x_PM_SKY130_FD_SC_LP__DECAP_4%VGND N_VGND_M1001_s N_VGND_c_23_n N_VGND_M1000_g
+ N_VGND_c_24_n N_VGND_c_25_n N_VGND_c_26_n N_VGND_c_27_n N_VGND_c_28_n VGND
diff --git a/cells/decap/sky130_fd_sc_lp__decap_4.spice b/cells/decap/sky130_fd_sc_lp__decap_4.spice
index d4fcda6..313d957 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_4.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_4.spice
-* Created: Fri Aug 28 10:19:54 2020
+* Created: Wed Sep 2 09:42:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_lp__decap_6.lvs.report b/cells/decap/sky130_fd_sc_lp__decap_6.lvs.report
new file mode 100644
index 0000000..39a1d74
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_lp__decap_6.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decap_6.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decap_6.sp ('sky130_fd_sc_lp__decap_6')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decap/sky130_fd_sc_lp__decap_6.spice ('sky130_fd_sc_lp__decap_6')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decap_6 sky130_fd_sc_lp__decap_6
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decap_6
+SOURCE CELL NAME: sky130_fd_sc_lp__decap_6
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_lp__decap_6.pex.spice b/cells/decap/sky130_fd_sc_lp__decap_6.pex.spice
index e434843..c67d5ec 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_6.pex.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_6.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_6.pex.spice
-* Created: Fri Aug 28 10:20:04 2020
+* Created: Wed Sep 2 09:42:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_lp__decap_6.pxi.spice b/cells/decap/sky130_fd_sc_lp__decap_6.pxi.spice
index c747596..b64eca6 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_6.pxi.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_6.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_6.pxi.spice
-* Created: Fri Aug 28 10:20:04 2020
+* Created: Wed Sep 2 09:42:06 2020
*
x_PM_SKY130_FD_SC_LP__DECAP_6%VGND N_VGND_M1001_s N_VGND_c_24_n N_VGND_c_25_n
+ N_VGND_c_26_n N_VGND_c_27_n N_VGND_c_28_n N_VGND_c_29_n N_VGND_c_30_n VGND
diff --git a/cells/decap/sky130_fd_sc_lp__decap_6.spice b/cells/decap/sky130_fd_sc_lp__decap_6.spice
index 2a795c0..5ae454f 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_6.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_6.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_6.spice
-* Created: Fri Aug 28 10:20:04 2020
+* Created: Wed Sep 2 09:42:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decap/sky130_fd_sc_lp__decap_8.lvs.report b/cells/decap/sky130_fd_sc_lp__decap_8.lvs.report
new file mode 100644
index 0000000..6201723
--- /dev/null
+++ b/cells/decap/sky130_fd_sc_lp__decap_8.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decap_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decap_8.sp ('sky130_fd_sc_lp__decap_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decap/sky130_fd_sc_lp__decap_8.spice ('sky130_fd_sc_lp__decap_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decap_8 sky130_fd_sc_lp__decap_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decap_8
+SOURCE CELL NAME: sky130_fd_sc_lp__decap_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decap/sky130_fd_sc_lp__decap_8.pex.spice b/cells/decap/sky130_fd_sc_lp__decap_8.pex.spice
index 43801de..64f6542 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_8.pex.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_8.pex.spice
-* Created: Fri Aug 28 10:20:12 2020
+* Created: Wed Sep 2 09:42:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decap/sky130_fd_sc_lp__decap_8.pxi.spice b/cells/decap/sky130_fd_sc_lp__decap_8.pxi.spice
index 349ddea..a1019ff 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_8.pxi.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_8.pxi.spice
-* Created: Fri Aug 28 10:20:12 2020
+* Created: Wed Sep 2 09:42:13 2020
*
x_PM_SKY130_FD_SC_LP__DECAP_8%VGND N_VGND_M1000_s N_VGND_c_27_n N_VGND_c_28_n
+ N_VGND_c_29_n N_VGND_c_30_n N_VGND_c_31_n VGND N_VGND_M1001_g N_VGND_c_32_n
diff --git a/cells/decap/sky130_fd_sc_lp__decap_8.spice b/cells/decap/sky130_fd_sc_lp__decap_8.spice
index 23d886f..e6306b9 100644
--- a/cells/decap/sky130_fd_sc_lp__decap_8.spice
+++ b/cells/decap/sky130_fd_sc_lp__decap_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decap_8.spice
-* Created: Fri Aug 28 10:20:12 2020
+* Created: Wed Sep 2 09:42:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.lvs.report b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.lvs.report
new file mode 100644
index 0000000..0e2785f
--- /dev/null
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decapkapwr_12.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decapkapwr_12.sp ('sky130_fd_sc_lp__decapkapwr_12')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.spice ('sky130_fd_sc_lp__decapkapwr_12')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decapkapwr_12 sky130_fd_sc_lp__decapkapwr_12
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decapkapwr_12
+SOURCE CELL NAME: sky130_fd_sc_lp__decapkapwr_12
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND KAPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pex.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pex.spice
index 406f12a..430f31d 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pex.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_12.pex.spice
-* Created: Fri Aug 28 10:20:20 2020
+* Created: Wed Sep 2 09:42:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pxi.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pxi.spice
index 17de296..5345c4d 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pxi.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_12.pxi.spice
-* Created: Fri Aug 28 10:20:20 2020
+* Created: Wed Sep 2 09:42:20 2020
*
x_PM_SKY130_FD_SC_LP__DECAPKAPWR_12%VGND N_VGND_M1000_s N_VGND_c_27_n
+ N_VGND_M1001_g N_VGND_c_28_n N_VGND_c_29_n N_VGND_c_30_n N_VGND_c_31_n VGND
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.spice
index b2b6023..71be5ad 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_12.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_12.spice
-* Created: Fri Aug 28 10:20:20 2020
+* Created: Wed Sep 2 09:42:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.lvs.report b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.lvs.report
new file mode 100644
index 0000000..7a576ff
--- /dev/null
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decapkapwr_3.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decapkapwr_3.sp ('sky130_fd_sc_lp__decapkapwr_3')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.spice ('sky130_fd_sc_lp__decapkapwr_3')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decapkapwr_3 sky130_fd_sc_lp__decapkapwr_3
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decapkapwr_3
+SOURCE CELL NAME: sky130_fd_sc_lp__decapkapwr_3
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND KAPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pex.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pex.spice
index 280bcf7..4d61838 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pex.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_3.pex.spice
-* Created: Fri Aug 28 10:20:27 2020
+* Created: Wed Sep 2 09:42:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pxi.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pxi.spice
index de9ce65..e5b652c 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pxi.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_3.pxi.spice
-* Created: Fri Aug 28 10:20:27 2020
+* Created: Wed Sep 2 09:42:27 2020
*
x_PM_SKY130_FD_SC_LP__DECAPKAPWR_3%VGND N_VGND_M1001_s N_VGND_c_22_n
+ N_VGND_M1000_g N_VGND_c_23_n N_VGND_c_24_n N_VGND_c_25_n N_VGND_c_26_n
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.spice
index 6bb46e8..024bd7c 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_3.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_3.spice
-* Created: Fri Aug 28 10:20:27 2020
+* Created: Wed Sep 2 09:42:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.lvs.report b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.lvs.report
new file mode 100644
index 0000000..13a0074
--- /dev/null
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decapkapwr_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decapkapwr_4.sp ('sky130_fd_sc_lp__decapkapwr_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.spice ('sky130_fd_sc_lp__decapkapwr_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decapkapwr_4 sky130_fd_sc_lp__decapkapwr_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decapkapwr_4
+SOURCE CELL NAME: sky130_fd_sc_lp__decapkapwr_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND KAPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pex.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pex.spice
index c478ced..4015a9b 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pex.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_4.pex.spice
-* Created: Fri Aug 28 10:20:36 2020
+* Created: Wed Sep 2 09:42:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pxi.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pxi.spice
index 3520700..2a4b3a4 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pxi.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_4.pxi.spice
-* Created: Fri Aug 28 10:20:36 2020
+* Created: Wed Sep 2 09:42:33 2020
*
x_PM_SKY130_FD_SC_LP__DECAPKAPWR_4%VGND N_VGND_M1001_s N_VGND_c_24_n
+ N_VGND_M1000_g N_VGND_c_25_n N_VGND_c_26_n N_VGND_c_27_n N_VGND_c_28_n
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.spice
index bdf2087..9fe8ed6 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_4.spice
-* Created: Fri Aug 28 10:20:36 2020
+* Created: Wed Sep 2 09:42:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.lvs.report b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.lvs.report
new file mode 100644
index 0000000..5e96dce
--- /dev/null
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decapkapwr_6.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decapkapwr_6.sp ('sky130_fd_sc_lp__decapkapwr_6')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.spice ('sky130_fd_sc_lp__decapkapwr_6')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decapkapwr_6 sky130_fd_sc_lp__decapkapwr_6
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decapkapwr_6
+SOURCE CELL NAME: sky130_fd_sc_lp__decapkapwr_6
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND KAPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pex.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pex.spice
index e529f61..ca227ab 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pex.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_6.pex.spice
-* Created: Fri Aug 28 10:20:49 2020
+* Created: Wed Sep 2 09:42:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pxi.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pxi.spice
index 20b2217..ea6b9b7 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pxi.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_6.pxi.spice
-* Created: Fri Aug 28 10:20:49 2020
+* Created: Wed Sep 2 09:42:40 2020
*
x_PM_SKY130_FD_SC_LP__DECAPKAPWR_6%VGND N_VGND_M1001_s N_VGND_c_25_n
+ N_VGND_c_26_n N_VGND_c_27_n N_VGND_c_28_n N_VGND_c_29_n N_VGND_c_30_n
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.spice
index adcc0e5..c27268b 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_6.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_6.spice
-* Created: Fri Aug 28 10:20:49 2020
+* Created: Wed Sep 2 09:42:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.lvs.report b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.lvs.report
new file mode 100644
index 0000000..d3f1d58
--- /dev/null
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__decapkapwr_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__decapkapwr_8.sp ('sky130_fd_sc_lp__decapkapwr_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.spice ('sky130_fd_sc_lp__decapkapwr_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__decapkapwr_8 sky130_fd_sc_lp__decapkapwr_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__decapkapwr_8
+SOURCE CELL NAME: sky130_fd_sc_lp__decapkapwr_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 5 5
+
+ Nets: 5 5
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 0 0
+
+ Nets: 5 5 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB VGND KAPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pex.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pex.spice
index 2ef4299..c82e37b 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pex.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_8.pex.spice
-* Created: Fri Aug 28 10:20:59 2020
+* Created: Wed Sep 2 09:42:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pxi.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pxi.spice
index 0321a35..df536a0 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pxi.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_8.pxi.spice
-* Created: Fri Aug 28 10:20:59 2020
+* Created: Wed Sep 2 09:42:47 2020
*
x_PM_SKY130_FD_SC_LP__DECAPKAPWR_8%VGND N_VGND_M1000_s N_VGND_c_26_n
+ N_VGND_c_27_n N_VGND_c_28_n N_VGND_c_29_n N_VGND_c_30_n VGND N_VGND_M1001_g
diff --git a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.spice b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.spice
index 30517fc..00c2532 100644
--- a/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.spice
+++ b/cells/decapkapwr/sky130_fd_sc_lp__decapkapwr_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__decapkapwr_8.spice
-* Created: Fri Aug 28 10:20:59 2020
+* Created: Wed Sep 2 09:42:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.lvs.report b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.lvs.report
new file mode 100644
index 0000000..ae82774
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfbbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfbbn_1.sp ('sky130_fd_sc_lp__dfbbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.spice ('sky130_fd_sc_lp__dfbbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfbbn_1 sky130_fd_sc_lp__dfbbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfbbn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pex.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pex.spice
index 6c9003e..fc3f411 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_1.pex.spice
-* Created: Fri Aug 28 10:21:09 2020
+* Created: Wed Sep 2 09:42:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pxi.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pxi.spice
index 975e874..8c4ef73 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_1.pxi.spice
-* Created: Fri Aug 28 10:21:09 2020
+* Created: Wed Sep 2 09:42:54 2020
*
x_PM_SKY130_FD_SC_LP__DFBBN_1%CLK_N N_CLK_N_M1029_g N_CLK_N_M1027_g CLK_N CLK_N
+ CLK_N N_CLK_N_c_281_n N_CLK_N_c_282_n PM_SKY130_FD_SC_LP__DFBBN_1%CLK_N
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.spice
index 28f3824..9dbce5d 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_1.spice
-* Created: Fri Aug 28 10:21:09 2020
+* Created: Wed Sep 2 09:42:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.lvs.report b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.lvs.report
new file mode 100644
index 0000000..ad9f9ec
--- /dev/null
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfbbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfbbn_2.sp ('sky130_fd_sc_lp__dfbbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.spice ('sky130_fd_sc_lp__dfbbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:42:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfbbn_2 sky130_fd_sc_lp__dfbbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfbbn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK_N D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pex.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pex.spice
index 5c542c7..b36bccc 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pex.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_2.pex.spice
-* Created: Fri Aug 28 10:21:17 2020
+* Created: Wed Sep 2 09:43:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pxi.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pxi.spice
index 2e13074..6bf5004 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pxi.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_2.pxi.spice
-* Created: Fri Aug 28 10:21:17 2020
+* Created: Wed Sep 2 09:43:01 2020
*
x_PM_SKY130_FD_SC_LP__DFBBN_2%CLK_N N_CLK_N_c_294_n N_CLK_N_M1025_g
+ N_CLK_N_c_301_n N_CLK_N_M1034_g N_CLK_N_c_296_n N_CLK_N_c_297_n
diff --git a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.spice b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.spice
index 4a67f2f..aa93274 100644
--- a/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.spice
+++ b/cells/dfbbn/sky130_fd_sc_lp__dfbbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbn_2.spice
-* Created: Fri Aug 28 10:21:17 2020
+* Created: Wed Sep 2 09:43:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.lvs.report b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.lvs.report
new file mode 100644
index 0000000..ea22a67
--- /dev/null
+++ b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfbbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfbbp_1.sp ('sky130_fd_sc_lp__dfbbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.spice ('sky130_fd_sc_lp__dfbbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfbbp_1 sky130_fd_sc_lp__dfbbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfbbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 29 29
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 5 5 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pex.spice b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pex.spice
index f74a592..a650feb 100644
--- a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pex.spice
+++ b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbp_1.pex.spice
-* Created: Fri Aug 28 10:21:25 2020
+* Created: Wed Sep 2 09:43:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pxi.spice b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pxi.spice
index 4d0635b..e589587 100644
--- a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pxi.spice
+++ b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbp_1.pxi.spice
-* Created: Fri Aug 28 10:21:25 2020
+* Created: Wed Sep 2 09:43:07 2020
*
x_PM_SKY130_FD_SC_LP__DFBBP_1%CLK N_CLK_c_259_n N_CLK_M1018_g N_CLK_c_266_n
+ N_CLK_M1033_g N_CLK_c_261_n N_CLK_c_262_n N_CLK_c_267_n CLK CLK CLK
diff --git a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.spice b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.spice
index 630567b..1f5a55e 100644
--- a/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.spice
+++ b/cells/dfbbp/sky130_fd_sc_lp__dfbbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfbbp_1.spice
-* Created: Fri Aug 28 10:21:25 2020
+* Created: Wed Sep 2 09:43:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.lvs.report b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.lvs.report
new file mode 100644
index 0000000..2f1e257
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrbp_1.sp ('sky130_fd_sc_lp__dfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.spice ('sky130_fd_sc_lp__dfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrbp_1 sky130_fd_sc_lp__dfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 13 13 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pex.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pex.spice
index 20f8a06..1fafe42 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_1.pex.spice
-* Created: Fri Aug 28 10:21:33 2020
+* Created: Wed Sep 2 09:43:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pxi.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pxi.spice
index 87ef113..be819ae 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_1.pxi.spice
-* Created: Fri Aug 28 10:21:33 2020
+* Created: Wed Sep 2 09:43:14 2020
*
x_PM_SKY130_FD_SC_LP__DFRBP_1%CLK N_CLK_M1027_g N_CLK_M1012_g CLK CLK
+ N_CLK_c_248_n PM_SKY130_FD_SC_LP__DFRBP_1%CLK
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.spice
index 880bfbe..d82a5f5 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_1.spice
-* Created: Fri Aug 28 10:21:33 2020
+* Created: Wed Sep 2 09:43:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.lvs.report b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.lvs.report
new file mode 100644
index 0000000..9fa3db9
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrbp_2.sp ('sky130_fd_sc_lp__dfrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.spice ('sky130_fd_sc_lp__dfrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrbp_2 sky130_fd_sc_lp__dfrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 13 13 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pex.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pex.spice
index 46e4e38..f1d9b4e 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_2.pex.spice
-* Created: Fri Aug 28 10:21:42 2020
+* Created: Wed Sep 2 09:43:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pxi.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pxi.spice
index 0782ec0..0fd573d 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_2.pxi.spice
-* Created: Fri Aug 28 10:21:42 2020
+* Created: Wed Sep 2 09:43:21 2020
*
x_PM_SKY130_FD_SC_LP__DFRBP_2%CLK N_CLK_M1033_g N_CLK_c_246_n N_CLK_M1005_g CLK
+ CLK PM_SKY130_FD_SC_LP__DFRBP_2%CLK
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.spice
index 1d23f15..5e70eea 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_2.spice
-* Created: Fri Aug 28 10:21:42 2020
+* Created: Wed Sep 2 09:43:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.lvs.report b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.lvs.report
new file mode 100644
index 0000000..5ff71db
--- /dev/null
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrbp_lp.sp ('sky130_fd_sc_lp__dfrbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.spice ('sky130_fd_sc_lp__dfrbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrbp_lp sky130_fd_sc_lp__dfrbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 41 41
+
+ Instances: 23 23 MN (4 pins)
+ 28 28 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 52 51
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 13 13 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 1 1 0 0 SMN3
+ 13 13 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pex.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pex.spice
index 71770af..9ccd5e9 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pex.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_lp.pex.spice
-* Created: Fri Aug 28 10:21:56 2020
+* Created: Wed Sep 2 09:43:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pxi.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pxi.spice
index da88233..4d3b001 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pxi.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_lp.pxi.spice
-* Created: Fri Aug 28 10:21:56 2020
+* Created: Wed Sep 2 09:43:27 2020
*
x_PM_SKY130_FD_SC_LP__DFRBP_LP%D N_D_M1043_g N_D_c_335_n N_D_c_336_n N_D_M1012_g
+ N_D_M1023_g N_D_c_329_n N_D_c_330_n N_D_c_331_n D D D N_D_c_333_n
diff --git a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.spice b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.spice
index bba47a8..b7671a6 100644
--- a/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.spice
+++ b/cells/dfrbp/sky130_fd_sc_lp__dfrbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrbp_lp.spice
-* Created: Fri Aug 28 10:21:56 2020
+* Created: Wed Sep 2 09:43:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.lvs.report b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.lvs.report
new file mode 100644
index 0000000..c1e351e
--- /dev/null
+++ b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrtn_1.sp ('sky130_fd_sc_lp__dfrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.spice ('sky130_fd_sc_lp__dfrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrtn_1 sky130_fd_sc_lp__dfrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrtn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D RESET_B CLK_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pex.spice b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pex.spice
index 7993833..7e54fe3 100644
--- a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pex.spice
+++ b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtn_1.pex.spice
-* Created: Fri Aug 28 10:22:05 2020
+* Created: Wed Sep 2 09:43:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pxi.spice b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pxi.spice
index c6dea96..9677e2a 100644
--- a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pxi.spice
+++ b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtn_1.pxi.spice
-* Created: Fri Aug 28 10:22:05 2020
+* Created: Wed Sep 2 09:43:34 2020
*
x_PM_SKY130_FD_SC_LP__DFRTN_1%D N_D_M1020_g N_D_M1004_g D D D N_D_c_230_n
+ N_D_c_231_n PM_SKY130_FD_SC_LP__DFRTN_1%D
diff --git a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.spice b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.spice
index b2db38b..114dd37 100644
--- a/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.spice
+++ b/cells/dfrtn/sky130_fd_sc_lp__dfrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtn_1.spice
-* Created: Fri Aug 28 10:22:05 2020
+* Created: Wed Sep 2 09:43:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.lvs.report b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.lvs.report
new file mode 100644
index 0000000..000e545
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrtp_1.sp ('sky130_fd_sc_lp__dfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.spice ('sky130_fd_sc_lp__dfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrtp_1 sky130_fd_sc_lp__dfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pex.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pex.spice
index 52df3e9..1af4d41 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_1.pex.spice
-* Created: Fri Aug 28 10:22:14 2020
+* Created: Wed Sep 2 09:43:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pxi.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pxi.spice
index 12f0229..f880f01 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_1.pxi.spice
-* Created: Fri Aug 28 10:22:14 2020
+* Created: Wed Sep 2 09:43:41 2020
*
x_PM_SKY130_FD_SC_LP__DFRTP_1%CLK N_CLK_M1013_g N_CLK_M1020_g N_CLK_c_236_n
+ N_CLK_c_241_n CLK CLK N_CLK_c_237_n N_CLK_c_238_n
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.spice
index 9628857..5b4a42e 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_1.spice
-* Created: Fri Aug 28 10:22:14 2020
+* Created: Wed Sep 2 09:43:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.lvs.report b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.lvs.report
new file mode 100644
index 0000000..3553504
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrtp_2.sp ('sky130_fd_sc_lp__dfrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.spice ('sky130_fd_sc_lp__dfrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrtp_2 sky130_fd_sc_lp__dfrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrtp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pex.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pex.spice
index e07a10c..6d7a9b3 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_2.pex.spice
-* Created: Fri Aug 28 10:22:22 2020
+* Created: Wed Sep 2 09:43:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pxi.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pxi.spice
index 0d51904..6300920 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_2.pxi.spice
-* Created: Fri Aug 28 10:22:22 2020
+* Created: Wed Sep 2 09:43:47 2020
*
x_PM_SKY130_FD_SC_LP__DFRTP_2%CLK N_CLK_M1009_g N_CLK_M1003_g N_CLK_c_261_n
+ N_CLK_c_266_n CLK CLK N_CLK_c_262_n N_CLK_c_263_n
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.spice
index 2a45f75..1059cac 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_2.spice
-* Created: Fri Aug 28 10:22:22 2020
+* Created: Wed Sep 2 09:43:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.lvs.report b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.lvs.report
new file mode 100644
index 0000000..8a026c7
--- /dev/null
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfrtp_4.sp ('sky130_fd_sc_lp__dfrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.spice ('sky130_fd_sc_lp__dfrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfrtp_4 sky130_fd_sc_lp__dfrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfrtp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 23 23
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 12 12 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 25 25
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 25 25 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pex.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pex.spice
index 07a641b..e2dcff5 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pex.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_4.pex.spice
-* Created: Fri Aug 28 10:22:30 2020
+* Created: Wed Sep 2 09:43:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pxi.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pxi.spice
index 3e825c2..ffc52c5 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pxi.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_4.pxi.spice
-* Created: Fri Aug 28 10:22:30 2020
+* Created: Wed Sep 2 09:43:54 2020
*
x_PM_SKY130_FD_SC_LP__DFRTP_4%CLK N_CLK_M1020_g N_CLK_M1036_g N_CLK_c_264_n
+ N_CLK_c_269_n CLK CLK CLK N_CLK_c_266_n PM_SKY130_FD_SC_LP__DFRTP_4%CLK
diff --git a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.spice b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.spice
index 37f8c5d..161d14e 100644
--- a/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.spice
+++ b/cells/dfrtp/sky130_fd_sc_lp__dfrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfrtp_4.spice
-* Created: Fri Aug 28 10:22:30 2020
+* Created: Wed Sep 2 09:43:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.lvs.report b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.lvs.report
new file mode 100644
index 0000000..31702e2
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfsbp_1.sp ('sky130_fd_sc_lp__dfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.spice ('sky130_fd_sc_lp__dfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:43:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfsbp_1 sky130_fd_sc_lp__dfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pex.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pex.spice
index 079bcda..b8a3a06 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_1.pex.spice
-* Created: Fri Aug 28 10:22:38 2020
+* Created: Wed Sep 2 09:44:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pxi.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pxi.spice
index d295c75..5f686b0 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_1.pxi.spice
-* Created: Fri Aug 28 10:22:38 2020
+* Created: Wed Sep 2 09:44:01 2020
*
x_PM_SKY130_FD_SC_LP__DFSBP_1%CLK N_CLK_c_259_n N_CLK_M1025_g N_CLK_M1021_g
+ N_CLK_c_265_n CLK CLK CLK CLK N_CLK_c_261_n N_CLK_c_262_n CLK
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.spice
index 00ded65..1df5949 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_1.spice
-* Created: Fri Aug 28 10:22:38 2020
+* Created: Wed Sep 2 09:44:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.lvs.report b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.lvs.report
new file mode 100644
index 0000000..a474dc2
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfsbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfsbp_2.sp ('sky130_fd_sc_lp__dfsbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.spice ('sky130_fd_sc_lp__dfsbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfsbp_2 sky130_fd_sc_lp__dfsbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfsbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pex.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pex.spice
index 1fa1358..d27b836 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_2.pex.spice
-* Created: Fri Aug 28 10:22:46 2020
+* Created: Wed Sep 2 09:44:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pxi.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pxi.spice
index b078314..4633564 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_2.pxi.spice
-* Created: Fri Aug 28 10:22:46 2020
+* Created: Wed Sep 2 09:44:07 2020
*
x_PM_SKY130_FD_SC_LP__DFSBP_2%CLK N_CLK_M1002_g N_CLK_M1000_g CLK CLK
+ N_CLK_c_264_n N_CLK_c_265_n PM_SKY130_FD_SC_LP__DFSBP_2%CLK
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.spice
index 818321f..b905bb6 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_2.spice
-* Created: Fri Aug 28 10:22:46 2020
+* Created: Wed Sep 2 09:44:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.lvs.report b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.lvs.report
new file mode 100644
index 0000000..5b313ea
--- /dev/null
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfsbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfsbp_lp.sp ('sky130_fd_sc_lp__dfsbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.spice ('sky130_fd_sc_lp__dfsbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfsbp_lp sky130_fd_sc_lp__dfsbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfsbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dfsbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 32 32
+
+ Instances: 24 24 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 42 41
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 1 1 MN (4 pins)
+ 11 11 MP (4 pins)
+ 10 10 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 10 10 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pex.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pex.spice
index 00f07ad..ad0327d 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pex.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_lp.pex.spice
-* Created: Fri Aug 28 10:23:00 2020
+* Created: Wed Sep 2 09:44:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pxi.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pxi.spice
index 6289fca..bea1415 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pxi.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_lp.pxi.spice
-* Created: Fri Aug 28 10:23:00 2020
+* Created: Wed Sep 2 09:44:14 2020
*
x_PM_SKY130_FD_SC_LP__DFSBP_LP%D N_D_c_280_n N_D_M1019_g N_D_M1002_g N_D_c_281_n
+ N_D_M1010_g N_D_c_282_n D D N_D_c_283_n N_D_c_284_n N_D_c_285_n
diff --git a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.spice b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.spice
index 022a055..38c8e10 100644
--- a/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.spice
+++ b/cells/dfsbp/sky130_fd_sc_lp__dfsbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfsbp_lp.spice
-* Created: Fri Aug 28 10:23:00 2020
+* Created: Wed Sep 2 09:44:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.lvs.report b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.lvs.report
new file mode 100644
index 0000000..fe52775
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfstp_1.sp ('sky130_fd_sc_lp__dfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfstp/sky130_fd_sc_lp__dfstp_1.spice ('sky130_fd_sc_lp__dfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfstp_1 sky130_fd_sc_lp__dfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfstp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pex.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pex.spice
index 16a80f4..8537bb0 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_1.pex.spice
-* Created: Fri Aug 28 10:23:09 2020
+* Created: Wed Sep 2 09:44:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pxi.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pxi.spice
index d6bd467..d57b914 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_1.pxi.spice
-* Created: Fri Aug 28 10:23:09 2020
+* Created: Wed Sep 2 09:44:20 2020
*
x_PM_SKY130_FD_SC_LP__DFSTP_1%CLK N_CLK_c_216_n N_CLK_c_221_n N_CLK_M1012_g
+ N_CLK_c_217_n N_CLK_M1017_g N_CLK_c_222_n CLK CLK N_CLK_c_219_n
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.spice
index 316847e..065b1f0 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_1.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_1.spice
-* Created: Fri Aug 28 10:23:09 2020
+* Created: Wed Sep 2 09:44:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.lvs.report b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.lvs.report
new file mode 100644
index 0000000..35c97bd
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfstp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfstp_2.sp ('sky130_fd_sc_lp__dfstp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfstp/sky130_fd_sc_lp__dfstp_2.spice ('sky130_fd_sc_lp__dfstp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfstp_2 sky130_fd_sc_lp__dfstp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfstp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pex.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pex.spice
index ace139a..d306cf5 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_2.pex.spice
-* Created: Fri Aug 28 10:23:18 2020
+* Created: Wed Sep 2 09:44:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pxi.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pxi.spice
index ba4adc9..147ce44 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_2.pxi.spice
-* Created: Fri Aug 28 10:23:18 2020
+* Created: Wed Sep 2 09:44:27 2020
*
x_PM_SKY130_FD_SC_LP__DFSTP_2%CLK N_CLK_c_246_n N_CLK_c_251_n N_CLK_M1009_g
+ N_CLK_M1007_g N_CLK_c_252_n CLK CLK N_CLK_c_249_n
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.spice
index ddeb1c8..64f7eaf 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_2.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_2.spice
-* Created: Fri Aug 28 10:23:18 2020
+* Created: Wed Sep 2 09:44:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.lvs.report b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.lvs.report
new file mode 100644
index 0000000..9bc75c4
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfstp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfstp_4.sp ('sky130_fd_sc_lp__dfstp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfstp/sky130_fd_sc_lp__dfstp_4.spice ('sky130_fd_sc_lp__dfstp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfstp_4 sky130_fd_sc_lp__dfstp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfstp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pex.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pex.spice
index 71c325b..3789ad5 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_4.pex.spice
-* Created: Fri Aug 28 10:23:26 2020
+* Created: Wed Sep 2 09:44:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pxi.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pxi.spice
index c37b26c..d636b19 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_4.pxi.spice
-* Created: Fri Aug 28 10:23:26 2020
+* Created: Wed Sep 2 09:44:34 2020
*
x_PM_SKY130_FD_SC_LP__DFSTP_4%CLK N_CLK_M1013_g N_CLK_c_249_n N_CLK_M1005_g
+ N_CLK_c_250_n CLK CLK CLK CLK CLK N_CLK_c_252_n N_CLK_c_253_n
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.spice
index c97d549..5f57999 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_4.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_4.spice
-* Created: Fri Aug 28 10:23:26 2020
+* Created: Wed Sep 2 09:44:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.lvs.report b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.lvs.report
new file mode 100644
index 0000000..a7c7a8e
--- /dev/null
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfstp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfstp_lp.sp ('sky130_fd_sc_lp__dfstp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.spice ('sky130_fd_sc_lp__dfstp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfstp_lp sky130_fd_sc_lp__dfstp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfstp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dfstp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 30 30
+
+ Instances: 22 22 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 1 1 MN (4 pins)
+ 10 10 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pex.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pex.spice
index 56a2875..9e2f725 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pex.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_lp.pex.spice
-* Created: Fri Aug 28 10:23:33 2020
+* Created: Wed Sep 2 09:44:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pxi.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pxi.spice
index dcc282e..b2fa3b3 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pxi.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_lp.pxi.spice
-* Created: Fri Aug 28 10:23:33 2020
+* Created: Wed Sep 2 09:44:41 2020
*
x_PM_SKY130_FD_SC_LP__DFSTP_LP%D N_D_c_270_n N_D_M1022_g N_D_M1005_g N_D_c_271_n
+ N_D_M1010_g N_D_c_272_n D D N_D_c_273_n N_D_c_274_n N_D_c_275_n
diff --git a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.spice b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.spice
index 78acad9..39c35b8 100644
--- a/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.spice
+++ b/cells/dfstp/sky130_fd_sc_lp__dfstp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfstp_lp.spice
-* Created: Fri Aug 28 10:23:33 2020
+* Created: Wed Sep 2 09:44:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.lvs.report b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.lvs.report
new file mode 100644
index 0000000..88d7b6c
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxbp_1.sp ('sky130_fd_sc_lp__dfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.spice ('sky130_fd_sc_lp__dfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxbp_1 sky130_fd_sc_lp__dfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pex.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pex.spice
index b7b04ca..a48d2f5 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_1.pex.spice
-* Created: Fri Aug 28 10:23:41 2020
+* Created: Wed Sep 2 09:44:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pxi.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pxi.spice
index 4e18771..431e8e1 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_1.pxi.spice
-* Created: Fri Aug 28 10:23:41 2020
+* Created: Wed Sep 2 09:44:47 2020
*
x_PM_SKY130_FD_SC_LP__DFXBP_1%CLK N_CLK_c_181_n N_CLK_M1004_g N_CLK_M1026_g
+ N_CLK_c_183_n CLK CLK CLK CLK N_CLK_c_185_n N_CLK_c_186_n
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.spice
index 8973127..ac38c82 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_1.spice
-* Created: Fri Aug 28 10:23:41 2020
+* Created: Wed Sep 2 09:44:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.lvs.report b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.lvs.report
new file mode 100644
index 0000000..ba1b02f
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxbp_2.sp ('sky130_fd_sc_lp__dfxbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.spice ('sky130_fd_sc_lp__dfxbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxbp_2 sky130_fd_sc_lp__dfxbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pex.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pex.spice
index a731177..e3f2831 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_2.pex.spice
-* Created: Fri Aug 28 10:23:49 2020
+* Created: Wed Sep 2 09:44:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pxi.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pxi.spice
index b167f24..5a34c2f 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_2.pxi.spice
-* Created: Fri Aug 28 10:23:49 2020
+* Created: Wed Sep 2 09:44:54 2020
*
x_PM_SKY130_FD_SC_LP__DFXBP_2%CLK N_CLK_M1008_g N_CLK_M1002_g N_CLK_c_193_n
+ N_CLK_c_194_n N_CLK_c_195_n CLK CLK CLK N_CLK_c_197_n
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.spice
index 6e54b2b..eec95c8 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_2.spice
-* Created: Fri Aug 28 10:23:49 2020
+* Created: Wed Sep 2 09:44:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.lvs.report b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.lvs.report
new file mode 100644
index 0000000..419af00
--- /dev/null
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxbp_lp.sp ('sky130_fd_sc_lp__dfxbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.spice ('sky130_fd_sc_lp__dfxbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:44:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxbp_lp sky130_fd_sc_lp__dfxbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 28 28
+
+ Instances: 22 22 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 2 2 MN (4 pins)
+ 10 10 MP (4 pins)
+ 10 10 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 10 10 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pex.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pex.spice
index 07d13ed..b0e22a6 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pex.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_lp.pex.spice
-* Created: Fri Aug 28 10:24:02 2020
+* Created: Wed Sep 2 09:45:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pxi.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pxi.spice
index 09a3bcb..29ff67f 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pxi.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_lp.pxi.spice
-* Created: Fri Aug 28 10:24:02 2020
+* Created: Wed Sep 2 09:45:00 2020
*
x_PM_SKY130_FD_SC_LP__DFXBP_LP%CLK N_CLK_M1013_g N_CLK_c_221_n N_CLK_M1018_g
+ N_CLK_c_222_n N_CLK_M1006_g CLK CLK N_CLK_c_224_n
diff --git a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.spice b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.spice
index eb94dc6..99d0119 100644
--- a/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.spice
+++ b/cells/dfxbp/sky130_fd_sc_lp__dfxbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxbp_lp.spice
-* Created: Fri Aug 28 10:24:02 2020
+* Created: Wed Sep 2 09:45:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.lvs.report b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.lvs.report
new file mode 100644
index 0000000..755a8ec
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxtp_1.sp ('sky130_fd_sc_lp__dfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.spice ('sky130_fd_sc_lp__dfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:04 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxtp_1 sky130_fd_sc_lp__dfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pex.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pex.spice
index 5b848cb..f02570d 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_1.pex.spice
-* Created: Fri Aug 28 10:24:12 2020
+* Created: Wed Sep 2 09:45:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pxi.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pxi.spice
index e0b69d2..10cfd02 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_1.pxi.spice
-* Created: Fri Aug 28 10:24:12 2020
+* Created: Wed Sep 2 09:45:07 2020
*
x_PM_SKY130_FD_SC_LP__DFXTP_1%CLK N_CLK_c_151_n N_CLK_M1002_g N_CLK_M1021_g
+ N_CLK_c_153_n N_CLK_c_154_n N_CLK_c_159_n CLK CLK CLK CLK N_CLK_c_156_n
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.spice
index c0f573c..3ed5be3 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_1.spice
-* Created: Fri Aug 28 10:24:12 2020
+* Created: Wed Sep 2 09:45:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.lvs.report b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.lvs.report
new file mode 100644
index 0000000..3862aa9
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxtp_2.sp ('sky130_fd_sc_lp__dfxtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.spice ('sky130_fd_sc_lp__dfxtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxtp_2 sky130_fd_sc_lp__dfxtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxtp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pex.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pex.spice
index abb00da..a6af30e 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_2.pex.spice
-* Created: Fri Aug 28 10:24:21 2020
+* Created: Wed Sep 2 09:45:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pxi.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pxi.spice
index 7e806fd..3e05b46 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_2.pxi.spice
-* Created: Fri Aug 28 10:24:21 2020
+* Created: Wed Sep 2 09:45:14 2020
*
x_PM_SKY130_FD_SC_LP__DFXTP_2%CLK N_CLK_c_158_n N_CLK_M1023_g N_CLK_M1021_g
+ N_CLK_c_160_n CLK CLK CLK CLK CLK N_CLK_c_162_n N_CLK_c_163_n
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.spice
index adbadf0..e701a44 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_2.spice
-* Created: Fri Aug 28 10:24:21 2020
+* Created: Wed Sep 2 09:45:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.lvs.report b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.lvs.report
new file mode 100644
index 0000000..ac8dd06
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxtp_4.sp ('sky130_fd_sc_lp__dfxtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.spice ('sky130_fd_sc_lp__dfxtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxtp_4 sky130_fd_sc_lp__dfxtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxtp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 15 15 MN (4 pins)
+ 15 15 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pex.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pex.spice
index 0582a15..cbacff4 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_4.pex.spice
-* Created: Fri Aug 28 10:24:29 2020
+* Created: Wed Sep 2 09:45:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pxi.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pxi.spice
index c74b518..15fbc5a 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_4.pxi.spice
-* Created: Fri Aug 28 10:24:29 2020
+* Created: Wed Sep 2 09:45:21 2020
*
x_PM_SKY130_FD_SC_LP__DFXTP_4%CLK N_CLK_c_188_n N_CLK_M1004_g N_CLK_M1023_g
+ N_CLK_c_190_n CLK CLK CLK CLK CLK N_CLK_c_192_n N_CLK_c_193_n
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.spice
index f8b79e7..ba347d7 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_4.spice
-* Created: Fri Aug 28 10:24:29 2020
+* Created: Wed Sep 2 09:45:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.lvs.report b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.lvs.report
new file mode 100644
index 0000000..90309eb
--- /dev/null
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dfxtp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dfxtp_lp.sp ('sky130_fd_sc_lp__dfxtp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.spice ('sky130_fd_sc_lp__dfxtp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dfxtp_lp sky130_fd_sc_lp__dfxtp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dfxtp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dfxtp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 24 24
+
+ Instances: 18 18 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 2 2 MN (4 pins)
+ 8 8 MP (4 pins)
+ 8 8 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 20 20
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 8 8 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 20 20 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CLK D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pex.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pex.spice
index 1d4a944..f293094 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pex.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_lp.pex.spice
-* Created: Fri Aug 28 10:24:36 2020
+* Created: Wed Sep 2 09:45:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pxi.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pxi.spice
index 403fcb7..4ef1440 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pxi.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_lp.pxi.spice
-* Created: Fri Aug 28 10:24:36 2020
+* Created: Wed Sep 2 09:45:28 2020
*
x_PM_SKY130_FD_SC_LP__DFXTP_LP%CLK N_CLK_M1026_g N_CLK_M1003_g N_CLK_M1020_g
+ N_CLK_c_195_n N_CLK_c_199_n CLK CLK N_CLK_c_197_n
diff --git a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.spice b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.spice
index a67dcb9..4bf0c77 100644
--- a/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.spice
+++ b/cells/dfxtp/sky130_fd_sc_lp__dfxtp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dfxtp_lp.spice
-* Created: Fri Aug 28 10:24:36 2020
+* Created: Wed Sep 2 09:45:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/diode/sky130_fd_sc_lp__diode_0.lvs.report b/cells/diode/sky130_fd_sc_lp__diode_0.lvs.report
new file mode 100644
index 0000000..865fde2
--- /dev/null
+++ b/cells/diode/sky130_fd_sc_lp__diode_0.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__diode_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__diode_0.sp ('sky130_fd_sc_lp__diode_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/diode/sky130_fd_sc_lp__diode_0.spice ('sky130_fd_sc_lp__diode_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/diode/sky130_fd_sc_lp__diode_1.lvs.report b/cells/diode/sky130_fd_sc_lp__diode_1.lvs.report
new file mode 100644
index 0000000..1e180d4
--- /dev/null
+++ b/cells/diode/sky130_fd_sc_lp__diode_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__diode_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__diode_1.sp ('sky130_fd_sc_lp__diode_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/diode/sky130_fd_sc_lp__diode_1.spice ('sky130_fd_sc_lp__diode_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.lvs.report b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.lvs.report
new file mode 100644
index 0000000..b7d02cb
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlclkp_1.sp ('sky130_fd_sc_lp__dlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.spice ('sky130_fd_sc_lp__dlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlclkp_1 sky130_fd_sc_lp__dlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pex.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pex.spice
index 4480887..e91161e 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_1.pex.spice
-* Created: Fri Aug 28 10:24:51 2020
+* Created: Wed Sep 2 09:45:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pxi.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pxi.spice
index 5b96bdd..fa702ef 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_1.pxi.spice
-* Created: Fri Aug 28 10:24:51 2020
+* Created: Wed Sep 2 09:45:41 2020
*
x_PM_SKY130_FD_SC_LP__DLCLKP_1%A_80_269# N_A_80_269#_M1016_d N_A_80_269#_M1000_d
+ N_A_80_269#_M1019_g N_A_80_269#_M1008_g N_A_80_269#_c_156_n
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.spice
index 47bf4ce..59fb1e9 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_1.spice
-* Created: Fri Aug 28 10:24:51 2020
+* Created: Wed Sep 2 09:45:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.lvs.report b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.lvs.report
new file mode 100644
index 0000000..b5b818d
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlclkp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlclkp_2.sp ('sky130_fd_sc_lp__dlclkp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.spice ('sky130_fd_sc_lp__dlclkp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlclkp_2 sky130_fd_sc_lp__dlclkp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlclkp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pex.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pex.spice
index 1df2fb9..3d31e91 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_2.pex.spice
-* Created: Fri Aug 28 10:25:05 2020
+* Created: Wed Sep 2 09:45:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pxi.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pxi.spice
index 9383bc9..5816eb7 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_2.pxi.spice
-* Created: Fri Aug 28 10:25:05 2020
+* Created: Wed Sep 2 09:45:47 2020
*
x_PM_SKY130_FD_SC_LP__DLCLKP_2%A_78_269# N_A_78_269#_M1015_d N_A_78_269#_M1004_d
+ N_A_78_269#_M1009_g N_A_78_269#_M1005_g N_A_78_269#_c_150_n
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.spice
index 0125184..b483356 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_2.spice
-* Created: Fri Aug 28 10:25:05 2020
+* Created: Wed Sep 2 09:45:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.lvs.report b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.lvs.report
new file mode 100644
index 0000000..644f0c5
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlclkp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlclkp_4.sp ('sky130_fd_sc_lp__dlclkp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.spice ('sky130_fd_sc_lp__dlclkp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlclkp_4 sky130_fd_sc_lp__dlclkp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlclkp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 17 17
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pex.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pex.spice
index e8ce22a..b09be37 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_4.pex.spice
-* Created: Fri Aug 28 10:25:14 2020
+* Created: Wed Sep 2 09:45:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pxi.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pxi.spice
index cb1ef89..399e735 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_4.pxi.spice
-* Created: Fri Aug 28 10:25:14 2020
+* Created: Wed Sep 2 09:45:54 2020
*
x_PM_SKY130_FD_SC_LP__DLCLKP_4%A_73_269# N_A_73_269#_M1001_d N_A_73_269#_M1020_d
+ N_A_73_269#_M1025_g N_A_73_269#_M1022_g N_A_73_269#_c_170_n
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.spice
index eef6ae2..b6c8c27 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_4.spice
-* Created: Fri Aug 28 10:25:14 2020
+* Created: Wed Sep 2 09:45:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.lvs.report b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.lvs.report
new file mode 100644
index 0000000..db93cac
--- /dev/null
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlclkp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlclkp_lp.sp ('sky130_fd_sc_lp__dlclkp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.spice ('sky130_fd_sc_lp__dlclkp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:45:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlclkp_lp sky130_fd_sc_lp__dlclkp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlclkp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlclkp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 6 6 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pex.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pex.spice
index 7919730..2b72cdf 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pex.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_lp.pex.spice
-* Created: Fri Aug 28 10:25:24 2020
+* Created: Wed Sep 2 09:46:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pxi.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pxi.spice
index be8cd7d..60aeffb 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pxi.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_lp.pxi.spice
-* Created: Fri Aug 28 10:25:24 2020
+* Created: Wed Sep 2 09:46:01 2020
*
x_PM_SKY130_FD_SC_LP__DLCLKP_LP%A_80_21# N_A_80_21#_M1016_s N_A_80_21#_M1020_s
+ N_A_80_21#_M1013_g N_A_80_21#_M1003_g N_A_80_21#_M1000_g N_A_80_21#_M1010_g
diff --git a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.spice b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.spice
index 7490703..ea625ee 100644
--- a/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.spice
+++ b/cells/dlclkp/sky130_fd_sc_lp__dlclkp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlclkp_lp.spice
-* Created: Fri Aug 28 10:25:24 2020
+* Created: Wed Sep 2 09:46:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.lvs.report b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.lvs.report
new file mode 100644
index 0000000..e1f75e5
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbn_1.sp ('sky130_fd_sc_lp__dlrbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.spice ('sky130_fd_sc_lp__dlrbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbn_1 sky130_fd_sc_lp__dlrbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE_N D RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pex.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pex.spice
index df07c26..1bbc2e8 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_1.pex.spice
-* Created: Fri Aug 28 10:25:32 2020
+* Created: Wed Sep 2 09:46:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pxi.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pxi.spice
index 0a1598a..e3107b3 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_1.pxi.spice
-* Created: Fri Aug 28 10:25:32 2020
+* Created: Wed Sep 2 09:46:08 2020
*
x_PM_SKY130_FD_SC_LP__DLRBN_1%GATE_N N_GATE_N_c_192_n N_GATE_N_M1009_g
+ N_GATE_N_M1011_g N_GATE_N_c_198_n GATE_N GATE_N GATE_N GATE_N N_GATE_N_c_195_n
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.spice
index 146e3cc..03088d9 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_1.spice
-* Created: Fri Aug 28 10:25:32 2020
+* Created: Wed Sep 2 09:46:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.lvs.report b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.lvs.report
new file mode 100644
index 0000000..4b05e68
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbn_2.sp ('sky130_fd_sc_lp__dlrbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.spice ('sky130_fd_sc_lp__dlrbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbn_2 sky130_fd_sc_lp__dlrbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE_N D RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pex.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pex.spice
index dc28f19..bd17b4a 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_2.pex.spice
-* Created: Fri Aug 28 10:25:40 2020
+* Created: Wed Sep 2 09:46:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pxi.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pxi.spice
index 3a71b36..b72e5cd 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_2.pxi.spice
-* Created: Fri Aug 28 10:25:40 2020
+* Created: Wed Sep 2 09:46:15 2020
*
x_PM_SKY130_FD_SC_LP__DLRBN_2%GATE_N N_GATE_N_c_188_n N_GATE_N_M1007_g
+ N_GATE_N_M1026_g N_GATE_N_c_194_n GATE_N GATE_N GATE_N GATE_N N_GATE_N_c_190_n
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.spice
index 26489c1..1ab08df 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_2.spice
-* Created: Fri Aug 28 10:25:40 2020
+* Created: Wed Sep 2 09:46:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.lvs.report b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.lvs.report
new file mode 100644
index 0000000..9bd821f
--- /dev/null
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbn_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbn_lp.sp ('sky130_fd_sc_lp__dlrbn_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.spice ('sky130_fd_sc_lp__dlrbn_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbn_lp sky130_fd_sc_lp__dlrbn_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbn_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbn_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 26 26
+
+ Instances: 18 18 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 8 8 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pex.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pex.spice
index 9dc8eff..b659743 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pex.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_lp.pex.spice
-* Created: Fri Aug 28 10:25:47 2020
+* Created: Wed Sep 2 09:46:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pxi.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pxi.spice
index d48879b..52e3462 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pxi.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_lp.pxi.spice
-* Created: Fri Aug 28 10:25:47 2020
+* Created: Wed Sep 2 09:46:22 2020
*
x_PM_SKY130_FD_SC_LP__DLRBN_LP%D N_D_M1015_g N_D_M1013_g N_D_M1002_g N_D_c_190_n
+ N_D_c_191_n D D N_D_c_192_n N_D_c_193_n PM_SKY130_FD_SC_LP__DLRBN_LP%D
diff --git a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.spice b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.spice
index ae33cb0..a81195c 100644
--- a/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.spice
+++ b/cells/dlrbn/sky130_fd_sc_lp__dlrbn_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbn_lp.spice
-* Created: Fri Aug 28 10:25:47 2020
+* Created: Wed Sep 2 09:46:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.lvs.report b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.lvs.report
new file mode 100644
index 0000000..cc2d70a
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbp_1.sp ('sky130_fd_sc_lp__dlrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.spice ('sky130_fd_sc_lp__dlrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbp_1 sky130_fd_sc_lp__dlrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE D RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pex.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pex.spice
index f329a26..04c13fd 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_1.pex.spice
-* Created: Fri Aug 28 10:25:55 2020
+* Created: Wed Sep 2 09:46:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pxi.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pxi.spice
index 40e44a3..b127332 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_1.pxi.spice
-* Created: Fri Aug 28 10:25:55 2020
+* Created: Wed Sep 2 09:46:29 2020
*
x_PM_SKY130_FD_SC_LP__DLRBP_1%GATE N_GATE_M1004_g N_GATE_c_172_n N_GATE_M1011_g
+ N_GATE_c_173_n GATE GATE N_GATE_c_174_n N_GATE_c_175_n N_GATE_c_176_n
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.spice
index b69dad9..57b5ef9 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_1.spice
-* Created: Fri Aug 28 10:25:55 2020
+* Created: Wed Sep 2 09:46:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.lvs.report b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.lvs.report
new file mode 100644
index 0000000..7889ada
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbp_2.sp ('sky130_fd_sc_lp__dlrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.spice ('sky130_fd_sc_lp__dlrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbp_2 sky130_fd_sc_lp__dlrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB RESET_B D GATE VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pex.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pex.spice
index 3c90529..beb9584 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_2.pex.spice
-* Created: Fri Aug 28 10:26:09 2020
+* Created: Wed Sep 2 09:46:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pxi.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pxi.spice
index dedd3d3..6fb8400 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_2.pxi.spice
-* Created: Fri Aug 28 10:26:09 2020
+* Created: Wed Sep 2 09:46:35 2020
*
x_PM_SKY130_FD_SC_LP__DLRBP_2%A_80_21# N_A_80_21#_M1009_s N_A_80_21#_M1021_s
+ N_A_80_21#_M1007_g N_A_80_21#_M1006_g N_A_80_21#_M1012_g N_A_80_21#_M1027_g
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.spice
index 93ea893..d5562af 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_2.spice
-* Created: Fri Aug 28 10:26:09 2020
+* Created: Wed Sep 2 09:46:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.lvs.report b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.lvs.report
new file mode 100644
index 0000000..1c49995
--- /dev/null
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrbp_lp.sp ('sky130_fd_sc_lp__dlrbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.spice ('sky130_fd_sc_lp__dlrbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrbp_lp sky130_fd_sc_lp__dlrbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 26 26
+
+ Instances: 18 18 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 8 8 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pex.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pex.spice
index 9269984..7011abb 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pex.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_lp.pex.spice
-* Created: Fri Aug 28 10:26:18 2020
+* Created: Wed Sep 2 09:46:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pxi.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pxi.spice
index 9784abe..58c86c2 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pxi.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_lp.pxi.spice
-* Created: Fri Aug 28 10:26:18 2020
+* Created: Wed Sep 2 09:46:42 2020
*
x_PM_SKY130_FD_SC_LP__DLRBP_LP%D N_D_M1014_g N_D_M1027_g N_D_M1006_g N_D_c_196_n
+ N_D_c_197_n D D N_D_c_199_n PM_SKY130_FD_SC_LP__DLRBP_LP%D
diff --git a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.spice b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.spice
index 65e6c4f..8ac57b2 100644
--- a/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.spice
+++ b/cells/dlrbp/sky130_fd_sc_lp__dlrbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrbp_lp.spice
-* Created: Fri Aug 28 10:26:18 2020
+* Created: Wed Sep 2 09:46:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.lvs.report b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.lvs.report
new file mode 100644
index 0000000..67a98ee
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtn_1.sp ('sky130_fd_sc_lp__dlrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.spice ('sky130_fd_sc_lp__dlrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtn_1 sky130_fd_sc_lp__dlrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pex.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pex.spice
index 715c8a2..79c1975 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_1.pex.spice
-* Created: Fri Aug 28 10:26:27 2020
+* Created: Wed Sep 2 09:46:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pxi.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pxi.spice
index b1ad82b..e4d89c2 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_1.pxi.spice
-* Created: Fri Aug 28 10:26:27 2020
+* Created: Wed Sep 2 09:46:50 2020
*
x_PM_SKY130_FD_SC_LP__DLRTN_1%D N_D_M1018_g N_D_c_129_n N_D_M1008_g N_D_c_131_n
+ D D D D N_D_c_133_n N_D_c_134_n PM_SKY130_FD_SC_LP__DLRTN_1%D
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.spice
index 68a1dad..a70fdea 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_1.spice
-* Created: Fri Aug 28 10:26:27 2020
+* Created: Wed Sep 2 09:46:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.lvs.report b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.lvs.report
new file mode 100644
index 0000000..4002b41
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtn_2.sp ('sky130_fd_sc_lp__dlrtn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.spice ('sky130_fd_sc_lp__dlrtn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:46:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtn_2 sky130_fd_sc_lp__dlrtn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pex.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pex.spice
index 4c09fec..da0091f 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_2.pex.spice
-* Created: Fri Aug 28 10:26:34 2020
+* Created: Wed Sep 2 09:46:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pxi.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pxi.spice
index a209180..c380f34 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_2.pxi.spice
-* Created: Fri Aug 28 10:26:34 2020
+* Created: Wed Sep 2 09:46:57 2020
*
x_PM_SKY130_FD_SC_LP__DLRTN_2%D N_D_M1013_g N_D_M1003_g N_D_c_150_n N_D_c_151_n
+ N_D_c_152_n D D D N_D_c_154_n PM_SKY130_FD_SC_LP__DLRTN_2%D
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.spice
index e7e712d..c7c3430 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_2.spice
-* Created: Fri Aug 28 10:26:34 2020
+* Created: Wed Sep 2 09:46:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.lvs.report b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.lvs.report
new file mode 100644
index 0000000..b3cd8c1
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtn_4.sp ('sky130_fd_sc_lp__dlrtn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.spice ('sky130_fd_sc_lp__dlrtn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtn_4 sky130_fd_sc_lp__dlrtn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtn_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pex.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pex.spice
index 85c0827..e02ee8e 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_4.pex.spice
-* Created: Fri Aug 28 10:26:42 2020
+* Created: Wed Sep 2 09:47:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pxi.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pxi.spice
index d433d35..3112a59 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_4.pxi.spice
-* Created: Fri Aug 28 10:26:42 2020
+* Created: Wed Sep 2 09:47:03 2020
*
x_PM_SKY130_FD_SC_LP__DLRTN_4%D N_D_c_161_n N_D_M1022_g N_D_M1016_g N_D_c_163_n
+ D D D N_D_c_165_n N_D_c_166_n PM_SKY130_FD_SC_LP__DLRTN_4%D
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.spice
index 7f0941c..e981c87 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_4.spice
-* Created: Fri Aug 28 10:26:42 2020
+* Created: Wed Sep 2 09:47:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.lvs.report b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.lvs.report
new file mode 100644
index 0000000..6445436
--- /dev/null
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtn_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtn_lp.sp ('sky130_fd_sc_lp__dlrtn_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.spice ('sky130_fd_sc_lp__dlrtn_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtn_lp sky130_fd_sc_lp__dlrtn_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtn_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtn_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 22 22
+
+ Instances: 14 14 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 6 6 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pex.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pex.spice
index 3040ee7..84e05b2 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pex.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_lp.pex.spice
-* Created: Fri Aug 28 10:26:49 2020
+* Created: Wed Sep 2 09:47:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pxi.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pxi.spice
index 48a0fe1..57ca6d8 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pxi.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_lp.pxi.spice
-* Created: Fri Aug 28 10:26:49 2020
+* Created: Wed Sep 2 09:47:10 2020
*
x_PM_SKY130_FD_SC_LP__DLRTN_LP%D N_D_c_157_n N_D_M1003_g N_D_c_158_n N_D_M1000_g
+ N_D_c_159_n N_D_c_160_n N_D_M1019_g N_D_c_161_n N_D_c_162_n D D N_D_c_163_n
diff --git a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.spice b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.spice
index 8414685..f49ddd5 100644
--- a/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.spice
+++ b/cells/dlrtn/sky130_fd_sc_lp__dlrtn_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtn_lp.spice
-* Created: Fri Aug 28 10:26:49 2020
+* Created: Wed Sep 2 09:47:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.lvs.report b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.lvs.report
new file mode 100644
index 0000000..99312b0
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtp_1.sp ('sky130_fd_sc_lp__dlrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.spice ('sky130_fd_sc_lp__dlrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtp_1 sky130_fd_sc_lp__dlrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pex.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pex.spice
index c404cea..27ce971 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_1.pex.spice
-* Created: Fri Aug 28 10:26:57 2020
+* Created: Wed Sep 2 09:47:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pxi.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pxi.spice
index 189bd24..cc5edfa 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_1.pxi.spice
-* Created: Fri Aug 28 10:26:57 2020
+* Created: Wed Sep 2 09:47:17 2020
*
x_PM_SKY130_FD_SC_LP__DLRTP_1%D N_D_c_145_n N_D_M1015_g N_D_M1000_g N_D_c_147_n
+ D D D N_D_c_149_n N_D_c_150_n PM_SKY130_FD_SC_LP__DLRTP_1%D
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.spice
index 80dba8a..219e0f2 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_1.spice
-* Created: Fri Aug 28 10:26:57 2020
+* Created: Wed Sep 2 09:47:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.lvs.report b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.lvs.report
new file mode 100644
index 0000000..bef3073
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtp_2.sp ('sky130_fd_sc_lp__dlrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.spice ('sky130_fd_sc_lp__dlrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtp_2 sky130_fd_sc_lp__dlrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pex.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pex.spice
index 83942f0..1bb6b52 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_2.pex.spice
-* Created: Fri Aug 28 10:27:11 2020
+* Created: Wed Sep 2 09:47:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pxi.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pxi.spice
index 1a87547..6146591 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_2.pxi.spice
-* Created: Fri Aug 28 10:27:11 2020
+* Created: Wed Sep 2 09:47:24 2020
*
x_PM_SKY130_FD_SC_LP__DLRTP_2%D N_D_M1011_g N_D_c_153_n N_D_M1017_g N_D_c_155_n
+ D D D D D N_D_c_159_n N_D_c_160_n D PM_SKY130_FD_SC_LP__DLRTP_2%D
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.spice
index ae8fb83..e82f23b 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_2.spice
-* Created: Fri Aug 28 10:27:11 2020
+* Created: Wed Sep 2 09:47:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.lvs.report b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.lvs.report
new file mode 100644
index 0000000..34de74d
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtp_4.sp ('sky130_fd_sc_lp__dlrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.spice ('sky130_fd_sc_lp__dlrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtp_4 sky130_fd_sc_lp__dlrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pex.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pex.spice
index 23a1c80..485686e 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_4.pex.spice
-* Created: Fri Aug 28 10:27:19 2020
+* Created: Wed Sep 2 09:47:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pxi.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pxi.spice
index 9d082a0..84dce24 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_4.pxi.spice
-* Created: Fri Aug 28 10:27:19 2020
+* Created: Wed Sep 2 09:47:30 2020
*
x_PM_SKY130_FD_SC_LP__DLRTP_4%D N_D_M1001_g N_D_c_170_n N_D_M1006_g N_D_c_172_n
+ D D D D D N_D_c_175_n N_D_c_176_n D PM_SKY130_FD_SC_LP__DLRTP_4%D
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.spice
index 26ce6f1..1f07aa0 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_4.spice
-* Created: Fri Aug 28 10:27:19 2020
+* Created: Wed Sep 2 09:47:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.lvs.report b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.lvs.report
new file mode 100644
index 0000000..bbf25da
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtp_lp.sp ('sky130_fd_sc_lp__dlrtp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.spice ('sky130_fd_sc_lp__dlrtp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtp_lp sky130_fd_sc_lp__dlrtp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 28 28
+
+ Instances: 14 14 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 7 7 SMN2 (4 pins)
+ 8 8 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 7 7 0 0 SMN2
+ 8 8 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE D RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pex.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pex.spice
index c72311a..2294231 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp.pex.spice
-* Created: Fri Aug 28 10:27:37 2020
+* Created: Wed Sep 2 09:47:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pxi.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pxi.spice
index d717675..a72750e 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp.pxi.spice
-* Created: Fri Aug 28 10:27:37 2020
+* Created: Wed Sep 2 09:47:44 2020
*
x_PM_SKY130_FD_SC_LP__DLRTP_LP%GATE N_GATE_M1010_g N_GATE_M1022_g N_GATE_M1001_g
+ N_GATE_M1018_g GATE GATE GATE N_GATE_c_169_n PM_SKY130_FD_SC_LP__DLRTP_LP%GATE
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.spice
index 88ae0eb..e65c745 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp.spice
-* Created: Fri Aug 28 10:27:37 2020
+* Created: Wed Sep 2 09:47:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.lvs.report b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.lvs.report
new file mode 100644
index 0000000..75b8359
--- /dev/null
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlrtp_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlrtp_lp2.sp ('sky130_fd_sc_lp__dlrtp_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.spice ('sky130_fd_sc_lp__dlrtp_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlrtp_lp2 sky130_fd_sc_lp__dlrtp_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlrtp_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlrtp_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 22 22
+
+ Instances: 14 14 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 15 15
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 13 13 0 0
+
+ Instances: 6 6 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 15 15 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pex.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pex.spice
index e1b1197..6e539a8 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pex.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp2.pex.spice
-* Created: Fri Aug 28 10:27:29 2020
+* Created: Wed Sep 2 09:47:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pxi.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pxi.spice
index b8d1bf6..9d4bd31 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pxi.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp2.pxi.spice
-* Created: Fri Aug 28 10:27:29 2020
+* Created: Wed Sep 2 09:47:37 2020
*
x_PM_SKY130_FD_SC_LP__DLRTP_LP2%D N_D_c_156_n N_D_M1016_g N_D_M1022_g
+ N_D_c_157_n N_D_M1004_g N_D_c_158_n N_D_c_159_n D N_D_c_160_n N_D_c_161_n
diff --git a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.spice b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.spice
index 7b507d2..e75803e 100644
--- a/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.spice
+++ b/cells/dlrtp/sky130_fd_sc_lp__dlrtp_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlrtp_lp2.spice
-* Created: Fri Aug 28 10:27:29 2020
+* Created: Wed Sep 2 09:47:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.lvs.report b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.lvs.report
new file mode 100644
index 0000000..7c0be16
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxbn_1.sp ('sky130_fd_sc_lp__dlxbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.spice ('sky130_fd_sc_lp__dlxbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxbn_1 sky130_fd_sc_lp__dlxbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxbn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pex.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pex.spice
index 76e619e..8f7df2a 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_1.pex.spice
-* Created: Fri Aug 28 10:27:45 2020
+* Created: Wed Sep 2 09:47:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pxi.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pxi.spice
index bac3c54..817bb99 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_1.pxi.spice
-* Created: Fri Aug 28 10:27:45 2020
+* Created: Wed Sep 2 09:47:51 2020
*
x_PM_SKY130_FD_SC_LP__DLXBN_1%D N_D_M1012_g N_D_M1015_g N_D_c_145_n N_D_c_146_n
+ N_D_c_151_n D D N_D_c_148_n PM_SKY130_FD_SC_LP__DLXBN_1%D
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.spice
index 325882d..6f379f1 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_1.spice
-* Created: Fri Aug 28 10:27:45 2020
+* Created: Wed Sep 2 09:47:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.lvs.report b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.lvs.report
new file mode 100644
index 0000000..43f7b0a
--- /dev/null
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxbn_2.sp ('sky130_fd_sc_lp__dlxbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.spice ('sky130_fd_sc_lp__dlxbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:47:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxbn_2 sky130_fd_sc_lp__dlxbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxbn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pex.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pex.spice
index 4ef2355..d62d6e1 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pex.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_2.pex.spice
-* Created: Fri Aug 28 10:27:52 2020
+* Created: Wed Sep 2 09:47:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pxi.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pxi.spice
index 755f466..98009f4 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pxi.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_2.pxi.spice
-* Created: Fri Aug 28 10:27:52 2020
+* Created: Wed Sep 2 09:47:57 2020
*
x_PM_SKY130_FD_SC_LP__DLXBN_2%D N_D_M1014_g N_D_M1011_g N_D_c_163_n N_D_c_164_n
+ N_D_c_169_n D D N_D_c_166_n PM_SKY130_FD_SC_LP__DLXBN_2%D
diff --git a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.spice b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.spice
index 6bb0c5f..47ea5ea 100644
--- a/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.spice
+++ b/cells/dlxbn/sky130_fd_sc_lp__dlxbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbn_2.spice
-* Created: Fri Aug 28 10:27:52 2020
+* Created: Wed Sep 2 09:47:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.lvs.report b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.lvs.report
new file mode 100644
index 0000000..5fcd471
--- /dev/null
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxbp_1.sp ('sky130_fd_sc_lp__dlxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.spice ('sky130_fd_sc_lp__dlxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxbp_1 sky130_fd_sc_lp__dlxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pex.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pex.spice
index a6f8868..8ca31c8 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pex.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_1.pex.spice
-* Created: Fri Aug 28 10:28:01 2020
+* Created: Wed Sep 2 09:48:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pxi.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pxi.spice
index b4a116f..2be1439 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pxi.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_1.pxi.spice
-* Created: Fri Aug 28 10:28:01 2020
+* Created: Wed Sep 2 09:48:04 2020
*
x_PM_SKY130_FD_SC_LP__DLXBP_1%D N_D_M1021_g N_D_M1002_g N_D_c_152_n N_D_c_153_n
+ N_D_c_154_n D D N_D_c_156_n PM_SKY130_FD_SC_LP__DLXBP_1%D
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.spice
index 763add9..d97314e 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_1.spice
-* Created: Fri Aug 28 10:28:01 2020
+* Created: Wed Sep 2 09:48:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.lvs.report b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.lvs.report
new file mode 100644
index 0000000..5a91d2c
--- /dev/null
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxbp_lp.sp ('sky130_fd_sc_lp__dlxbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.spice ('sky130_fd_sc_lp__dlxbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxbp_lp sky130_fd_sc_lp__dlxbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 32 32
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 9 9 SMN2 (4 pins)
+ 9 9 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 9 9 0 0 SMN2
+ 9 9 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pex.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pex.spice
index 434bd96..fd9a366 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pex.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp.pex.spice
-* Created: Fri Aug 28 10:28:23 2020
+* Created: Wed Sep 2 09:48:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pxi.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pxi.spice
index 0f15a68..ad2873d 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pxi.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp.pxi.spice
-* Created: Fri Aug 28 10:28:23 2020
+* Created: Wed Sep 2 09:48:17 2020
*
x_PM_SKY130_FD_SC_LP__DLXBP_LP%D N_D_c_187_n N_D_M1032_g N_D_M1021_g N_D_M1028_g
+ N_D_M1010_g N_D_c_185_n D D D N_D_c_186_n PM_SKY130_FD_SC_LP__DLXBP_LP%D
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.spice
index a9883c8..04552a7 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp.spice
-* Created: Fri Aug 28 10:28:23 2020
+* Created: Wed Sep 2 09:48:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.lvs.report b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.lvs.report
new file mode 100644
index 0000000..45bd018
--- /dev/null
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxbp_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxbp_lp2.sp ('sky130_fd_sc_lp__dlxbp_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.spice ('sky130_fd_sc_lp__dlxbp_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxbp_lp2 sky130_fd_sc_lp__dlxbp_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxbp_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxbp_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 25 25
+
+ Instances: 18 18 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 30 29
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pex.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pex.spice
index 06c84e8..3b98755 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pex.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp2.pex.spice
-* Created: Fri Aug 28 10:28:14 2020
+* Created: Wed Sep 2 09:48:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pxi.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pxi.spice
index 6744c4b..6c71e5c 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pxi.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp2.pxi.spice
-* Created: Fri Aug 28 10:28:14 2020
+* Created: Wed Sep 2 09:48:11 2020
*
x_PM_SKY130_FD_SC_LP__DLXBP_LP2%D N_D_M1011_g N_D_M1018_g N_D_M1000_g
+ N_D_c_170_n N_D_c_171_n D D N_D_c_173_n PM_SKY130_FD_SC_LP__DLXBP_LP2%D
diff --git a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.spice b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.spice
index 9904ab6..5e2efa8 100644
--- a/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.spice
+++ b/cells/dlxbp/sky130_fd_sc_lp__dlxbp_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxbp_lp2.spice
-* Created: Fri Aug 28 10:28:14 2020
+* Created: Wed Sep 2 09:48:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.lvs.report b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.lvs.report
new file mode 100644
index 0000000..15c44a3
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtn_1.sp ('sky130_fd_sc_lp__dlxtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.spice ('sky130_fd_sc_lp__dlxtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtn_1 sky130_fd_sc_lp__dlxtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pex.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pex.spice
index be99689..1f099a8 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_1.pex.spice
-* Created: Fri Aug 28 10:28:33 2020
+* Created: Wed Sep 2 09:48:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pxi.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pxi.spice
index 34bc8b2..4237824 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_1.pxi.spice
-* Created: Fri Aug 28 10:28:33 2020
+* Created: Wed Sep 2 09:48:24 2020
*
x_PM_SKY130_FD_SC_LP__DLXTN_1%D N_D_M1009_g N_D_M1001_g D D D N_D_c_131_n
+ N_D_c_132_n PM_SKY130_FD_SC_LP__DLXTN_1%D
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.spice
index 4015fbf..5b568da 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_1.spice
-* Created: Fri Aug 28 10:28:33 2020
+* Created: Wed Sep 2 09:48:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.lvs.report b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.lvs.report
new file mode 100644
index 0000000..0f303be
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtn_2.sp ('sky130_fd_sc_lp__dlxtn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.spice ('sky130_fd_sc_lp__dlxtn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtn_2 sky130_fd_sc_lp__dlxtn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pex.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pex.spice
index 0671462..50a42a3 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_2.pex.spice
-* Created: Fri Aug 28 10:28:41 2020
+* Created: Wed Sep 2 09:48:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pxi.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pxi.spice
index 780b357..3d66c04 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_2.pxi.spice
-* Created: Fri Aug 28 10:28:41 2020
+* Created: Wed Sep 2 09:48:31 2020
*
x_PM_SKY130_FD_SC_LP__DLXTN_2%D N_D_M1007_g N_D_M1010_g D D D N_D_c_140_n
+ N_D_c_141_n PM_SKY130_FD_SC_LP__DLXTN_2%D
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.spice
index f5fb787..51d3e6b 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_2.spice
-* Created: Fri Aug 28 10:28:41 2020
+* Created: Wed Sep 2 09:48:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.lvs.report b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.lvs.report
new file mode 100644
index 0000000..c0d1b07
--- /dev/null
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtn_4.sp ('sky130_fd_sc_lp__dlxtn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.spice ('sky130_fd_sc_lp__dlxtn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtn_4 sky130_fd_sc_lp__dlxtn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtn_4
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pex.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pex.spice
index 9e2abe3..7779188 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pex.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_4.pex.spice
-* Created: Fri Aug 28 10:28:49 2020
+* Created: Wed Sep 2 09:48:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pxi.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pxi.spice
index 57d024d..e3d7b73 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pxi.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_4.pxi.spice
-* Created: Fri Aug 28 10:28:49 2020
+* Created: Wed Sep 2 09:48:37 2020
*
x_PM_SKY130_FD_SC_LP__DLXTN_4%D N_D_M1017_g N_D_M1007_g D D N_D_c_162_n
+ N_D_c_163_n PM_SKY130_FD_SC_LP__DLXTN_4%D
diff --git a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.spice b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.spice
index fe68d67..cce1fe2 100644
--- a/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.spice
+++ b/cells/dlxtn/sky130_fd_sc_lp__dlxtn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtn_4.spice
-* Created: Fri Aug 28 10:28:49 2020
+* Created: Wed Sep 2 09:48:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.lvs.report b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.lvs.report
new file mode 100644
index 0000000..8760646
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtp_1.sp ('sky130_fd_sc_lp__dlxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.spice ('sky130_fd_sc_lp__dlxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtp_1 sky130_fd_sc_lp__dlxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pex.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pex.spice
index 63e6335..48401e9 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_1.pex.spice
-* Created: Fri Aug 28 10:28:56 2020
+* Created: Wed Sep 2 09:48:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pxi.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pxi.spice
index 7e9d1db..0bf9284 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_1.pxi.spice
-* Created: Fri Aug 28 10:28:56 2020
+* Created: Wed Sep 2 09:48:44 2020
*
x_PM_SKY130_FD_SC_LP__DLXTP_1%D N_D_M1007_g N_D_M1008_g N_D_c_120_n N_D_c_121_n
+ N_D_c_122_n D D N_D_c_124_n PM_SKY130_FD_SC_LP__DLXTP_1%D
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.spice
index ad5d248..e824c0b 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_1.spice
-* Created: Fri Aug 28 10:28:56 2020
+* Created: Wed Sep 2 09:48:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.lvs.report b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.lvs.report
new file mode 100644
index 0000000..6e8c695
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtp_lp.sp ('sky130_fd_sc_lp__dlxtp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.spice ('sky130_fd_sc_lp__dlxtp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtp_lp sky130_fd_sc_lp__dlxtp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 26 26
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 7 7 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 SMN2
+ 7 7 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE D VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pex.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pex.spice
index be3f1b9..2eeecae 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp.pex.spice
-* Created: Fri Aug 28 10:29:17 2020
+* Created: Wed Sep 2 09:48:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pxi.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pxi.spice
index 17f7e88..1502686 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp.pxi.spice
-* Created: Fri Aug 28 10:29:17 2020
+* Created: Wed Sep 2 09:48:58 2020
*
x_PM_SKY130_FD_SC_LP__DLXTP_LP%GATE N_GATE_M1010_g N_GATE_M1022_g N_GATE_M1001_g
+ N_GATE_M1000_g GATE GATE N_GATE_c_146_n PM_SKY130_FD_SC_LP__DLXTP_LP%GATE
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.spice
index 29331f3..54a2edd 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp.spice
-* Created: Fri Aug 28 10:29:17 2020
+* Created: Wed Sep 2 09:48:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.lvs.report b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.lvs.report
new file mode 100644
index 0000000..f046287
--- /dev/null
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlxtp_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlxtp_lp2.sp ('sky130_fd_sc_lp__dlxtp_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.spice ('sky130_fd_sc_lp__dlxtp_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:48:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlxtp_lp2 sky130_fd_sc_lp__dlxtp_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlxtp_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlxtp_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 24 23
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 5 5 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 14 14
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 5 5 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 14 14 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pex.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pex.spice
index 209ed0f..de4e565 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pex.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp2.pex.spice
-* Created: Fri Aug 28 10:29:04 2020
+* Created: Wed Sep 2 09:48:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pxi.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pxi.spice
index 923e6a4..c3d4eee 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pxi.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp2.pxi.spice
-* Created: Fri Aug 28 10:29:04 2020
+* Created: Wed Sep 2 09:48:51 2020
*
x_PM_SKY130_FD_SC_LP__DLXTP_LP2%D N_D_c_138_n N_D_M1009_g N_D_M1004_g
+ N_D_M1002_g N_D_c_140_n N_D_c_141_n D D N_D_c_142_n N_D_c_143_n
diff --git a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.spice b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.spice
index c345226..9b8d7ca 100644
--- a/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.spice
+++ b/cells/dlxtp/sky130_fd_sc_lp__dlxtp_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlxtp_lp2.spice
-* Created: Fri Aug 28 10:29:04 2020
+* Created: Wed Sep 2 09:48:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.lvs.report b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.lvs.report
new file mode 100644
index 0000000..06caa5f
--- /dev/null
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s15kapwr_1.sp ('sky130_fd_sc_lp__dlybuf4s15kapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice ('sky130_fd_sc_lp__dlybuf4s15kapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s15kapwr_1 sky130_fd_sc_lp__dlybuf4s15kapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pex.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pex.spice
index 5280984..684924f 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pex.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_1.pex.spice
-* Created: Fri Aug 28 10:29:26 2020
+* Created: Wed Sep 2 09:49:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pxi.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pxi.spice
index 864c429..4203659 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pxi.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_1.pxi.spice
-* Created: Fri Aug 28 10:29:26 2020
+* Created: Wed Sep 2 09:49:04 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S15KAPWR_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_59_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S15KAPWR_1%A
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice
index 4a7dbf8..9107b9a 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_1.spice
-* Created: Fri Aug 28 10:29:26 2020
+* Created: Wed Sep 2 09:49:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.lvs.report b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.lvs.report
new file mode 100644
index 0000000..1da3cff
--- /dev/null
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s15kapwr_2.sp ('sky130_fd_sc_lp__dlybuf4s15kapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice ('sky130_fd_sc_lp__dlybuf4s15kapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s15kapwr_2 sky130_fd_sc_lp__dlybuf4s15kapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s15kapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pex.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pex.spice
index ba31618..1f49acd 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pex.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_2.pex.spice
-* Created: Fri Aug 28 10:29:36 2020
+* Created: Wed Sep 2 09:49:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pxi.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pxi.spice
index b15dd61..37d297e 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pxi.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_2.pxi.spice
-* Created: Fri Aug 28 10:29:36 2020
+* Created: Wed Sep 2 09:49:11 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S15KAPWR_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_63_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S15KAPWR_2%A
diff --git a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice
index 2d334bb..9b1c8b9 100644
--- a/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice
+++ b/cells/dlybuf4s15kapwr/sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s15kapwr_2.spice
-* Created: Fri Aug 28 10:29:36 2020
+* Created: Wed Sep 2 09:49:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.lvs.report b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.lvs.report
new file mode 100644
index 0000000..05279bb
--- /dev/null
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s18kapwr_1.sp ('sky130_fd_sc_lp__dlybuf4s18kapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice ('sky130_fd_sc_lp__dlybuf4s18kapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s18kapwr_1 sky130_fd_sc_lp__dlybuf4s18kapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pex.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pex.spice
index 1c1d660..7e3803b 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pex.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_1.pex.spice
-* Created: Fri Aug 28 10:29:43 2020
+* Created: Wed Sep 2 09:49:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pxi.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pxi.spice
index 354cebe..8be8835 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pxi.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_1.pxi.spice
-* Created: Fri Aug 28 10:29:43 2020
+* Created: Wed Sep 2 09:49:18 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_57_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S18KAPWR_1%A
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice
index 1ff39ec..50d8775 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_1.spice
-* Created: Fri Aug 28 10:29:43 2020
+* Created: Wed Sep 2 09:49:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.lvs.report b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.lvs.report
new file mode 100644
index 0000000..29b80d5
--- /dev/null
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s18kapwr_2.sp ('sky130_fd_sc_lp__dlybuf4s18kapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice ('sky130_fd_sc_lp__dlybuf4s18kapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s18kapwr_2 sky130_fd_sc_lp__dlybuf4s18kapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s18kapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pex.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pex.spice
index c248537..829ceea 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pex.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_2.pex.spice
-* Created: Fri Aug 28 10:29:51 2020
+* Created: Wed Sep 2 09:49:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pxi.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pxi.spice
index c102de3..7b13a0c 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pxi.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_2.pxi.spice
-* Created: Fri Aug 28 10:29:51 2020
+* Created: Wed Sep 2 09:49:24 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S18KAPWR_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_61_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S18KAPWR_2%A
diff --git a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice
index 323e5b9..bb21178 100644
--- a/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice
+++ b/cells/dlybuf4s18kapwr/sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s18kapwr_2.spice
-* Created: Fri Aug 28 10:29:51 2020
+* Created: Wed Sep 2 09:49:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.lvs.report b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.lvs.report
new file mode 100644
index 0000000..2b157ea
--- /dev/null
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s25kapwr_1.sp ('sky130_fd_sc_lp__dlybuf4s25kapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice ('sky130_fd_sc_lp__dlybuf4s25kapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s25kapwr_1 sky130_fd_sc_lp__dlybuf4s25kapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pex.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pex.spice
index fc881f6..3e3c3b3 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pex.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_1.pex.spice
-* Created: Fri Aug 28 10:29:59 2020
+* Created: Wed Sep 2 09:49:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pxi.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pxi.spice
index 8803683..9efe7ff 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pxi.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_1.pxi.spice
-* Created: Fri Aug 28 10:29:59 2020
+* Created: Wed Sep 2 09:49:31 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S25KAPWR_1%A N_A_M1003_g N_A_M1007_g A A N_A_c_57_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S25KAPWR_1%A
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice
index 0e3ebfa..7f7f9b4 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_1.spice
-* Created: Fri Aug 28 10:29:59 2020
+* Created: Wed Sep 2 09:49:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.lvs.report b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.lvs.report
new file mode 100644
index 0000000..45b1840
--- /dev/null
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s25kapwr_2.sp ('sky130_fd_sc_lp__dlybuf4s25kapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice ('sky130_fd_sc_lp__dlybuf4s25kapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s25kapwr_2 sky130_fd_sc_lp__dlybuf4s25kapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s25kapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pex.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pex.spice
index 875faf5..25ca5e4 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pex.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_2.pex.spice
-* Created: Fri Aug 28 10:30:07 2020
+* Created: Wed Sep 2 09:49:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pxi.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pxi.spice
index c40c080..4427915 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pxi.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_2.pxi.spice
-* Created: Fri Aug 28 10:30:07 2020
+* Created: Wed Sep 2 09:49:38 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S25KAPWR_2%A N_A_M1004_g N_A_M1009_g A A N_A_c_61_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S25KAPWR_2%A
diff --git a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice
index 41d9db2..c932028 100644
--- a/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice
+++ b/cells/dlybuf4s25kapwr/sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s25kapwr_2.spice
-* Created: Fri Aug 28 10:30:07 2020
+* Created: Wed Sep 2 09:49:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.lvs.report b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.lvs.report
new file mode 100644
index 0000000..7a8adea
--- /dev/null
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s50kapwr_1.sp ('sky130_fd_sc_lp__dlybuf4s50kapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice ('sky130_fd_sc_lp__dlybuf4s50kapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s50kapwr_1 sky130_fd_sc_lp__dlybuf4s50kapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pex.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pex.spice
index 2679cb4..10e8769 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pex.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_1.pex.spice
-* Created: Fri Aug 28 10:30:20 2020
+* Created: Wed Sep 2 09:49:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pxi.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pxi.spice
index 3be173c..1608399 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pxi.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_1.pxi.spice
-* Created: Fri Aug 28 10:30:20 2020
+* Created: Wed Sep 2 09:49:45 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S50KAPWR_1%A N_A_M1004_g N_A_M1007_g A A N_A_c_56_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S50KAPWR_1%A
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice
index ff1d241..c0caf25 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_1.spice
-* Created: Fri Aug 28 10:30:20 2020
+* Created: Wed Sep 2 09:49:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.lvs.report b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.lvs.report
new file mode 100644
index 0000000..10445ff
--- /dev/null
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlybuf4s50kapwr_2.sp ('sky130_fd_sc_lp__dlybuf4s50kapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice ('sky130_fd_sc_lp__dlybuf4s50kapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlybuf4s50kapwr_2 sky130_fd_sc_lp__dlybuf4s50kapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__dlybuf4s50kapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pex.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pex.spice
index 9790671..1192a0f 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pex.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_2.pex.spice
-* Created: Fri Aug 28 10:30:29 2020
+* Created: Wed Sep 2 09:49:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pxi.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pxi.spice
index e8d7259..cca648b 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pxi.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_2.pxi.spice
-* Created: Fri Aug 28 10:30:29 2020
+* Created: Wed Sep 2 09:49:51 2020
*
x_PM_SKY130_FD_SC_LP__DLYBUF4S50KAPWR_2%A N_A_M1005_g N_A_M1009_g A A N_A_c_60_n
+ PM_SKY130_FD_SC_LP__DLYBUF4S50KAPWR_2%A
diff --git a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice
index 6d70a46..1d96c9c 100644
--- a/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice
+++ b/cells/dlybuf4s50kapwr/sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlybuf4s50kapwr_2.spice
-* Created: Fri Aug 28 10:30:29 2020
+* Created: Wed Sep 2 09:49:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.lvs.report b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.lvs.report
new file mode 100644
index 0000000..908d148
--- /dev/null
+++ b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlygate4s15_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlygate4s15_1.sp ('sky130_fd_sc_lp__dlygate4s15_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.spice ('sky130_fd_sc_lp__dlygate4s15_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:49:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlygate4s15_1 sky130_fd_sc_lp__dlygate4s15_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlygate4s15_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlygate4s15_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pex.spice b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pex.spice
index 0a4f121..542e13c 100644
--- a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pex.spice
+++ b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s15_1.pex.spice
-* Created: Fri Aug 28 10:30:38 2020
+* Created: Wed Sep 2 09:49:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pxi.spice b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pxi.spice
index 637adcc..8a7920b 100644
--- a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pxi.spice
+++ b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s15_1.pxi.spice
-* Created: Fri Aug 28 10:30:38 2020
+* Created: Wed Sep 2 09:49:58 2020
*
x_PM_SKY130_FD_SC_LP__DLYGATE4S15_1%A N_A_M1005_g N_A_M1004_g N_A_c_69_n
+ N_A_c_74_n A A N_A_c_71_n PM_SKY130_FD_SC_LP__DLYGATE4S15_1%A
diff --git a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.spice b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.spice
index a9af41e..e80f925 100644
--- a/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.spice
+++ b/cells/dlygate4s15/sky130_fd_sc_lp__dlygate4s15_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s15_1.spice
-* Created: Fri Aug 28 10:30:38 2020
+* Created: Wed Sep 2 09:49:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.lvs.report b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.lvs.report
new file mode 100644
index 0000000..f0ef853
--- /dev/null
+++ b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlygate4s18_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlygate4s18_1.sp ('sky130_fd_sc_lp__dlygate4s18_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.spice ('sky130_fd_sc_lp__dlygate4s18_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlygate4s18_1 sky130_fd_sc_lp__dlygate4s18_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlygate4s18_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlygate4s18_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pex.spice b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pex.spice
index 81b2131..d984984 100644
--- a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pex.spice
+++ b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s18_1.pex.spice
-* Created: Fri Aug 28 10:30:46 2020
+* Created: Wed Sep 2 09:50:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pxi.spice b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pxi.spice
index 77dd924..eef5c20 100644
--- a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pxi.spice
+++ b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s18_1.pxi.spice
-* Created: Fri Aug 28 10:30:46 2020
+* Created: Wed Sep 2 09:50:04 2020
*
x_PM_SKY130_FD_SC_LP__DLYGATE4S18_1%A N_A_M1005_g N_A_M1003_g N_A_c_67_n
+ N_A_c_72_n A A N_A_c_69_n PM_SKY130_FD_SC_LP__DLYGATE4S18_1%A
diff --git a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.spice b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.spice
index 7712e54..4e0349b 100644
--- a/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.spice
+++ b/cells/dlygate4s18/sky130_fd_sc_lp__dlygate4s18_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s18_1.spice
-* Created: Fri Aug 28 10:30:46 2020
+* Created: Wed Sep 2 09:50:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.lvs.report b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.lvs.report
new file mode 100644
index 0000000..4826eab
--- /dev/null
+++ b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlygate4s50_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlygate4s50_1.sp ('sky130_fd_sc_lp__dlygate4s50_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.spice ('sky130_fd_sc_lp__dlygate4s50_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlygate4s50_1 sky130_fd_sc_lp__dlygate4s50_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlygate4s50_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlygate4s50_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pex.spice b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pex.spice
index c3c36a2..e36ec8a 100644
--- a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pex.spice
+++ b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s50_1.pex.spice
-* Created: Fri Aug 28 10:30:53 2020
+* Created: Wed Sep 2 09:50:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pxi.spice b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pxi.spice
index 7aed3c9..f3f435d 100644
--- a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pxi.spice
+++ b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s50_1.pxi.spice
-* Created: Fri Aug 28 10:30:53 2020
+* Created: Wed Sep 2 09:50:11 2020
*
x_PM_SKY130_FD_SC_LP__DLYGATE4S50_1%A N_A_M1003_g N_A_M1002_g N_A_c_62_n
+ N_A_c_67_n A A N_A_c_64_n PM_SKY130_FD_SC_LP__DLYGATE4S50_1%A
diff --git a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.spice b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.spice
index 7c836f3..e3a9dda 100644
--- a/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.spice
+++ b/cells/dlygate4s50/sky130_fd_sc_lp__dlygate4s50_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlygate4s50_1.spice
-* Created: Fri Aug 28 10:30:53 2020
+* Created: Wed Sep 2 09:50:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.lvs.report b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.lvs.report
new file mode 100644
index 0000000..1dbb6d9
--- /dev/null
+++ b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlymetal6s2s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlymetal6s2s_1.sp ('sky130_fd_sc_lp__dlymetal6s2s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.spice ('sky130_fd_sc_lp__dlymetal6s2s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlymetal6s2s_1 sky130_fd_sc_lp__dlymetal6s2s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlymetal6s2s_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlymetal6s2s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pex.spice b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pex.spice
index b04cec5..ea231b5 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pex.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s2s_1.pex.spice
-* Created: Fri Aug 28 10:31:01 2020
+* Created: Wed Sep 2 09:50:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pxi.spice b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pxi.spice
index 43fc4ae..8afab69 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pxi.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s2s_1.pxi.spice
-* Created: Fri Aug 28 10:31:01 2020
+* Created: Wed Sep 2 09:50:18 2020
*
x_PM_SKY130_FD_SC_LP__DLYMETAL6S2S_1%A N_A_M1008_g N_A_M1010_g A N_A_c_95_n
+ N_A_c_96_n PM_SKY130_FD_SC_LP__DLYMETAL6S2S_1%A
diff --git a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.spice b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.spice
index be677a2..1f1602c 100644
--- a/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.spice
+++ b/cells/dlymetal6s2s/sky130_fd_sc_lp__dlymetal6s2s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s2s_1.spice
-* Created: Fri Aug 28 10:31:01 2020
+* Created: Wed Sep 2 09:50:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.lvs.report b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.lvs.report
new file mode 100644
index 0000000..8441dad
--- /dev/null
+++ b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlymetal6s4s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlymetal6s4s_1.sp ('sky130_fd_sc_lp__dlymetal6s4s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.spice ('sky130_fd_sc_lp__dlymetal6s4s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlymetal6s4s_1 sky130_fd_sc_lp__dlymetal6s4s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlymetal6s4s_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlymetal6s4s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pex.spice b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pex.spice
index 2656524..87c18dd 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pex.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s4s_1.pex.spice
-* Created: Fri Aug 28 10:31:09 2020
+* Created: Wed Sep 2 09:50:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pxi.spice b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pxi.spice
index d490ff6..622b4d3 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pxi.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s4s_1.pxi.spice
-* Created: Fri Aug 28 10:31:09 2020
+* Created: Wed Sep 2 09:50:25 2020
*
x_PM_SKY130_FD_SC_LP__DLYMETAL6S4S_1%A N_A_M1008_g N_A_M1010_g A N_A_c_96_n
+ N_A_c_97_n PM_SKY130_FD_SC_LP__DLYMETAL6S4S_1%A
diff --git a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.spice b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.spice
index 6242cac..1dfc69e 100644
--- a/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.spice
+++ b/cells/dlymetal6s4s/sky130_fd_sc_lp__dlymetal6s4s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s4s_1.spice
-* Created: Fri Aug 28 10:31:09 2020
+* Created: Wed Sep 2 09:50:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.lvs.report b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.lvs.report
new file mode 100644
index 0000000..403e57a
--- /dev/null
+++ b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__dlymetal6s6s_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__dlymetal6s6s_1.sp ('sky130_fd_sc_lp__dlymetal6s6s_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.spice ('sky130_fd_sc_lp__dlymetal6s6s_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__dlymetal6s6s_1 sky130_fd_sc_lp__dlymetal6s6s_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__dlymetal6s6s_1
+SOURCE CELL NAME: sky130_fd_sc_lp__dlymetal6s6s_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pex.spice b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pex.spice
index 316b7a2..a35b258 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pex.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s6s_1.pex.spice
-* Created: Fri Aug 28 10:31:23 2020
+* Created: Wed Sep 2 09:50:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pxi.spice b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pxi.spice
index 09725c2..285d5d8 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pxi.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s6s_1.pxi.spice
-* Created: Fri Aug 28 10:31:23 2020
+* Created: Wed Sep 2 09:50:31 2020
*
x_PM_SKY130_FD_SC_LP__DLYMETAL6S6S_1%A N_A_M1008_g N_A_M1010_g A N_A_c_95_n
+ N_A_c_96_n PM_SKY130_FD_SC_LP__DLYMETAL6S6S_1%A
diff --git a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.spice b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.spice
index 3570f3d..dc6dbf0 100644
--- a/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.spice
+++ b/cells/dlymetal6s6s/sky130_fd_sc_lp__dlymetal6s6s_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__dlymetal6s6s_1.spice
-* Created: Fri Aug 28 10:31:23 2020
+* Created: Wed Sep 2 09:50:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.lvs.report
new file mode 100644
index 0000000..00841a6
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_1.sp ('sky130_fd_sc_lp__ebufn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_1.spice ('sky130_fd_sc_lp__ebufn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_1 sky130_fd_sc_lp__ebufn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pex.spice
index dfe7d08..a2f4daf 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_1.pex.spice
-* Created: Fri Aug 28 10:31:32 2020
+* Created: Wed Sep 2 09:50:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pxi.spice
index 8a7a3db..7661899 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_1.pxi.spice
-* Created: Fri Aug 28 10:31:32 2020
+* Created: Wed Sep 2 09:50:38 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_1%A_105_263# N_A_105_263#_M1005_d
+ N_A_105_263#_M1004_d N_A_105_263#_M1007_g N_A_105_263#_M1003_g
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.spice
index 02be8ed..129653a 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_1.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_1.spice
-* Created: Fri Aug 28 10:31:32 2020
+* Created: Wed Sep 2 09:50:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.lvs.report
new file mode 100644
index 0000000..49dd89e
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_2.sp ('sky130_fd_sc_lp__ebufn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_2.spice ('sky130_fd_sc_lp__ebufn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_2 sky130_fd_sc_lp__ebufn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pex.spice
index edd1d2a..0de6ec7 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_2.pex.spice
-* Created: Fri Aug 28 10:31:41 2020
+* Created: Wed Sep 2 09:50:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pxi.spice
index 09a444e..421f3c1 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_2.pxi.spice
-* Created: Fri Aug 28 10:31:41 2020
+* Created: Wed Sep 2 09:50:45 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_2%A_96_21# N_A_96_21#_M1005_d N_A_96_21#_M1011_d
+ N_A_96_21#_M1001_g N_A_96_21#_M1002_g N_A_96_21#_M1010_g N_A_96_21#_M1009_g
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.spice
index 9c468ee..bb4dc04 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_2.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_2.spice
-* Created: Fri Aug 28 10:31:41 2020
+* Created: Wed Sep 2 09:50:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.lvs.report
new file mode 100644
index 0000000..fb7564f
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_4.sp ('sky130_fd_sc_lp__ebufn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_4.spice ('sky130_fd_sc_lp__ebufn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_4 sky130_fd_sc_lp__ebufn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_4
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pex.spice
index ddd6893..6fe305d 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_4.pex.spice
-* Created: Fri Aug 28 10:31:49 2020
+* Created: Wed Sep 2 09:50:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pxi.spice
index af9ffa7..8ecb579 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_4.pxi.spice
-* Created: Fri Aug 28 10:31:49 2020
+* Created: Wed Sep 2 09:50:51 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_4%A_84_21# N_A_84_21#_M1019_d N_A_84_21#_M1005_d
+ N_A_84_21#_M1000_g N_A_84_21#_M1001_g N_A_84_21#_M1003_g N_A_84_21#_M1006_g
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.spice
index df0b9fe..c789635 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_4.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_4.spice
-* Created: Fri Aug 28 10:31:49 2020
+* Created: Wed Sep 2 09:50:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.lvs.report
new file mode 100644
index 0000000..3d88353
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_8.sp ('sky130_fd_sc_lp__ebufn_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_8.spice ('sky130_fd_sc_lp__ebufn_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:50:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_8 sky130_fd_sc_lp__ebufn_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_8
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 6.
+ 30 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 6.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pex.spice
index 7508b34..6b1e961 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_8.pex.spice
-* Created: Fri Aug 28 10:31:56 2020
+* Created: Wed Sep 2 09:50:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pxi.spice
index eacb262..ab0077d 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_8.pxi.spice
-* Created: Fri Aug 28 10:31:56 2020
+* Created: Wed Sep 2 09:50:58 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_8%A_84_21# N_A_84_21#_M1008_s N_A_84_21#_M1019_s
+ N_A_84_21#_M1003_g N_A_84_21#_M1006_g N_A_84_21#_M1005_g N_A_84_21#_M1011_g
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.spice
index ac6817d..7cf3134 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_8.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_8.spice
-* Created: Fri Aug 28 10:31:56 2020
+* Created: Wed Sep 2 09:50:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.lvs.report
new file mode 100644
index 0000000..e80db1e
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_lp.sp ('sky130_fd_sc_lp__ebufn_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.spice ('sky130_fd_sc_lp__ebufn_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_lp sky130_fd_sc_lp__ebufn_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE_B VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pex.spice
index c0c47b2..374ed58 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp.pex.spice
-* Created: Fri Aug 28 10:32:11 2020
+* Created: Wed Sep 2 09:51:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pxi.spice
index e031b62..0d11086 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp.pxi.spice
-* Created: Fri Aug 28 10:32:11 2020
+* Created: Wed Sep 2 09:51:11 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_LP%A N_A_M1010_g N_A_M1004_g N_A_M1000_g N_A_M1001_g
+ A A N_A_c_75_n N_A_c_76_n PM_SKY130_FD_SC_LP__EBUFN_LP%A
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.spice
index 65a9e2d..bbb39ce 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp.spice
-* Created: Fri Aug 28 10:32:11 2020
+* Created: Wed Sep 2 09:51:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.lvs.report b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.lvs.report
new file mode 100644
index 0000000..8c2685a
--- /dev/null
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ebufn_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ebufn_lp2.sp ('sky130_fd_sc_lp__ebufn_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.spice ('sky130_fd_sc_lp__ebufn_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ebufn_lp2 sky130_fd_sc_lp__ebufn_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ebufn_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__ebufn_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE_B VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pex.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pex.spice
index de069c7..35c1b85 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pex.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp2.pex.spice
-* Created: Fri Aug 28 10:32:03 2020
+* Created: Wed Sep 2 09:51:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pxi.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pxi.spice
index a23dd0b..f3ff4ac 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pxi.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp2.pxi.spice
-* Created: Fri Aug 28 10:32:03 2020
+* Created: Wed Sep 2 09:51:05 2020
*
x_PM_SKY130_FD_SC_LP__EBUFN_LP2%A N_A_c_69_n N_A_M1001_g N_A_M1000_g N_A_M1007_g
+ N_A_c_71_n N_A_c_72_n A A A N_A_c_74_n PM_SKY130_FD_SC_LP__EBUFN_LP2%A
diff --git a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.spice b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.spice
index 94a5f9c..6764a3b 100644
--- a/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.spice
+++ b/cells/ebufn/sky130_fd_sc_lp__ebufn_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ebufn_lp2.spice
-* Created: Fri Aug 28 10:32:03 2020
+* Created: Wed Sep 2 09:51:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.lvs.report b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.lvs.report
new file mode 100644
index 0000000..e93748d
--- /dev/null
+++ b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__edfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__edfxbp_1.sp ('sky130_fd_sc_lp__edfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.spice ('sky130_fd_sc_lp__edfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__edfxbp_1 sky130_fd_sc_lp__edfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__edfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__edfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 27 27
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 26 26
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 26 26 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB DE D CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pex.spice b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pex.spice
index fdf41db..4df5c72 100644
--- a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pex.spice
+++ b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__edfxbp_1.pex.spice
-* Created: Fri Aug 28 10:32:25 2020
+* Created: Wed Sep 2 09:51:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pxi.spice b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pxi.spice
index d7b694f..d8edbaf 100644
--- a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pxi.spice
+++ b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__edfxbp_1.pxi.spice
-* Created: Fri Aug 28 10:32:25 2020
+* Created: Wed Sep 2 09:51:18 2020
*
x_PM_SKY130_FD_SC_LP__EDFXBP_1%DE N_DE_M1007_g N_DE_M1001_g N_DE_c_272_n
+ N_DE_M1022_g N_DE_c_274_n N_DE_M1005_g N_DE_c_275_n N_DE_c_276_n DE DE DE
diff --git a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.spice b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.spice
index f542bcb..8a34986 100644
--- a/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.spice
+++ b/cells/edfxbp/sky130_fd_sc_lp__edfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__edfxbp_1.spice
-* Created: Fri Aug 28 10:32:25 2020
+* Created: Wed Sep 2 09:51:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_0.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_0.lvs.report
new file mode 100644
index 0000000..b23e03e
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_0.sp ('sky130_fd_sc_lp__einvn_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_0.spice ('sky130_fd_sc_lp__einvn_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_0 sky130_fd_sc_lp__einvn_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_0
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_0.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_0.pex.spice
index 9e6eb43..c6a856e 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_0.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_0.pex.spice
-* Created: Fri Aug 28 10:32:33 2020
+* Created: Wed Sep 2 09:51:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_0.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_0.pxi.spice
index 0ecf619..3636a1c 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_0.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_0.pxi.spice
-* Created: Fri Aug 28 10:32:33 2020
+* Created: Wed Sep 2 09:51:25 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_0%A_28_141# N_A_28_141#_M1004_s N_A_28_141#_M1001_s
+ N_A_28_141#_c_35_n N_A_28_141#_M1005_g N_A_28_141#_c_36_n N_A_28_141#_c_37_n
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_0.spice b/cells/einvn/sky130_fd_sc_lp__einvn_0.spice
index fec369d..3540aad 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_0.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_0.spice
-* Created: Fri Aug 28 10:32:33 2020
+* Created: Wed Sep 2 09:51:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_1.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_1.lvs.report
new file mode 100644
index 0000000..f6fa8ec
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_1.sp ('sky130_fd_sc_lp__einvn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_1.spice ('sky130_fd_sc_lp__einvn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_1 sky130_fd_sc_lp__einvn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE_B Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_1.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_1.pex.spice
index be2fb26..a3abc14 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_1.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_1.pex.spice
-* Created: Fri Aug 28 10:32:42 2020
+* Created: Wed Sep 2 09:51:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_1.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_1.pxi.spice
index f881b6b..828916a 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_1.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_1.pxi.spice
-* Created: Fri Aug 28 10:32:42 2020
+* Created: Wed Sep 2 09:51:32 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_1%A N_A_M1000_g N_A_M1004_g A A N_A_c_46_n
+ N_A_c_47_n PM_SKY130_FD_SC_LP__EINVN_1%A
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_1.spice b/cells/einvn/sky130_fd_sc_lp__einvn_1.spice
index 5624ea5..2ec3cf5 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_1.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_1.spice
-* Created: Fri Aug 28 10:32:42 2020
+* Created: Wed Sep 2 09:51:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_2.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_2.lvs.report
new file mode 100644
index 0000000..2132a3c
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_2.sp ('sky130_fd_sc_lp__einvn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_2.spice ('sky130_fd_sc_lp__einvn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_2 sky130_fd_sc_lp__einvn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_2.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_2.pex.spice
index 6bee0d5..9903ec9 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_2.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_2.pex.spice
-* Created: Fri Aug 28 10:32:50 2020
+* Created: Wed Sep 2 09:51:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_2.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_2.pxi.spice
index d4bb660..5f5e281 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_2.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_2.pxi.spice
-* Created: Fri Aug 28 10:32:50 2020
+* Created: Wed Sep 2 09:51:39 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_2%TE_B N_TE_B_M1002_g N_TE_B_c_61_n N_TE_B_c_67_n
+ N_TE_B_M1006_g N_TE_B_c_68_n N_TE_B_M1007_g N_TE_B_c_62_n N_TE_B_c_63_n
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_2.spice b/cells/einvn/sky130_fd_sc_lp__einvn_2.spice
index 9f7c56b..320b271 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_2.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_2.spice
-* Created: Fri Aug 28 10:32:50 2020
+* Created: Wed Sep 2 09:51:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_4.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_4.lvs.report
new file mode 100644
index 0000000..5026b17
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_4.sp ('sky130_fd_sc_lp__einvn_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_4.spice ('sky130_fd_sc_lp__einvn_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_4 sky130_fd_sc_lp__einvn_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_4
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE_B Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_4.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_4.pex.spice
index 93f189c..126f2e0 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_4.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_4.pex.spice
-* Created: Fri Aug 28 10:32:57 2020
+* Created: Wed Sep 2 09:51:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_4.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_4.pxi.spice
index 3f15e7d..a47b38d 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_4.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_4.pxi.spice
-* Created: Fri Aug 28 10:32:57 2020
+* Created: Wed Sep 2 09:51:46 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_4%A N_A_c_109_n N_A_M1002_g N_A_M1000_g N_A_c_110_n
+ N_A_M1003_g N_A_M1001_g N_A_M1004_g N_A_M1010_g N_A_c_112_n N_A_c_113_n
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_4.spice b/cells/einvn/sky130_fd_sc_lp__einvn_4.spice
index 1174dec..331a05f 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_4.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_4.spice
-* Created: Fri Aug 28 10:32:57 2020
+* Created: Wed Sep 2 09:51:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_8.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_8.lvs.report
new file mode 100644
index 0000000..d689e05
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_8.sp ('sky130_fd_sc_lp__einvn_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_8.spice ('sky130_fd_sc_lp__einvn_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_8 sky130_fd_sc_lp__einvn_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_8
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_8.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_8.pex.spice
index f8ef49f..3e80928 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_8.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_8.pex.spice
-* Created: Fri Aug 28 10:33:04 2020
+* Created: Wed Sep 2 09:51:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_8.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_8.pxi.spice
index f5ff844..d8cc5c9 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_8.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_8.pxi.spice
-* Created: Fri Aug 28 10:33:04 2020
+* Created: Wed Sep 2 09:51:52 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_8%A_110_57# N_A_110_57#_M1023_d N_A_110_57#_M1010_d
+ N_A_110_57#_c_159_n N_A_110_57#_c_160_n N_A_110_57#_c_161_n
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_8.spice b/cells/einvn/sky130_fd_sc_lp__einvn_8.spice
index 774345c..ac2487c 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_8.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_8.spice
-* Created: Fri Aug 28 10:33:04 2020
+* Created: Wed Sep 2 09:51:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_lp.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_lp.lvs.report
new file mode 100644
index 0000000..8d48ffd
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_lp.sp ('sky130_fd_sc_lp__einvn_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_lp.spice ('sky130_fd_sc_lp__einvn_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:51:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_lp sky130_fd_sc_lp__einvn_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_lp.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_lp.pex.spice
index aca2101..9e7c602 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_lp.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_lp.pex.spice
-* Created: Fri Aug 28 10:33:12 2020
+* Created: Wed Sep 2 09:51:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_lp.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_lp.pxi.spice
index 502e4c0..ece20cb 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_lp.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_lp.pxi.spice
-* Created: Fri Aug 28 10:33:12 2020
+* Created: Wed Sep 2 09:51:59 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_LP%TE_B N_TE_B_M1003_g N_TE_B_c_40_n N_TE_B_M1004_g
+ N_TE_B_M1001_g N_TE_B_c_41_n N_TE_B_M1002_g TE_B N_TE_B_c_38_n N_TE_B_c_39_n
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_lp.spice b/cells/einvn/sky130_fd_sc_lp__einvn_lp.spice
index d46378d..e2b0fb2 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_lp.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_lp.spice
-* Created: Fri Aug 28 10:33:12 2020
+* Created: Wed Sep 2 09:51:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_m.lvs.report b/cells/einvn/sky130_fd_sc_lp__einvn_m.lvs.report
new file mode 100644
index 0000000..1650b55
--- /dev/null
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvn_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvn_m.sp ('sky130_fd_sc_lp__einvn_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvn/sky130_fd_sc_lp__einvn_m.spice ('sky130_fd_sc_lp__einvn_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvn_m sky130_fd_sc_lp__einvn_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvn_m
+SOURCE CELL NAME: sky130_fd_sc_lp__einvn_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE_B A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_m.pex.spice b/cells/einvn/sky130_fd_sc_lp__einvn_m.pex.spice
index 8e273f2..7978134 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_m.pex.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_m.pex.spice
-* Created: Fri Aug 28 10:33:26 2020
+* Created: Wed Sep 2 09:52:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_m.pxi.spice b/cells/einvn/sky130_fd_sc_lp__einvn_m.pxi.spice
index 2141749..271c216 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_m.pxi.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_m.pxi.spice
-* Created: Fri Aug 28 10:33:26 2020
+* Created: Wed Sep 2 09:52:06 2020
*
x_PM_SKY130_FD_SC_LP__EINVN_M%TE_B N_TE_B_M1004_g N_TE_B_c_43_n N_TE_B_M1002_g
+ N_TE_B_c_44_n N_TE_B_c_45_n N_TE_B_M1005_g N_TE_B_c_46_n TE_B TE_B
diff --git a/cells/einvn/sky130_fd_sc_lp__einvn_m.spice b/cells/einvn/sky130_fd_sc_lp__einvn_m.spice
index 7448dca..5acdd3a 100644
--- a/cells/einvn/sky130_fd_sc_lp__einvn_m.spice
+++ b/cells/einvn/sky130_fd_sc_lp__einvn_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvn_m.spice
-* Created: Fri Aug 28 10:33:26 2020
+* Created: Wed Sep 2 09:52:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_0.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_0.lvs.report
new file mode 100644
index 0000000..bedbf4a
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_0.sp ('sky130_fd_sc_lp__einvp_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_0.spice ('sky130_fd_sc_lp__einvp_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_0 sky130_fd_sc_lp__einvp_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_0
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_0.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_0.pex.spice
index f1d3380..36679fd 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_0.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_0.pex.spice
-* Created: Fri Aug 28 10:33:35 2020
+* Created: Wed Sep 2 09:52:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_0.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_0.pxi.spice
index 5a1df7a..4fefa83 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_0.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_0.pxi.spice
-* Created: Fri Aug 28 10:33:35 2020
+* Created: Wed Sep 2 09:52:14 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_0%TE N_TE_c_38_n N_TE_M1003_g N_TE_M1000_g
+ N_TE_M1004_g N_TE_c_40_n N_TE_c_41_n TE TE TE N_TE_c_43_n
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_0.spice b/cells/einvp/sky130_fd_sc_lp__einvp_0.spice
index 75d31e6..2e034f3 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_0.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_0.spice
-* Created: Fri Aug 28 10:33:35 2020
+* Created: Wed Sep 2 09:52:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_1.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_1.lvs.report
new file mode 100644
index 0000000..6147ee2
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_1.sp ('sky130_fd_sc_lp__einvp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_1.spice ('sky130_fd_sc_lp__einvp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_1 sky130_fd_sc_lp__einvp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_1.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_1.pex.spice
index 6b65eb1..2b663b2 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_1.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_1.pex.spice
-* Created: Fri Aug 28 10:33:44 2020
+* Created: Wed Sep 2 09:52:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_1.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_1.pxi.spice
index 096c8f4..a8da747 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_1.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_1.pxi.spice
-* Created: Fri Aug 28 10:33:44 2020
+* Created: Wed Sep 2 09:52:21 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_1%A N_A_M1003_g N_A_M1005_g A A N_A_c_43_n
+ PM_SKY130_FD_SC_LP__EINVP_1%A
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_1.spice b/cells/einvp/sky130_fd_sc_lp__einvp_1.spice
index 8164d78..77b2343 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_1.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_1.spice
-* Created: Fri Aug 28 10:33:44 2020
+* Created: Wed Sep 2 09:52:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_2.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_2.lvs.report
new file mode 100644
index 0000000..c6eae79
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_2.sp ('sky130_fd_sc_lp__einvp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_2.spice ('sky130_fd_sc_lp__einvp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_2 sky130_fd_sc_lp__einvp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_2.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_2.pex.spice
index 202c15f..5497492 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_2.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_2.pex.spice
-* Created: Fri Aug 28 10:33:51 2020
+* Created: Wed Sep 2 09:52:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_2.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_2.pxi.spice
index b16f1e6..4edf754 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_2.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_2.pxi.spice
-* Created: Fri Aug 28 10:33:51 2020
+* Created: Wed Sep 2 09:52:28 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_2%TE N_TE_M1000_g N_TE_M1006_g N_TE_c_65_n
+ N_TE_c_73_n N_TE_c_66_n N_TE_M1004_g N_TE_c_67_n N_TE_c_68_n N_TE_c_69_n
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_2.spice b/cells/einvp/sky130_fd_sc_lp__einvp_2.spice
index 4f8e634..f18833e 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_2.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_2.spice
-* Created: Fri Aug 28 10:33:51 2020
+* Created: Wed Sep 2 09:52:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_4.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_4.lvs.report
new file mode 100644
index 0000000..62e59dc
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_4.sp ('sky130_fd_sc_lp__einvp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_4.spice ('sky130_fd_sc_lp__einvp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_4 sky130_fd_sc_lp__einvp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_4.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_4.pex.spice
index 17e05e4..c29da8d 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_4.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_4.pex.spice
-* Created: Fri Aug 28 10:33:58 2020
+* Created: Wed Sep 2 09:52:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_4.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_4.pxi.spice
index 2ed9875..2e46f20 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_4.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_4.pxi.spice
-* Created: Fri Aug 28 10:33:58 2020
+* Created: Wed Sep 2 09:52:35 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_4%TE N_TE_c_106_n N_TE_M1016_g N_TE_M1004_g
+ N_TE_c_108_n N_TE_c_109_n N_TE_M1005_g N_TE_c_110_n N_TE_c_111_n N_TE_M1006_g
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_4.spice b/cells/einvp/sky130_fd_sc_lp__einvp_4.spice
index b449827..2551701 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_4.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_4.spice
-* Created: Fri Aug 28 10:33:58 2020
+* Created: Wed Sep 2 09:52:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_8.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_8.lvs.report
new file mode 100644
index 0000000..5ab0800
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_8.sp ('sky130_fd_sc_lp__einvp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_8.spice ('sky130_fd_sc_lp__einvp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_8 sky130_fd_sc_lp__einvp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_8
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_8.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_8.pex.spice
index ceec4f7..d8517cd 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_8.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_8.pex.spice
-* Created: Fri Aug 28 10:34:06 2020
+* Created: Wed Sep 2 09:52:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_8.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_8.pxi.spice
index 1a9a0c3..390728b 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_8.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_8.pxi.spice
-* Created: Fri Aug 28 10:34:06 2020
+* Created: Wed Sep 2 09:52:42 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_8%A_182_367# N_A_182_367#_M1027_d
+ N_A_182_367#_M1026_d N_A_182_367#_c_175_n N_A_182_367#_c_176_n
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_8.spice b/cells/einvp/sky130_fd_sc_lp__einvp_8.spice
index 5123869..5e5323a 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_8.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_8.spice
-* Created: Fri Aug 28 10:34:06 2020
+* Created: Wed Sep 2 09:52:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_lp.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_lp.lvs.report
new file mode 100644
index 0000000..d44dd96
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_lp.sp ('sky130_fd_sc_lp__einvp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_lp.spice ('sky130_fd_sc_lp__einvp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_lp sky130_fd_sc_lp__einvp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A TE Z VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_lp.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_lp.pex.spice
index ff275e2..7781a03 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_lp.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_lp.pex.spice
-* Created: Fri Aug 28 10:34:14 2020
+* Created: Wed Sep 2 09:52:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_lp.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_lp.pxi.spice
index e14d30b..fe4b11d 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_lp.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_lp.pxi.spice
-* Created: Fri Aug 28 10:34:14 2020
+* Created: Wed Sep 2 09:52:49 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_LP%A N_A_c_40_n N_A_M1006_g N_A_M1005_g A A
+ N_A_c_44_n PM_SKY130_FD_SC_LP__EINVP_LP%A
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_lp.spice b/cells/einvp/sky130_fd_sc_lp__einvp_lp.spice
index f6786e3..4466cb1 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_lp.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_lp.spice
-* Created: Fri Aug 28 10:34:14 2020
+* Created: Wed Sep 2 09:52:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_m.lvs.report b/cells/einvp/sky130_fd_sc_lp__einvp_m.lvs.report
new file mode 100644
index 0000000..ac9cfad
--- /dev/null
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__einvp_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__einvp_m.sp ('sky130_fd_sc_lp__einvp_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/einvp/sky130_fd_sc_lp__einvp_m.spice ('sky130_fd_sc_lp__einvp_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__einvp_m sky130_fd_sc_lp__einvp_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__einvp_m
+SOURCE CELL NAME: sky130_fd_sc_lp__einvp_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB TE A VPWR Z VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_m.pex.spice b/cells/einvp/sky130_fd_sc_lp__einvp_m.pex.spice
index 6ebaf1d..eb1c1c5 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_m.pex.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_m.pex.spice
-* Created: Fri Aug 28 10:34:27 2020
+* Created: Wed Sep 2 09:52:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_m.pxi.spice b/cells/einvp/sky130_fd_sc_lp__einvp_m.pxi.spice
index 8b1958a..5f06fb3 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_m.pxi.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_m.pxi.spice
-* Created: Fri Aug 28 10:34:27 2020
+* Created: Wed Sep 2 09:52:56 2020
*
x_PM_SKY130_FD_SC_LP__EINVP_M%TE N_TE_c_40_n N_TE_M1001_g N_TE_c_48_n
+ N_TE_M1005_g N_TE_c_42_n N_TE_c_43_n N_TE_M1004_g N_TE_c_44_n N_TE_c_49_n TE
diff --git a/cells/einvp/sky130_fd_sc_lp__einvp_m.spice b/cells/einvp/sky130_fd_sc_lp__einvp_m.spice
index 21ce407..4398b40 100644
--- a/cells/einvp/sky130_fd_sc_lp__einvp_m.spice
+++ b/cells/einvp/sky130_fd_sc_lp__einvp_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__einvp_m.spice
-* Created: Fri Aug 28 10:34:27 2020
+* Created: Wed Sep 2 09:52:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_0.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_0.lvs.report
new file mode 100644
index 0000000..30c82b6
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_0.lvs.report
@@ -0,0 +1,480 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_0.sp ('sky130_fd_sc_lp__fa_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_0.spice ('sky130_fd_sc_lp__fa_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:52:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_0 sky130_fd_sc_lp__fa_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_0
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CIN COUT VPWR SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_0.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_0.pex.spice
index 87f2110..40dd1ce 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_0.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_0.pex.spice
-* Created: Fri Aug 28 10:34:35 2020
+* Created: Wed Sep 2 09:53:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_0.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_0.pxi.spice
index 27acbe8..90c5a99 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_0.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_0.pxi.spice
-* Created: Fri Aug 28 10:34:35 2020
+* Created: Wed Sep 2 09:53:03 2020
*
x_PM_SKY130_FD_SC_LP__FA_0%A N_A_M1010_g N_A_M1003_g N_A_c_162_n N_A_c_163_n
+ N_A_M1016_g N_A_M1023_g N_A_c_164_n N_A_c_165_n N_A_c_166_n N_A_c_167_n
diff --git a/cells/fa/sky130_fd_sc_lp__fa_0.spice b/cells/fa/sky130_fd_sc_lp__fa_0.spice
index d2d7aaf..aa9931a 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_0.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_0.spice
-* Created: Fri Aug 28 10:34:35 2020
+* Created: Wed Sep 2 09:53:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_1.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_1.lvs.report
new file mode 100644
index 0000000..a915d4f
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_1.lvs.report
@@ -0,0 +1,480 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_1.sp ('sky130_fd_sc_lp__fa_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_1.spice ('sky130_fd_sc_lp__fa_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_1 sky130_fd_sc_lp__fa_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_1
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CIN COUT VPWR SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_1.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_1.pex.spice
index 50b7a64..281237b 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_1.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_1.pex.spice
-* Created: Fri Aug 28 10:34:45 2020
+* Created: Wed Sep 2 09:53:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_1.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_1.pxi.spice
index 0579ad9..ad8458f 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_1.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_1.pxi.spice
-* Created: Fri Aug 28 10:34:45 2020
+* Created: Wed Sep 2 09:53:09 2020
*
x_PM_SKY130_FD_SC_LP__FA_1%A_80_27# N_A_80_27#_M1026_d N_A_80_27#_M1008_d
+ N_A_80_27#_M1016_g N_A_80_27#_M1017_g N_A_80_27#_M1018_g N_A_80_27#_M1025_g
diff --git a/cells/fa/sky130_fd_sc_lp__fa_1.spice b/cells/fa/sky130_fd_sc_lp__fa_1.spice
index e94136f..c7aed4e 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_1.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_1.spice
-* Created: Fri Aug 28 10:34:45 2020
+* Created: Wed Sep 2 09:53:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_2.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_2.lvs.report
new file mode 100644
index 0000000..4b79775
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_2.lvs.report
@@ -0,0 +1,485 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_2.sp ('sky130_fd_sc_lp__fa_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_2.spice ('sky130_fd_sc_lp__fa_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_2 sky130_fd_sc_lp__fa_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_2
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A CIN B VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_2.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_2.pex.spice
index d36622d..975b9f8 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_2.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_2.pex.spice
-* Created: Fri Aug 28 10:34:52 2020
+* Created: Wed Sep 2 09:53:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_2.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_2.pxi.spice
index 6e78b96..9960087 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_2.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_2.pxi.spice
-* Created: Fri Aug 28 10:34:52 2020
+* Created: Wed Sep 2 09:53:16 2020
*
x_PM_SKY130_FD_SC_LP__FA_2%A_84_21# N_A_84_21#_M1019_d N_A_84_21#_M1017_d
+ N_A_84_21#_M1007_g N_A_84_21#_M1020_g N_A_84_21#_c_177_n N_A_84_21#_M1008_g
diff --git a/cells/fa/sky130_fd_sc_lp__fa_2.spice b/cells/fa/sky130_fd_sc_lp__fa_2.spice
index e77bb98..0c7b6f7 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_2.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_2.spice
-* Created: Fri Aug 28 10:34:52 2020
+* Created: Wed Sep 2 09:53:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_4.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_4.lvs.report
new file mode 100644
index 0000000..e904f0d
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_4.lvs.report
@@ -0,0 +1,485 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_4.sp ('sky130_fd_sc_lp__fa_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_4.spice ('sky130_fd_sc_lp__fa_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_4 sky130_fd_sc_lp__fa_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_4
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A CIN B VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_4.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_4.pex.spice
index 457f131..43fac12 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_4.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_4.pex.spice
-* Created: Fri Aug 28 10:35:00 2020
+* Created: Wed Sep 2 09:53:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_4.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_4.pxi.spice
index 8b665e3..c637dd3 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_4.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_4.pxi.spice
-* Created: Fri Aug 28 10:35:00 2020
+* Created: Wed Sep 2 09:53:23 2020
*
x_PM_SKY130_FD_SC_LP__FA_4%A N_A_c_190_n N_A_M1038_g N_A_M1030_g N_A_M1016_g
+ N_A_M1006_g N_A_M1035_g N_A_M1031_g N_A_M1003_g N_A_M1029_g N_A_c_211_n
diff --git a/cells/fa/sky130_fd_sc_lp__fa_4.spice b/cells/fa/sky130_fd_sc_lp__fa_4.spice
index 4ccf766..044932f 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_4.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_4.spice
-* Created: Fri Aug 28 10:35:00 2020
+* Created: Wed Sep 2 09:53:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_lp.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_lp.lvs.report
new file mode 100644
index 0000000..723ebe3
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_lp.lvs.report
@@ -0,0 +1,478 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_lp.sp ('sky130_fd_sc_lp__fa_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_lp.spice ('sky130_fd_sc_lp__fa_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_lp sky130_fd_sc_lp__fa_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 23 23
+
+ Instances: 16 16 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 31 30
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B CIN A COUT VPWR SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_lp.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_lp.pex.spice
index 6e42835..802308f 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_lp.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_lp.pex.spice
-* Created: Fri Aug 28 10:35:07 2020
+* Created: Wed Sep 2 09:53:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_lp.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_lp.pxi.spice
index 16fa35f..56b85e0 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_lp.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_lp.pxi.spice
-* Created: Fri Aug 28 10:35:07 2020
+* Created: Wed Sep 2 09:53:29 2020
*
x_PM_SKY130_FD_SC_LP__FA_LP%A_84_209# N_A_84_209#_M1007_d N_A_84_209#_M1011_d
+ N_A_84_209#_M1014_g N_A_84_209#_M1018_g N_A_84_209#_M1005_g
diff --git a/cells/fa/sky130_fd_sc_lp__fa_lp.spice b/cells/fa/sky130_fd_sc_lp__fa_lp.spice
index 42dc8f3..2cc4086 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_lp.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_lp.spice
-* Created: Fri Aug 28 10:35:07 2020
+* Created: Wed Sep 2 09:53:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fa/sky130_fd_sc_lp__fa_m.lvs.report b/cells/fa/sky130_fd_sc_lp__fa_m.lvs.report
new file mode 100644
index 0000000..07c7cc1
--- /dev/null
+++ b/cells/fa/sky130_fd_sc_lp__fa_m.lvs.report
@@ -0,0 +1,480 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fa_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fa_m.sp ('sky130_fd_sc_lp__fa_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fa/sky130_fd_sc_lp__fa_m.spice ('sky130_fd_sc_lp__fa_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fa_m sky130_fd_sc_lp__fa_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fa_m
+SOURCE CELL NAME: sky130_fd_sc_lp__fa_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 21 21
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ 1 1 SPMP_3_1 (6 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1
+ 1 1 0 0 SPMN_3_1
+ 1 1 0 0 SPMP_2_1
+ 1 1 0 0 SPMP_3_1
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B CIN A COUT VPWR SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fa/sky130_fd_sc_lp__fa_m.pex.spice b/cells/fa/sky130_fd_sc_lp__fa_m.pex.spice
index c9653a1..7d1b85a 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_m.pex.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_m.pex.spice
-* Created: Fri Aug 28 10:35:15 2020
+* Created: Wed Sep 2 09:53:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fa/sky130_fd_sc_lp__fa_m.pxi.spice b/cells/fa/sky130_fd_sc_lp__fa_m.pxi.spice
index 74135f4..30a2cf1 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_m.pxi.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_m.pxi.spice
-* Created: Fri Aug 28 10:35:15 2020
+* Created: Wed Sep 2 09:53:36 2020
*
x_PM_SKY130_FD_SC_LP__FA_M%A_80_241# N_A_80_241#_M1007_d N_A_80_241#_M1005_d
+ N_A_80_241#_M1024_g N_A_80_241#_M1021_g N_A_80_241#_M1027_g
diff --git a/cells/fa/sky130_fd_sc_lp__fa_m.spice b/cells/fa/sky130_fd_sc_lp__fa_m.spice
index 3da7ace..07254e2 100644
--- a/cells/fa/sky130_fd_sc_lp__fa_m.spice
+++ b/cells/fa/sky130_fd_sc_lp__fa_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fa_m.spice
-* Created: Fri Aug 28 10:35:15 2020
+* Created: Wed Sep 2 09:53:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fah/sky130_fd_sc_lp__fah_1.lvs.report b/cells/fah/sky130_fd_sc_lp__fah_1.lvs.report
new file mode 100644
index 0000000..b3d6066
--- /dev/null
+++ b/cells/fah/sky130_fd_sc_lp__fah_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fah_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fah_1.sp ('sky130_fd_sc_lp__fah_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fah/sky130_fd_sc_lp__fah_1.spice ('sky130_fd_sc_lp__fah_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fah_1 sky130_fd_sc_lp__fah_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fah_1
+SOURCE CELL NAME: sky130_fd_sc_lp__fah_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB CI B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fah/sky130_fd_sc_lp__fah_1.pex.spice b/cells/fah/sky130_fd_sc_lp__fah_1.pex.spice
index b3b4f2e..2711bb2 100644
--- a/cells/fah/sky130_fd_sc_lp__fah_1.pex.spice
+++ b/cells/fah/sky130_fd_sc_lp__fah_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fah_1.pex.spice
-* Created: Fri Aug 28 10:35:28 2020
+* Created: Wed Sep 2 09:53:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fah/sky130_fd_sc_lp__fah_1.pxi.spice b/cells/fah/sky130_fd_sc_lp__fah_1.pxi.spice
index 01f798a..8b17a2a 100644
--- a/cells/fah/sky130_fd_sc_lp__fah_1.pxi.spice
+++ b/cells/fah/sky130_fd_sc_lp__fah_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fah_1.pxi.spice
-* Created: Fri Aug 28 10:35:28 2020
+* Created: Wed Sep 2 09:53:43 2020
*
x_PM_SKY130_FD_SC_LP__FAH_1%CI N_CI_M1008_g N_CI_M1011_g CI N_CI_c_267_n
+ PM_SKY130_FD_SC_LP__FAH_1%CI
diff --git a/cells/fah/sky130_fd_sc_lp__fah_1.spice b/cells/fah/sky130_fd_sc_lp__fah_1.spice
index 6a105f3..49294d7 100644
--- a/cells/fah/sky130_fd_sc_lp__fah_1.spice
+++ b/cells/fah/sky130_fd_sc_lp__fah_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fah_1.spice
-* Created: Fri Aug 28 10:35:28 2020
+* Created: Wed Sep 2 09:53:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.lvs.report b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.lvs.report
new file mode 100644
index 0000000..c903717
--- /dev/null
+++ b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fahcin_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fahcin_1.sp ('sky130_fd_sc_lp__fahcin_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fahcin/sky130_fd_sc_lp__fahcin_1.spice ('sky130_fd_sc_lp__fahcin_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fahcin_1 sky130_fd_sc_lp__fahcin_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fahcin_1
+SOURCE CELL NAME: sky130_fd_sc_lp__fahcin_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CIN VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pex.spice b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pex.spice
index 18e24a2..d030edb 100644
--- a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pex.spice
+++ b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcin_1.pex.spice
-* Created: Fri Aug 28 10:35:37 2020
+* Created: Wed Sep 2 09:53:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pxi.spice b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pxi.spice
index eb29408..cbbb07d 100644
--- a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pxi.spice
+++ b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcin_1.pxi.spice
-* Created: Fri Aug 28 10:35:37 2020
+* Created: Wed Sep 2 09:53:50 2020
*
x_PM_SKY130_FD_SC_LP__FAHCIN_1%A N_A_M1016_g N_A_M1012_g A N_A_c_250_n
+ N_A_c_251_n PM_SKY130_FD_SC_LP__FAHCIN_1%A
diff --git a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.spice b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.spice
index 916bc04..b2602a2 100644
--- a/cells/fahcin/sky130_fd_sc_lp__fahcin_1.spice
+++ b/cells/fahcin/sky130_fd_sc_lp__fahcin_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcin_1.spice
-* Created: Fri Aug 28 10:35:37 2020
+* Created: Wed Sep 2 09:53:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.lvs.report b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.lvs.report
new file mode 100644
index 0000000..630ea1a
--- /dev/null
+++ b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fahcon_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fahcon_1.sp ('sky130_fd_sc_lp__fahcon_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fahcon/sky130_fd_sc_lp__fahcon_1.spice ('sky130_fd_sc_lp__fahcon_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:53:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__fahcon_1 sky130_fd_sc_lp__fahcon_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__fahcon_1
+SOURCE CELL NAME: sky130_fd_sc_lp__fahcon_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 19 19
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 16 16 0 0 MN(NSHORT)
+ 16 16 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B CI VPWR COUT_N SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pex.spice b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pex.spice
index 96dd7f1..4a1cf6e 100644
--- a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pex.spice
+++ b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcon_1.pex.spice
-* Created: Fri Aug 28 10:35:46 2020
+* Created: Wed Sep 2 09:53:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pxi.spice b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pxi.spice
index 3fe8bcd..a653cd0 100644
--- a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pxi.spice
+++ b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcon_1.pxi.spice
-* Created: Fri Aug 28 10:35:46 2020
+* Created: Wed Sep 2 09:53:57 2020
*
x_PM_SKY130_FD_SC_LP__FAHCON_1%A N_A_M1030_g N_A_M1025_g A N_A_c_218_n
+ N_A_c_219_n PM_SKY130_FD_SC_LP__FAHCON_1%A
diff --git a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.spice b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.spice
index eb55890..738340c 100644
--- a/cells/fahcon/sky130_fd_sc_lp__fahcon_1.spice
+++ b/cells/fahcon/sky130_fd_sc_lp__fahcon_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__fahcon_1.spice
-* Created: Fri Aug 28 10:35:46 2020
+* Created: Wed Sep 2 09:53:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/fill/sky130_fd_sc_lp__fill_1.lvs.report b/cells/fill/sky130_fd_sc_lp__fill_1.lvs.report
new file mode 100644
index 0000000..c7fa7f9
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_lp__fill_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fill_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fill_1.sp ('sky130_fd_sc_lp__fill_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fill/sky130_fd_sc_lp__fill_1.spice ('sky130_fd_sc_lp__fill_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_lp__fill_2.lvs.report b/cells/fill/sky130_fd_sc_lp__fill_2.lvs.report
new file mode 100644
index 0000000..98bee45
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_lp__fill_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fill_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fill_2.sp ('sky130_fd_sc_lp__fill_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fill/sky130_fd_sc_lp__fill_2.spice ('sky130_fd_sc_lp__fill_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_lp__fill_4.lvs.report b/cells/fill/sky130_fd_sc_lp__fill_4.lvs.report
new file mode 100644
index 0000000..00c7bb6
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_lp__fill_4.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fill_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fill_4.sp ('sky130_fd_sc_lp__fill_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fill/sky130_fd_sc_lp__fill_4.spice ('sky130_fd_sc_lp__fill_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/fill/sky130_fd_sc_lp__fill_8.lvs.report b/cells/fill/sky130_fd_sc_lp__fill_8.lvs.report
new file mode 100644
index 0000000..45bad48
--- /dev/null
+++ b/cells/fill/sky130_fd_sc_lp__fill_8.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__fill_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__fill_8.sp ('sky130_fd_sc_lp__fill_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/fill/sky130_fd_sc_lp__fill_8.spice ('sky130_fd_sc_lp__fill_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_0.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_0.lvs.report
new file mode 100644
index 0000000..460b201
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_0.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_0.sp ('sky130_fd_sc_lp__ha_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_0.spice ('sky130_fd_sc_lp__ha_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_0 sky130_fd_sc_lp__ha_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_0
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_0.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_0.pex.spice
index 18e6861..b279e59 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_0.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_0.pex.spice
-* Created: Fri Aug 28 10:36:06 2020
+* Created: Wed Sep 2 09:54:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_0.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_0.pxi.spice
index 343315c..b5a8e0e 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_0.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_0.pxi.spice
-* Created: Fri Aug 28 10:36:06 2020
+* Created: Wed Sep 2 09:54:17 2020
*
x_PM_SKY130_FD_SC_LP__HA_0%A_80_60# N_A_80_60#_M1013_s N_A_80_60#_M1008_d
+ N_A_80_60#_M1003_g N_A_80_60#_c_96_n N_A_80_60#_M1000_g N_A_80_60#_c_98_n
diff --git a/cells/ha/sky130_fd_sc_lp__ha_0.spice b/cells/ha/sky130_fd_sc_lp__ha_0.spice
index 5cd4181..66108b7 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_0.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_0.spice
-* Created: Fri Aug 28 10:36:06 2020
+* Created: Wed Sep 2 09:54:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_lp__ha_1.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_1.lvs.report
new file mode 100644
index 0000000..854ccec
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_1.sp ('sky130_fd_sc_lp__ha_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_1.spice ('sky130_fd_sc_lp__ha_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_1 sky130_fd_sc_lp__ha_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_1
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_1.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_1.pex.spice
index 40acd35..a45d531 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_1.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_1.pex.spice
-* Created: Fri Aug 28 10:36:13 2020
+* Created: Wed Sep 2 09:54:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_1.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_1.pxi.spice
index 3782b97..cdd3950 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_1.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_1.pxi.spice
-* Created: Fri Aug 28 10:36:13 2020
+* Created: Wed Sep 2 09:54:23 2020
*
x_PM_SKY130_FD_SC_LP__HA_1%A_80_30# N_A_80_30#_M1007_s N_A_80_30#_M1008_d
+ N_A_80_30#_M1009_g N_A_80_30#_M1003_g N_A_80_30#_c_101_n N_A_80_30#_c_102_n
diff --git a/cells/ha/sky130_fd_sc_lp__ha_1.spice b/cells/ha/sky130_fd_sc_lp__ha_1.spice
index caef92b..521bae8 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_1.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_1.spice
-* Created: Fri Aug 28 10:36:13 2020
+* Created: Wed Sep 2 09:54:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_lp__ha_2.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_2.lvs.report
new file mode 100644
index 0000000..3932616
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_2.sp ('sky130_fd_sc_lp__ha_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_2.spice ('sky130_fd_sc_lp__ha_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_2 sky130_fd_sc_lp__ha_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_2
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR COUT SUM VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_2.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_2.pex.spice
index 1a49724..a71e681 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_2.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_2.pex.spice
-* Created: Fri Aug 28 10:36:21 2020
+* Created: Wed Sep 2 09:54:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_2.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_2.pxi.spice
index d81b568..8fdbc4e 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_2.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_2.pxi.spice
-* Created: Fri Aug 28 10:36:21 2020
+* Created: Wed Sep 2 09:54:30 2020
*
x_PM_SKY130_FD_SC_LP__HA_2%A_270_95# N_A_270_95#_M1004_s N_A_270_95#_M1014_d
+ N_A_270_95#_c_102_n N_A_270_95#_M1011_g N_A_270_95#_c_103_n
diff --git a/cells/ha/sky130_fd_sc_lp__ha_2.spice b/cells/ha/sky130_fd_sc_lp__ha_2.spice
index 6fc2cf3..d1fe7fc 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_2.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_2.spice
-* Created: Fri Aug 28 10:36:21 2020
+* Created: Wed Sep 2 09:54:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_lp__ha_4.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_4.lvs.report
new file mode 100644
index 0000000..9d7ac50
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_4.sp ('sky130_fd_sc_lp__ha_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_4.spice ('sky130_fd_sc_lp__ha_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_4 sky130_fd_sc_lp__ha_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_4
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 36 layout mos transistors were reduced to 14.
+ 22 mos transistors were deleted by parallel reduction.
+ 36 source mos transistors were reduced to 14.
+ 22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR SUM COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_4.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_4.pex.spice
index 16ed44b..d31d7dc 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_4.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_4.pex.spice
-* Created: Fri Aug 28 10:36:35 2020
+* Created: Wed Sep 2 09:54:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_4.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_4.pxi.spice
index 1f03018..508d4a6 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_4.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_4.pxi.spice
-* Created: Fri Aug 28 10:36:35 2020
+* Created: Wed Sep 2 09:54:37 2020
*
x_PM_SKY130_FD_SC_LP__HA_4%A_110_263# N_A_110_263#_M1005_d N_A_110_263#_M1008_d
+ N_A_110_263#_M1028_d N_A_110_263#_M1015_d N_A_110_263#_M1003_g
diff --git a/cells/ha/sky130_fd_sc_lp__ha_4.spice b/cells/ha/sky130_fd_sc_lp__ha_4.spice
index c8b43ba..dc4960f 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_4.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_4.spice
-* Created: Fri Aug 28 10:36:35 2020
+* Created: Wed Sep 2 09:54:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_lp__ha_lp.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_lp.lvs.report
new file mode 100644
index 0000000..5350f19
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_lp.sp ('sky130_fd_sc_lp__ha_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_lp.spice ('sky130_fd_sc_lp__ha_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_lp sky130_fd_sc_lp__ha_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 9 9 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_lp.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_lp.pex.spice
index 03d1c7a..4457bbf 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_lp.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_lp.pex.spice
-* Created: Fri Aug 28 10:36:44 2020
+* Created: Wed Sep 2 09:54:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_lp.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_lp.pxi.spice
index e6e54e9..cd75aa8 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_lp.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_lp.pxi.spice
-* Created: Fri Aug 28 10:36:44 2020
+* Created: Wed Sep 2 09:54:44 2020
*
x_PM_SKY130_FD_SC_LP__HA_LP%A_83_153# N_A_83_153#_M1005_s N_A_83_153#_M1013_d
+ N_A_83_153#_M1008_g N_A_83_153#_c_117_n N_A_83_153#_M1006_g
diff --git a/cells/ha/sky130_fd_sc_lp__ha_lp.spice b/cells/ha/sky130_fd_sc_lp__ha_lp.spice
index 73a8992..03626d3 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_lp.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_lp.spice
-* Created: Fri Aug 28 10:36:44 2020
+* Created: Wed Sep 2 09:54:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/ha/sky130_fd_sc_lp__ha_m.lvs.report b/cells/ha/sky130_fd_sc_lp__ha_m.lvs.report
new file mode 100644
index 0000000..0e980b8
--- /dev/null
+++ b/cells/ha/sky130_fd_sc_lp__ha_m.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__ha_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__ha_m.sp ('sky130_fd_sc_lp__ha_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/ha/sky130_fd_sc_lp__ha_m.spice ('sky130_fd_sc_lp__ha_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__ha_m sky130_fd_sc_lp__ha_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__ha_m
+SOURCE CELL NAME: sky130_fd_sc_lp__ha_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 10 10
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 10 10 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A SUM VPWR COUT VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/ha/sky130_fd_sc_lp__ha_m.pex.spice b/cells/ha/sky130_fd_sc_lp__ha_m.pex.spice
index 3992ed5..c0414f8 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_m.pex.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_m.pex.spice
-* Created: Fri Aug 28 10:36:53 2020
+* Created: Wed Sep 2 09:54:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/ha/sky130_fd_sc_lp__ha_m.pxi.spice b/cells/ha/sky130_fd_sc_lp__ha_m.pxi.spice
index a57bf8d..4f0a163 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_m.pxi.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_m.pxi.spice
-* Created: Fri Aug 28 10:36:53 2020
+* Created: Wed Sep 2 09:54:51 2020
*
x_PM_SKY130_FD_SC_LP__HA_M%A_80_60# N_A_80_60#_M1011_s N_A_80_60#_M1003_d
+ N_A_80_60#_M1001_g N_A_80_60#_c_101_n N_A_80_60#_c_102_n N_A_80_60#_c_103_n
diff --git a/cells/ha/sky130_fd_sc_lp__ha_m.spice b/cells/ha/sky130_fd_sc_lp__ha_m.spice
index 6d58065..e420685 100644
--- a/cells/ha/sky130_fd_sc_lp__ha_m.spice
+++ b/cells/ha/sky130_fd_sc_lp__ha_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__ha_m.spice
-* Created: Fri Aug 28 10:36:53 2020
+* Created: Wed Sep 2 09:54:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.lvs.report b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.lvs.report
new file mode 100644
index 0000000..fda61b1
--- /dev/null
+++ b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inputiso0n_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inputiso0n_lp.sp ('sky130_fd_sc_lp__inputiso0n_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.spice ('sky130_fd_sc_lp__inputiso0n_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:54:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inputiso0n_lp sky130_fd_sc_lp__inputiso0n_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inputiso0n_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inputiso0n_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 13
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP_B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pex.spice b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pex.spice
index 838e821..d5c70ce 100644
--- a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pex.spice
+++ b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0n_lp.pex.spice
-* Created: Fri Aug 28 10:37:01 2020
+* Created: Wed Sep 2 09:54:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pxi.spice b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pxi.spice
index 79dc9a8..9afb1c4 100644
--- a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pxi.spice
+++ b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0n_lp.pxi.spice
-* Created: Fri Aug 28 10:37:01 2020
+* Created: Wed Sep 2 09:54:58 2020
*
x_PM_SKY130_FD_SC_LP__INPUTISO0N_LP%A N_A_M1009_g N_A_M1007_g N_A_M1005_g A
+ N_A_c_49_n N_A_c_50_n PM_SKY130_FD_SC_LP__INPUTISO0N_LP%A
diff --git a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.spice b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.spice
index e67fe09..1254f1b 100644
--- a/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.spice
+++ b/cells/inputiso0n/sky130_fd_sc_lp__inputiso0n_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0n_lp.spice
-* Created: Fri Aug 28 10:37:01 2020
+* Created: Wed Sep 2 09:54:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.lvs.report b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.lvs.report
new file mode 100644
index 0000000..c0acceb
--- /dev/null
+++ b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inputiso0p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inputiso0p_lp.sp ('sky130_fd_sc_lp__inputiso0p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.spice ('sky130_fd_sc_lp__inputiso0p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inputiso0p_lp sky130_fd_sc_lp__inputiso0p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inputiso0p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inputiso0p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pex.spice b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pex.spice
index 0ad268b..6543a53 100644
--- a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pex.spice
+++ b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0p_lp.pex.spice
-* Created: Fri Aug 28 10:37:09 2020
+* Created: Wed Sep 2 09:55:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pxi.spice b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pxi.spice
index 793c621..c428989 100644
--- a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pxi.spice
+++ b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0p_lp.pxi.spice
-* Created: Fri Aug 28 10:37:09 2020
+* Created: Wed Sep 2 09:55:04 2020
*
x_PM_SKY130_FD_SC_LP__INPUTISO0P_LP%SLEEP N_SLEEP_M1012_g N_SLEEP_M1005_g
+ N_SLEEP_M1006_g N_SLEEP_M1002_g SLEEP SLEEP N_SLEEP_c_65_n
diff --git a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.spice b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.spice
index 9567721..8956d43 100644
--- a/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.spice
+++ b/cells/inputiso0p/sky130_fd_sc_lp__inputiso0p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso0p_lp.spice
-* Created: Fri Aug 28 10:37:09 2020
+* Created: Wed Sep 2 09:55:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.lvs.report b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.lvs.report
new file mode 100644
index 0000000..8f42254
--- /dev/null
+++ b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inputiso1n_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inputiso1n_lp.sp ('sky130_fd_sc_lp__inputiso1n_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.spice ('sky130_fd_sc_lp__inputiso1n_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inputiso1n_lp sky130_fd_sc_lp__inputiso1n_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inputiso1n_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inputiso1n_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP_B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pex.spice b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pex.spice
index 108e504..365f6ed 100644
--- a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pex.spice
+++ b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1n_lp.pex.spice
-* Created: Fri Aug 28 10:37:17 2020
+* Created: Wed Sep 2 09:55:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pxi.spice b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pxi.spice
index d8ae887..ac92608 100644
--- a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pxi.spice
+++ b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1n_lp.pxi.spice
-* Created: Fri Aug 28 10:37:17 2020
+* Created: Wed Sep 2 09:55:11 2020
*
x_PM_SKY130_FD_SC_LP__INPUTISO1N_LP%SLEEP_B N_SLEEP_B_M1006_g N_SLEEP_B_M1004_g
+ N_SLEEP_B_M1001_g N_SLEEP_B_M1009_g SLEEP_B SLEEP_B N_SLEEP_B_c_65_n
diff --git a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.spice b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.spice
index dbcfba2..061606b 100644
--- a/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.spice
+++ b/cells/inputiso1n/sky130_fd_sc_lp__inputiso1n_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1n_lp.spice
-* Created: Fri Aug 28 10:37:17 2020
+* Created: Wed Sep 2 09:55:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.lvs.report b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.lvs.report
new file mode 100644
index 0000000..fbc5724
--- /dev/null
+++ b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inputiso1p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inputiso1p_lp.sp ('sky130_fd_sc_lp__inputiso1p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.spice ('sky130_fd_sc_lp__inputiso1p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inputiso1p_lp sky130_fd_sc_lp__inputiso1p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inputiso1p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inputiso1p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pex.spice b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pex.spice
index 1097845..9ad224d 100644
--- a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pex.spice
+++ b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1p_lp.pex.spice
-* Created: Fri Aug 28 10:37:25 2020
+* Created: Wed Sep 2 09:55:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pxi.spice b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pxi.spice
index 77a368a..ed7571c 100644
--- a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pxi.spice
+++ b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1p_lp.pxi.spice
-* Created: Fri Aug 28 10:37:25 2020
+* Created: Wed Sep 2 09:55:18 2020
*
x_PM_SKY130_FD_SC_LP__INPUTISO1P_LP%A N_A_c_43_n N_A_M1007_g N_A_c_44_n
+ N_A_M1005_g N_A_c_46_n N_A_M1008_g A A PM_SKY130_FD_SC_LP__INPUTISO1P_LP%A
diff --git a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.spice b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.spice
index 4dc2caf..21a0201 100644
--- a/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.spice
+++ b/cells/inputiso1p/sky130_fd_sc_lp__inputiso1p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputiso1p_lp.spice
-* Created: Fri Aug 28 10:37:25 2020
+* Created: Wed Sep 2 09:55:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.lvs.report b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.lvs.report
new file mode 100644
index 0000000..d97e127
--- /dev/null
+++ b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inputisolatch_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inputisolatch_lp.sp ('sky130_fd_sc_lp__inputisolatch_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.spice ('sky130_fd_sc_lp__inputisolatch_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inputisolatch_lp sky130_fd_sc_lp__inputisolatch_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inputisolatch_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inputisolatch_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 19 19
+
+ Instances: 12 12 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SLEEP_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pex.spice b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pex.spice
index b69a21c..c062bd1 100644
--- a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pex.spice
+++ b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputisolatch_lp.pex.spice
-* Created: Fri Aug 28 10:37:39 2020
+* Created: Wed Sep 2 09:55:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pxi.spice b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pxi.spice
index 5e19a90..b72ce60 100644
--- a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pxi.spice
+++ b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputisolatch_lp.pxi.spice
-* Created: Fri Aug 28 10:37:39 2020
+* Created: Wed Sep 2 09:55:25 2020
*
x_PM_SKY130_FD_SC_LP__INPUTISOLATCH_LP%D N_D_M1001_g N_D_M1010_g N_D_c_147_n
+ N_D_c_151_n N_D_c_152_n N_D_c_153_n D D N_D_c_149_n
diff --git a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.spice b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.spice
index a6a36d6..4b5383d 100644
--- a/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.spice
+++ b/cells/inputisolatch/sky130_fd_sc_lp__inputisolatch_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inputisolatch_lp.spice
-* Created: Fri Aug 28 10:37:39 2020
+* Created: Wed Sep 2 09:55:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_0.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_0.lvs.report
new file mode 100644
index 0000000..e47ea5b
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_0.sp ('sky130_fd_sc_lp__inv_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_0.spice ('sky130_fd_sc_lp__inv_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_0 sky130_fd_sc_lp__inv_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_0
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_0.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_0.pex.spice
index e688236..9d50f3a 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_0.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_0.pex.spice
-* Created: Fri Aug 28 10:37:47 2020
+* Created: Wed Sep 2 09:55:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_0.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_0.pxi.spice
index e35915e..ff862fa 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_0.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_0.pxi.spice
-* Created: Fri Aug 28 10:37:47 2020
+* Created: Wed Sep 2 09:55:32 2020
*
x_PM_SKY130_FD_SC_LP__INV_0%A N_A_M1000_g N_A_M1001_g A A A N_A_c_20_n
+ N_A_c_21_n PM_SKY130_FD_SC_LP__INV_0%A
diff --git a/cells/inv/sky130_fd_sc_lp__inv_0.spice b/cells/inv/sky130_fd_sc_lp__inv_0.spice
index b76c83a..6f98d3d 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_0.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_0.spice
-* Created: Fri Aug 28 10:37:47 2020
+* Created: Wed Sep 2 09:55:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_1.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_1.lvs.report
new file mode 100644
index 0000000..95b02f7
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_1.sp ('sky130_fd_sc_lp__inv_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_1.spice ('sky130_fd_sc_lp__inv_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_1 sky130_fd_sc_lp__inv_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_1
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_1.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_1.pex.spice
index f4ae640..ac85fd7 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_1.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_1.pex.spice
-* Created: Fri Aug 28 10:38:05 2020
+* Created: Wed Sep 2 09:55:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_1.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_1.pxi.spice
index 99b8b18..2926d9e 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_1.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_1.pxi.spice
-* Created: Fri Aug 28 10:38:05 2020
+* Created: Wed Sep 2 09:55:45 2020
*
x_PM_SKY130_FD_SC_LP__INV_1%A N_A_M1000_g N_A_M1001_g A A N_A_c_20_n N_A_c_21_n
+ PM_SKY130_FD_SC_LP__INV_1%A
diff --git a/cells/inv/sky130_fd_sc_lp__inv_1.spice b/cells/inv/sky130_fd_sc_lp__inv_1.spice
index e216415..8d99bae 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_1.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_1.spice
-* Created: Fri Aug 28 10:38:05 2020
+* Created: Wed Sep 2 09:55:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_16.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_16.lvs.report
new file mode 100644
index 0000000..4704105
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_16.lvs.report
@@ -0,0 +1,502 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_16.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_16.sp ('sky130_fd_sc_lp__inv_16')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_16.spice ('sky130_fd_sc_lp__inv_16')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_lp__inv_16 sky130_fd_sc_lp__inv_16
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_16
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_16
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 5 *
+
+ Nets: 6 6
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 5 *
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT PORTS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 2 on net: 2 ** missing port **
+ 2 VPWR on net: VPWR VPB on net: VPB
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 5 5 1 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 2.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Layout Names That Are Missing In The Source:
+
+ Ports: VPWR
+ Nets: VPWR
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB A Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_16.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_16.pex.spice
index 70554ac..17396d0 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_16.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_16.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_16.pex.spice
-* Created: Fri Aug 28 10:37:57 2020
+* Created: Wed Sep 2 09:55:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_16.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_16.pxi.spice
index 1963de0..40094ad 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_16.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_16.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_16.pxi.spice
-* Created: Fri Aug 28 10:37:57 2020
+* Created: Wed Sep 2 09:55:38 2020
*
x_PM_SKY130_FD_SC_LP__INV_16%A N_A_M1001_g N_A_c_147_n N_A_M1000_g N_A_M1002_g
+ N_A_c_148_n N_A_M1004_g N_A_M1003_g N_A_c_149_n N_A_M1006_g N_A_M1005_g
diff --git a/cells/inv/sky130_fd_sc_lp__inv_16.spice b/cells/inv/sky130_fd_sc_lp__inv_16.spice
index 8ab4aca..4602780 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_16.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_16.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_16.spice
-* Created: Fri Aug 28 10:37:57 2020
+* Created: Wed Sep 2 09:55:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_2.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_2.lvs.report
new file mode 100644
index 0000000..70cdc2d
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_2.sp ('sky130_fd_sc_lp__inv_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_2.spice ('sky130_fd_sc_lp__inv_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_2 sky130_fd_sc_lp__inv_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_2
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_2.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_2.pex.spice
index 8bd896d..dc75c8a 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_2.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_2.pex.spice
-* Created: Fri Aug 28 10:38:13 2020
+* Created: Wed Sep 2 09:55:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_2.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_2.pxi.spice
index 3290b28..4e89b77 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_2.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_2.pxi.spice
-* Created: Fri Aug 28 10:38:13 2020
+* Created: Wed Sep 2 09:55:52 2020
*
x_PM_SKY130_FD_SC_LP__INV_2%A N_A_c_25_n N_A_M1000_g N_A_M1001_g N_A_c_27_n
+ N_A_M1002_g N_A_M1003_g A A N_A_c_30_n PM_SKY130_FD_SC_LP__INV_2%A
diff --git a/cells/inv/sky130_fd_sc_lp__inv_2.spice b/cells/inv/sky130_fd_sc_lp__inv_2.spice
index 9eef8a2..f700155 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_2.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_2.spice
-* Created: Fri Aug 28 10:38:13 2020
+* Created: Wed Sep 2 09:55:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_4.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_4.lvs.report
new file mode 100644
index 0000000..546a5c3
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_4.sp ('sky130_fd_sc_lp__inv_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_4.spice ('sky130_fd_sc_lp__inv_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:55:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_4 sky130_fd_sc_lp__inv_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_4
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_4.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_4.pex.spice
index 9a0cb2b..294a778 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_4.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_4.pex.spice
-* Created: Fri Aug 28 10:38:20 2020
+* Created: Wed Sep 2 09:55:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_4.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_4.pxi.spice
index d7b4e77..5578319 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_4.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_4.pxi.spice
-* Created: Fri Aug 28 10:38:20 2020
+* Created: Wed Sep 2 09:55:59 2020
*
x_PM_SKY130_FD_SC_LP__INV_4%A N_A_c_41_n N_A_M1000_g N_A_M1003_g N_A_c_43_n
+ N_A_M1001_g N_A_M1004_g N_A_c_45_n N_A_M1002_g N_A_M1006_g N_A_c_47_n
diff --git a/cells/inv/sky130_fd_sc_lp__inv_4.spice b/cells/inv/sky130_fd_sc_lp__inv_4.spice
index cc9cdab..087b8c8 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_4.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_4.spice
-* Created: Fri Aug 28 10:38:20 2020
+* Created: Wed Sep 2 09:55:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_8.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_8.lvs.report
new file mode 100644
index 0000000..0b98b70
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_8.sp ('sky130_fd_sc_lp__inv_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_8.spice ('sky130_fd_sc_lp__inv_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_8 sky130_fd_sc_lp__inv_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_8
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 2.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_8.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_8.pex.spice
index b65c839..950b828 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_8.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_8.pex.spice
-* Created: Fri Aug 28 10:38:29 2020
+* Created: Wed Sep 2 09:56:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_8.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_8.pxi.spice
index ba11dda..6ce0960 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_8.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_8.pxi.spice
-* Created: Fri Aug 28 10:38:29 2020
+* Created: Wed Sep 2 09:56:05 2020
*
x_PM_SKY130_FD_SC_LP__INV_8%A N_A_M1001_g N_A_M1000_g N_A_M1004_g N_A_M1002_g
+ N_A_M1005_g N_A_M1003_g N_A_M1007_g N_A_M1006_g N_A_M1010_g N_A_M1008_g
diff --git a/cells/inv/sky130_fd_sc_lp__inv_8.spice b/cells/inv/sky130_fd_sc_lp__inv_8.spice
index f8cc23b..de5d624 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_8.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_8.spice
-* Created: Fri Aug 28 10:38:29 2020
+* Created: Wed Sep 2 09:56:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_lp.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_lp.lvs.report
new file mode 100644
index 0000000..c6043b3
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_lp.sp ('sky130_fd_sc_lp__inv_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_lp.spice ('sky130_fd_sc_lp__inv_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_lp sky130_fd_sc_lp__inv_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_lp.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_lp.pex.spice
index 04f4e53..824c637 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_lp.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_lp.pex.spice
-* Created: Fri Aug 28 10:38:42 2020
+* Created: Wed Sep 2 09:56:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_lp.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_lp.pxi.spice
index c0d0c77..c192d30 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_lp.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_lp.pxi.spice
-* Created: Fri Aug 28 10:38:42 2020
+* Created: Wed Sep 2 09:56:12 2020
*
x_PM_SKY130_FD_SC_LP__INV_LP%A N_A_M1000_g N_A_M1001_g N_A_M1002_g A A
+ N_A_c_27_n PM_SKY130_FD_SC_LP__INV_LP%A
diff --git a/cells/inv/sky130_fd_sc_lp__inv_lp.spice b/cells/inv/sky130_fd_sc_lp__inv_lp.spice
index a368429..8602ef0 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_lp.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_lp.spice
-* Created: Fri Aug 28 10:38:42 2020
+* Created: Wed Sep 2 09:56:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/inv/sky130_fd_sc_lp__inv_m.lvs.report b/cells/inv/sky130_fd_sc_lp__inv_m.lvs.report
new file mode 100644
index 0000000..baa6371
--- /dev/null
+++ b/cells/inv/sky130_fd_sc_lp__inv_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__inv_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__inv_m.sp ('sky130_fd_sc_lp__inv_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/inv/sky130_fd_sc_lp__inv_m.spice ('sky130_fd_sc_lp__inv_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__inv_m sky130_fd_sc_lp__inv_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__inv_m
+SOURCE CELL NAME: sky130_fd_sc_lp__inv_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/inv/sky130_fd_sc_lp__inv_m.pex.spice b/cells/inv/sky130_fd_sc_lp__inv_m.pex.spice
index 0430c30..6297753 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_m.pex.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_m.pex.spice
-* Created: Fri Aug 28 10:38:51 2020
+* Created: Wed Sep 2 09:56:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/inv/sky130_fd_sc_lp__inv_m.pxi.spice b/cells/inv/sky130_fd_sc_lp__inv_m.pxi.spice
index 6f0898b..5500efd 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_m.pxi.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_m.pxi.spice
-* Created: Fri Aug 28 10:38:51 2020
+* Created: Wed Sep 2 09:56:19 2020
*
x_PM_SKY130_FD_SC_LP__INV_M%A N_A_M1000_g N_A_M1001_g A A A A N_A_c_21_n
+ N_A_c_22_n N_A_c_23_n PM_SKY130_FD_SC_LP__INV_M%A
diff --git a/cells/inv/sky130_fd_sc_lp__inv_m.spice b/cells/inv/sky130_fd_sc_lp__inv_m.spice
index a051810..1dc8b9f 100644
--- a/cells/inv/sky130_fd_sc_lp__inv_m.spice
+++ b/cells/inv/sky130_fd_sc_lp__inv_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__inv_m.spice
-* Created: Fri Aug 28 10:38:51 2020
+* Created: Wed Sep 2 09:56:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.lvs.report b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.lvs.report
new file mode 100644
index 0000000..3c62a71
--- /dev/null
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invkapwr_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invkapwr_1.sp ('sky130_fd_sc_lp__invkapwr_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.spice ('sky130_fd_sc_lp__invkapwr_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invkapwr_1 sky130_fd_sc_lp__invkapwr_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invkapwr_1
+SOURCE CELL NAME: sky130_fd_sc_lp__invkapwr_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR Y VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pex.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pex.spice
index e9600ff..ed0eec4 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pex.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_1.pex.spice
-* Created: Fri Aug 28 10:39:01 2020
+* Created: Wed Sep 2 09:56:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pxi.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pxi.spice
index 21b852f..fadd116 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pxi.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_1.pxi.spice
-* Created: Fri Aug 28 10:39:01 2020
+* Created: Wed Sep 2 09:56:26 2020
*
x_PM_SKY130_FD_SC_LP__INVKAPWR_1%A N_A_M1000_g N_A_M1001_g N_A_c_26_n
+ N_A_M1002_g A A A PM_SKY130_FD_SC_LP__INVKAPWR_1%A
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.spice
index 2355840..752d302 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_1.spice
-* Created: Fri Aug 28 10:39:01 2020
+* Created: Wed Sep 2 09:56:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.lvs.report b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.lvs.report
new file mode 100644
index 0000000..f37fd9b
--- /dev/null
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invkapwr_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invkapwr_2.sp ('sky130_fd_sc_lp__invkapwr_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.spice ('sky130_fd_sc_lp__invkapwr_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invkapwr_2 sky130_fd_sc_lp__invkapwr_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invkapwr_2
+SOURCE CELL NAME: sky130_fd_sc_lp__invkapwr_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 6 5
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 5 layout mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+ 5 source mos transistors were reduced to 2.
+ 3 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A Y KAPWR VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pex.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pex.spice
index ff524aa..d4edf40 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pex.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_2.pex.spice
-* Created: Fri Aug 28 10:39:08 2020
+* Created: Wed Sep 2 09:56:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pxi.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pxi.spice
index bcf06b8..e4273bf 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pxi.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_2.pxi.spice
-* Created: Fri Aug 28 10:39:08 2020
+* Created: Wed Sep 2 09:56:33 2020
*
x_PM_SKY130_FD_SC_LP__INVKAPWR_2%A N_A_M1001_g N_A_M1002_g N_A_M1000_g
+ N_A_M1004_g N_A_M1003_g A A N_A_c_32_n N_A_c_33_n
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.spice
index 6b7869d..95c2031 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_2.spice
-* Created: Fri Aug 28 10:39:08 2020
+* Created: Wed Sep 2 09:56:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.lvs.report b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.lvs.report
new file mode 100644
index 0000000..28b1fa3
--- /dev/null
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invkapwr_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invkapwr_4.sp ('sky130_fd_sc_lp__invkapwr_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.spice ('sky130_fd_sc_lp__invkapwr_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invkapwr_4 sky130_fd_sc_lp__invkapwr_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invkapwr_4
+SOURCE CELL NAME: sky130_fd_sc_lp__invkapwr_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 10 layout mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+ 10 source mos transistors were reduced to 2.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR Y VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pex.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pex.spice
index 60dc2a1..7ede8e7 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pex.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_4.pex.spice
-* Created: Fri Aug 28 10:39:16 2020
+* Created: Wed Sep 2 09:56:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pxi.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pxi.spice
index 2b1dd42..e4fead5 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pxi.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_4.pxi.spice
-* Created: Fri Aug 28 10:39:16 2020
+* Created: Wed Sep 2 09:56:40 2020
*
x_PM_SKY130_FD_SC_LP__INVKAPWR_4%A N_A_M1001_g N_A_M1000_g N_A_M1002_g
+ N_A_M1004_g N_A_M1003_g N_A_M1007_g N_A_M1005_g N_A_M1008_g N_A_M1006_g
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.spice
index 4edc4cd..e7c3d0a 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_4.spice
-* Created: Fri Aug 28 10:39:16 2020
+* Created: Wed Sep 2 09:56:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.lvs.report b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.lvs.report
new file mode 100644
index 0000000..441793e
--- /dev/null
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.lvs.report
@@ -0,0 +1,479 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invkapwr_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invkapwr_8.sp ('sky130_fd_sc_lp__invkapwr_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.spice ('sky130_fd_sc_lp__invkapwr_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invkapwr_8 sky130_fd_sc_lp__invkapwr_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invkapwr_8
+SOURCE CELL NAME: sky130_fd_sc_lp__invkapwr_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 2.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A KAPWR Y VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pex.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pex.spice
index 1f1b0b7..a957add 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pex.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_8.pex.spice
-* Created: Fri Aug 28 10:39:23 2020
+* Created: Wed Sep 2 09:56:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pxi.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pxi.spice
index 2905e97..8224395 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pxi.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_8.pxi.spice
-* Created: Fri Aug 28 10:39:23 2020
+* Created: Wed Sep 2 09:56:46 2020
*
x_PM_SKY130_FD_SC_LP__INVKAPWR_8%A N_A_M1000_g N_A_M1003_g N_A_M1001_g
+ N_A_M1005_g N_A_M1002_g N_A_M1007_g N_A_M1004_g N_A_M1008_g N_A_M1006_g
diff --git a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.spice b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.spice
index 7bdb20c..e1bf8c6 100644
--- a/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.spice
+++ b/cells/invkapwr/sky130_fd_sc_lp__invkapwr_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invkapwr_8.spice
-* Created: Fri Aug 28 10:39:23 2020
+* Created: Wed Sep 2 09:56:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_0.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_0.lvs.report
new file mode 100644
index 0000000..f7f864f
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_0.sp ('sky130_fd_sc_lp__invlp_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_0.spice ('sky130_fd_sc_lp__invlp_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_0 sky130_fd_sc_lp__invlp_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_0
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_0.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_0.pex.spice
index e7427ce..b7b3a2e 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_0.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_0.pex.spice
-* Created: Fri Aug 28 10:39:31 2020
+* Created: Wed Sep 2 09:56:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_0.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_0.pxi.spice
index 3717209..8b4d719 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_0.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_0.pxi.spice
-* Created: Fri Aug 28 10:39:31 2020
+* Created: Wed Sep 2 09:56:53 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_0%A N_A_M1000_g N_A_M1001_g N_A_c_29_n N_A_M1002_g
+ N_A_M1003_g N_A_c_32_n N_A_c_38_n N_A_c_33_n A A A N_A_c_35_n
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_0.spice b/cells/invlp/sky130_fd_sc_lp__invlp_0.spice
index 5e3fd7e..38b21ac 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_0.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_0.spice
-* Created: Fri Aug 28 10:39:31 2020
+* Created: Wed Sep 2 09:56:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_1.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_1.lvs.report
new file mode 100644
index 0000000..9417ee3
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_1.sp ('sky130_fd_sc_lp__invlp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_1.spice ('sky130_fd_sc_lp__invlp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:56:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_1 sky130_fd_sc_lp__invlp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_1.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_1.pex.spice
index d5a9de1..e9759d6 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_1.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_1.pex.spice
-* Created: Fri Aug 28 10:39:45 2020
+* Created: Wed Sep 2 09:57:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_1.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_1.pxi.spice
index d54416a..28fb880 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_1.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_1.pxi.spice
-* Created: Fri Aug 28 10:39:45 2020
+* Created: Wed Sep 2 09:57:00 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_1%A N_A_c_23_n N_A_M1003_g N_A_M1000_g N_A_c_25_n
+ N_A_c_26_n N_A_M1001_g N_A_M1002_g N_A_c_28_n N_A_c_29_n N_A_c_30_n A
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_1.spice b/cells/invlp/sky130_fd_sc_lp__invlp_1.spice
index 6b6e85d..fbc8050 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_1.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_1.spice
-* Created: Fri Aug 28 10:39:45 2020
+* Created: Wed Sep 2 09:57:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_2.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_2.lvs.report
new file mode 100644
index 0000000..9b5d05e
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_2.sp ('sky130_fd_sc_lp__invlp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_2.spice ('sky130_fd_sc_lp__invlp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_2 sky130_fd_sc_lp__invlp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_2.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_2.pex.spice
index 7a45acf..82f0ba2 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_2.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_2.pex.spice
-* Created: Fri Aug 28 10:39:53 2020
+* Created: Wed Sep 2 09:57:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_2.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_2.pxi.spice
index 949bb7f..0eb72d2 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_2.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_2.pxi.spice
-* Created: Fri Aug 28 10:39:53 2020
+* Created: Wed Sep 2 09:57:07 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_2%A N_A_c_39_n N_A_M1001_g N_A_M1000_g N_A_c_41_n
+ N_A_M1002_g N_A_M1004_g N_A_c_44_n N_A_M1007_g N_A_M1005_g N_A_c_47_n
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_2.spice b/cells/invlp/sky130_fd_sc_lp__invlp_2.spice
index 97b5e3a..f899695 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_2.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_2.spice
-* Created: Fri Aug 28 10:39:53 2020
+* Created: Wed Sep 2 09:57:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_4.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_4.lvs.report
new file mode 100644
index 0000000..8e175d7
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_4.sp ('sky130_fd_sc_lp__invlp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_4.spice ('sky130_fd_sc_lp__invlp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_4 sky130_fd_sc_lp__invlp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_4.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_4.pex.spice
index 08f8181..c8bac39 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_4.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_4.pex.spice
-* Created: Fri Aug 28 10:40:03 2020
+* Created: Wed Sep 2 09:57:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_4.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_4.pxi.spice
index fdbfe83..a3a2004 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_4.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_4.pxi.spice
-* Created: Fri Aug 28 10:40:03 2020
+* Created: Wed Sep 2 09:57:14 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_4%A N_A_M1000_g N_A_M1002_g N_A_M1009_g N_A_M1004_g
+ N_A_M1005_g N_A_M1011_g N_A_M1001_g N_A_M1003_g N_A_M1008_g N_A_M1006_g
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_4.spice b/cells/invlp/sky130_fd_sc_lp__invlp_4.spice
index 76f95b4..7f37c97 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_4.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_4.spice
-* Created: Fri Aug 28 10:40:03 2020
+* Created: Wed Sep 2 09:57:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_8.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_8.lvs.report
new file mode 100644
index 0000000..3eb6343
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_8.sp ('sky130_fd_sc_lp__invlp_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_8.spice ('sky130_fd_sc_lp__invlp_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_8 sky130_fd_sc_lp__invlp_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_8
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_8.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_8.pex.spice
index 41e7144..d39b463 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_8.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_8.pex.spice
-* Created: Fri Aug 28 10:40:11 2020
+* Created: Wed Sep 2 09:57:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_8.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_8.pxi.spice
index 7ac7286..e43f3b5 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_8.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_8.pxi.spice
-* Created: Fri Aug 28 10:40:11 2020
+* Created: Wed Sep 2 09:57:21 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_8%A N_A_M1001_g N_A_M1003_g N_A_M1004_g N_A_M1006_g
+ N_A_M1011_g N_A_M1010_g N_A_M1013_g N_A_M1017_g N_A_M1015_g N_A_M1020_g
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_8.spice b/cells/invlp/sky130_fd_sc_lp__invlp_8.spice
index e0e3732..c4c2b9b 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_8.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_8.spice
-* Created: Fri Aug 28 10:40:11 2020
+* Created: Wed Sep 2 09:57:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_m.lvs.report b/cells/invlp/sky130_fd_sc_lp__invlp_m.lvs.report
new file mode 100644
index 0000000..786e3ff
--- /dev/null
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__invlp_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__invlp_m.sp ('sky130_fd_sc_lp__invlp_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/invlp/sky130_fd_sc_lp__invlp_m.spice ('sky130_fd_sc_lp__invlp_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__invlp_m sky130_fd_sc_lp__invlp_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__invlp_m
+SOURCE CELL NAME: sky130_fd_sc_lp__invlp_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 6 6
+
+ Nets: 6 6
+
+ Instances: 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 2 2
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 6 6 0 0
+
+ Nets: 6 6 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 2 2 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_m.pex.spice b/cells/invlp/sky130_fd_sc_lp__invlp_m.pex.spice
index d7ba90a..290c5a6 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_m.pex.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_m.pex.spice
-* Created: Fri Aug 28 10:40:18 2020
+* Created: Wed Sep 2 09:57:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_m.pxi.spice b/cells/invlp/sky130_fd_sc_lp__invlp_m.pxi.spice
index a9e7a87..2cd3716 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_m.pxi.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_m.pxi.spice
-* Created: Fri Aug 28 10:40:18 2020
+* Created: Wed Sep 2 09:57:27 2020
*
x_PM_SKY130_FD_SC_LP__INVLP_M%A N_A_M1000_g N_A_M1001_g N_A_c_28_n N_A_M1003_g
+ N_A_M1002_g N_A_c_31_n N_A_c_37_n N_A_c_32_n A A A N_A_c_34_n
diff --git a/cells/invlp/sky130_fd_sc_lp__invlp_m.spice b/cells/invlp/sky130_fd_sc_lp__invlp_m.spice
index 85c706e..de4c607 100644
--- a/cells/invlp/sky130_fd_sc_lp__invlp_m.spice
+++ b/cells/invlp/sky130_fd_sc_lp__invlp_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__invlp_m.spice
-* Created: Fri Aug 28 10:40:18 2020
+* Created: Wed Sep 2 09:57:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.lvs.report b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.lvs.report
new file mode 100644
index 0000000..bc7e5d1
--- /dev/null
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso0n_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso0n_lp.sp ('sky130_fd_sc_lp__iso0n_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.spice ('sky130_fd_sc_lp__iso0n_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso0n_lp sky130_fd_sc_lp__iso0n_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso0n_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__iso0n_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 4 4 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VGND (port: VGND),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP_B VPWR X KAGND VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pex.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pex.spice
index c083a97..8a472e2 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pex.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp.pex.spice
-* Created: Fri Aug 28 10:40:34 2020
+* Created: Wed Sep 2 09:57:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pxi.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pxi.spice
index 515ff5a..bac5e49 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pxi.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp.pxi.spice
-* Created: Fri Aug 28 10:40:34 2020
+* Created: Wed Sep 2 09:57:41 2020
*
x_PM_SKY130_FD_SC_LP__ISO0N_LP%A N_A_M1009_g N_A_M1007_g N_A_M1005_g A
+ N_A_c_49_n N_A_c_50_n PM_SKY130_FD_SC_LP__ISO0N_LP%A
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.spice
index e9115c0..9d3843b 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp.spice
-* Created: Fri Aug 28 10:40:34 2020
+* Created: Wed Sep 2 09:57:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.lvs.report b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.lvs.report
new file mode 100644
index 0000000..09ca0de
--- /dev/null
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso0n_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso0n_lp2.sp ('sky130_fd_sc_lp__iso0n_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.spice ('sky130_fd_sc_lp__iso0n_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso0n_lp2 sky130_fd_sc_lp__iso0n_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso0n_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__iso0n_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 3 3 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VGND (port: VGND),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP_B VPWR X KAGND VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pex.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pex.spice
index a7c8326..429ef2a 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pex.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp2.pex.spice
-* Created: Fri Aug 28 10:40:25 2020
+* Created: Wed Sep 2 09:57:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pxi.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pxi.spice
index e97a70c..79c2403 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pxi.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp2.pxi.spice
-* Created: Fri Aug 28 10:40:25 2020
+* Created: Wed Sep 2 09:57:34 2020
*
x_PM_SKY130_FD_SC_LP__ISO0N_LP2%A N_A_c_46_n N_A_c_47_n N_A_c_48_n N_A_M1005_g
+ N_A_M1001_g A A N_A_c_51_n N_A_c_52_n PM_SKY130_FD_SC_LP__ISO0N_LP2%A
diff --git a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.spice b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.spice
index e6a5dd0..37008b4 100644
--- a/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.spice
+++ b/cells/iso0n/sky130_fd_sc_lp__iso0n_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0n_lp2.spice
-* Created: Fri Aug 28 10:40:25 2020
+* Created: Wed Sep 2 09:57:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.lvs.report b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.lvs.report
new file mode 100644
index 0000000..724fd99
--- /dev/null
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso0p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso0p_lp.sp ('sky130_fd_sc_lp__iso0p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.spice ('sky130_fd_sc_lp__iso0p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso0p_lp sky130_fd_sc_lp__iso0p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso0p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__iso0p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 17 17
+
+ Instances: 6 6 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pex.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pex.spice
index 1686f92..a862c94 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pex.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp.pex.spice
-* Created: Fri Aug 28 10:40:56 2020
+* Created: Wed Sep 2 09:57:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pxi.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pxi.spice
index 2455fa4..f6d0e87 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pxi.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp.pxi.spice
-* Created: Fri Aug 28 10:40:56 2020
+* Created: Wed Sep 2 09:57:55 2020
*
x_PM_SKY130_FD_SC_LP__ISO0P_LP%SLEEP N_SLEEP_M1012_g N_SLEEP_M1005_g
+ N_SLEEP_M1006_g N_SLEEP_M1002_g SLEEP SLEEP N_SLEEP_c_62_n
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.spice
index 50c1c0a..8815e22 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp.spice
-* Created: Fri Aug 28 10:40:56 2020
+* Created: Wed Sep 2 09:57:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.lvs.report b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.lvs.report
new file mode 100644
index 0000000..69e2b74
--- /dev/null
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso0p_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso0p_lp2.sp ('sky130_fd_sc_lp__iso0p_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.spice ('sky130_fd_sc_lp__iso0p_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso0p_lp2 sky130_fd_sc_lp__iso0p_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso0p_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__iso0p_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 4 4 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP A KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pex.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pex.spice
index 2cd9db2..28acf54 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pex.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp2.pex.spice
-* Created: Fri Aug 28 10:40:47 2020
+* Created: Wed Sep 2 09:57:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pxi.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pxi.spice
index 8bcbf3d..3a11b1d 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pxi.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp2.pxi.spice
-* Created: Fri Aug 28 10:40:47 2020
+* Created: Wed Sep 2 09:57:48 2020
*
x_PM_SKY130_FD_SC_LP__ISO0P_LP2%SLEEP N_SLEEP_c_53_n N_SLEEP_M1008_g
+ N_SLEEP_M1007_g N_SLEEP_c_54_n N_SLEEP_M1003_g SLEEP SLEEP N_SLEEP_c_55_n
diff --git a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.spice b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.spice
index 888f5a2..022fc34 100644
--- a/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.spice
+++ b/cells/iso0p/sky130_fd_sc_lp__iso0p_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso0p_lp2.spice
-* Created: Fri Aug 28 10:40:47 2020
+* Created: Wed Sep 2 09:57:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.lvs.report b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.lvs.report
new file mode 100644
index 0000000..7df644e
--- /dev/null
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso1n_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso1n_lp.sp ('sky130_fd_sc_lp__iso1n_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.spice ('sky130_fd_sc_lp__iso1n_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso1n_lp sky130_fd_sc_lp__iso1n_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso1n_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__iso1n_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 4 4 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VGND (port: VGND),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP_B A VPWR X KAGND VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pex.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pex.spice
index 732734f..9e1a58f 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pex.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp.pex.spice
-* Created: Fri Aug 28 10:41:13 2020
+* Created: Wed Sep 2 09:58:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pxi.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pxi.spice
index e9877a5..0726116 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pxi.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp.pxi.spice
-* Created: Fri Aug 28 10:41:13 2020
+* Created: Wed Sep 2 09:58:08 2020
*
x_PM_SKY130_FD_SC_LP__ISO1N_LP%SLEEP_B N_SLEEP_B_M1006_g N_SLEEP_B_M1004_g
+ N_SLEEP_B_M1001_g N_SLEEP_B_M1009_g SLEEP_B SLEEP_B N_SLEEP_B_c_62_n
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.spice
index f2678f9..c3319ed 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp.spice
-* Created: Fri Aug 28 10:41:13 2020
+* Created: Wed Sep 2 09:58:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.lvs.report b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.lvs.report
new file mode 100644
index 0000000..cbe8273
--- /dev/null
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.lvs.report
@@ -0,0 +1,476 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso1n_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso1n_lp2.sp ('sky130_fd_sc_lp__iso1n_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.spice ('sky130_fd_sc_lp__iso1n_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:57:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso1n_lp2 sky130_fd_sc_lp__iso1n_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso1n_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__iso1n_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VGND (port: VGND),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SLEEP_B A VPWR X KAGND VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pex.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pex.spice
index 78f2b5b..79b198a 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pex.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp2.pex.spice
-* Created: Fri Aug 28 10:41:05 2020
+* Created: Wed Sep 2 09:58:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pxi.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pxi.spice
index c306c12..9f02e32 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pxi.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp2.pxi.spice
-* Created: Fri Aug 28 10:41:05 2020
+* Created: Wed Sep 2 09:58:02 2020
*
x_PM_SKY130_FD_SC_LP__ISO1N_LP2%SLEEP_B N_SLEEP_B_c_63_n N_SLEEP_B_M1001_g
+ N_SLEEP_B_c_64_n N_SLEEP_B_c_65_n N_SLEEP_B_M1000_g N_SLEEP_B_c_66_n
diff --git a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.spice b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.spice
index 4cb42e5..370b927 100644
--- a/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.spice
+++ b/cells/iso1n/sky130_fd_sc_lp__iso1n_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1n_lp2.spice
-* Created: Fri Aug 28 10:41:05 2020
+* Created: Wed Sep 2 09:58:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.lvs.report b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.lvs.report
new file mode 100644
index 0000000..1f57a06
--- /dev/null
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso1p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso1p_lp.sp ('sky130_fd_sc_lp__iso1p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.spice ('sky130_fd_sc_lp__iso1p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso1p_lp sky130_fd_sc_lp__iso1p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso1p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__iso1p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pex.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pex.spice
index ab72e20..d4d2bf5 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pex.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp.pex.spice
-* Created: Fri Aug 28 10:41:28 2020
+* Created: Wed Sep 2 09:58:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pxi.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pxi.spice
index 5d286f7..c2733ea 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pxi.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp.pxi.spice
-* Created: Fri Aug 28 10:41:28 2020
+* Created: Wed Sep 2 09:58:22 2020
*
x_PM_SKY130_FD_SC_LP__ISO1P_LP%A N_A_c_42_n N_A_M1007_g N_A_c_43_n N_A_M1005_g
+ N_A_c_45_n N_A_M1008_g A A PM_SKY130_FD_SC_LP__ISO1P_LP%A
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.spice
index cf46826..1d11e5a 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp.spice
-* Created: Fri Aug 28 10:41:28 2020
+* Created: Wed Sep 2 09:58:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.lvs.report b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.lvs.report
new file mode 100644
index 0000000..a52bde4
--- /dev/null
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.lvs.report
@@ -0,0 +1,476 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__iso1p_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__iso1p_lp2.sp ('sky130_fd_sc_lp__iso1p_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.spice ('sky130_fd_sc_lp__iso1p_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__iso1p_lp2 sky130_fd_sc_lp__iso1p_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__iso1p_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__iso1p_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 passthrough layout net was found.
+ 1 passthrough source net was found.
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Passthrough Layout Nets And Their Ports:
+
+ (Layout nets which are connected only to ports).
+
+ VPWR (port: VPWR),
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP KAPWR X VGND VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pex.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pex.spice
index 51f4f1d..dcde97f 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pex.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp2.pex.spice
-* Created: Fri Aug 28 10:41:20 2020
+* Created: Wed Sep 2 09:58:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pxi.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pxi.spice
index 0424909..84546d1 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pxi.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp2.pxi.spice
-* Created: Fri Aug 28 10:41:20 2020
+* Created: Wed Sep 2 09:58:15 2020
*
x_PM_SKY130_FD_SC_LP__ISO1P_LP2%A N_A_M1006_g N_A_c_54_n N_A_M1003_g N_A_M1000_g
+ N_A_c_55_n A A N_A_c_52_n N_A_c_53_n PM_SKY130_FD_SC_LP__ISO1P_LP2%A
diff --git a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.spice b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.spice
index 13a2b58..91ddb39 100644
--- a/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.spice
+++ b/cells/iso1p/sky130_fd_sc_lp__iso1p_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__iso1p_lp2.spice
-* Created: Fri Aug 28 10:41:20 2020
+* Created: Wed Sep 2 09:58:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.lvs.report b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.lvs.report
new file mode 100644
index 0000000..397bdad
--- /dev/null
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__isobufsrc_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__isobufsrc_1.sp ('sky130_fd_sc_lp__isobufsrc_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.spice ('sky130_fd_sc_lp__isobufsrc_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__isobufsrc_1 sky130_fd_sc_lp__isobufsrc_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__isobufsrc_1
+SOURCE CELL NAME: sky130_fd_sc_lp__isobufsrc_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pex.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pex.spice
index 6c202ba..afb83bb 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pex.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_1.pex.spice
-* Created: Fri Aug 28 10:41:36 2020
+* Created: Wed Sep 2 09:58:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pxi.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pxi.spice
index cc28895..841e45d 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pxi.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_1.pxi.spice
-* Created: Fri Aug 28 10:41:36 2020
+* Created: Wed Sep 2 09:58:29 2020
*
x_PM_SKY130_FD_SC_LP__ISOBUFSRC_1%A N_A_M1002_g N_A_c_43_n N_A_M1003_g A A
+ PM_SKY130_FD_SC_LP__ISOBUFSRC_1%A
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.spice
index b0dae28..fc2ba8b 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_1.spice
-* Created: Fri Aug 28 10:41:36 2020
+* Created: Wed Sep 2 09:58:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.lvs.report b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.lvs.report
new file mode 100644
index 0000000..a2e3cdd
--- /dev/null
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__isobufsrc_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__isobufsrc_2.sp ('sky130_fd_sc_lp__isobufsrc_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.spice ('sky130_fd_sc_lp__isobufsrc_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__isobufsrc_2 sky130_fd_sc_lp__isobufsrc_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__isobufsrc_2
+SOURCE CELL NAME: sky130_fd_sc_lp__isobufsrc_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pex.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pex.spice
index 493d088..eb54b39 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pex.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_2.pex.spice
-* Created: Fri Aug 28 10:41:49 2020
+* Created: Wed Sep 2 09:58:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pxi.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pxi.spice
index 8bf6f0b..60424c0 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pxi.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_2.pxi.spice
-* Created: Fri Aug 28 10:41:49 2020
+* Created: Wed Sep 2 09:58:36 2020
*
x_PM_SKY130_FD_SC_LP__ISOBUFSRC_2%A N_A_c_55_n N_A_M1001_g N_A_M1003_g A
+ N_A_c_58_n PM_SKY130_FD_SC_LP__ISOBUFSRC_2%A
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.spice
index 9912a5f..b0fd043 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_2.spice
-* Created: Fri Aug 28 10:41:49 2020
+* Created: Wed Sep 2 09:58:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.lvs.report b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.lvs.report
new file mode 100644
index 0000000..03aff76
--- /dev/null
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__isobufsrc_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__isobufsrc_4.sp ('sky130_fd_sc_lp__isobufsrc_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.spice ('sky130_fd_sc_lp__isobufsrc_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__isobufsrc_4 sky130_fd_sc_lp__isobufsrc_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__isobufsrc_4
+SOURCE CELL NAME: sky130_fd_sc_lp__isobufsrc_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A SLEEP VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pex.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pex.spice
index f130060..88e195b 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pex.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_4.pex.spice
-* Created: Fri Aug 28 10:41:58 2020
+* Created: Wed Sep 2 09:58:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pxi.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pxi.spice
index ba3e80a..67f7c96 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pxi.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_4.pxi.spice
-* Created: Fri Aug 28 10:41:58 2020
+* Created: Wed Sep 2 09:58:43 2020
*
x_PM_SKY130_FD_SC_LP__ISOBUFSRC_4%A N_A_M1012_g N_A_M1013_g N_A_c_85_n
+ N_A_c_86_n A N_A_c_87_n PM_SKY130_FD_SC_LP__ISOBUFSRC_4%A
diff --git a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.spice b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.spice
index 3f3360b..c1ee2d9 100644
--- a/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.spice
+++ b/cells/isobufsrc/sky130_fd_sc_lp__isobufsrc_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isobufsrc_4.spice
-* Created: Fri Aug 28 10:41:58 2020
+* Created: Wed Sep 2 09:58:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.lvs.report b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.lvs.report
new file mode 100644
index 0000000..30fce71
--- /dev/null
+++ b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__isolatch_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__isolatch_lp.sp ('sky130_fd_sc_lp__isolatch_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.spice ('sky130_fd_sc_lp__isolatch_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__isolatch_lp sky130_fd_sc_lp__isolatch_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__isolatch_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__isolatch_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 12 12
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 12 12 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pex.spice b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pex.spice
index 32613a0..e048d8c 100644
--- a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pex.spice
+++ b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isolatch_lp.pex.spice
-* Created: Fri Aug 28 10:42:08 2020
+* Created: Wed Sep 2 09:58:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pxi.spice b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pxi.spice
index 80a1e10..0487cee 100644
--- a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pxi.spice
+++ b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isolatch_lp.pxi.spice
-* Created: Fri Aug 28 10:42:08 2020
+* Created: Wed Sep 2 09:58:50 2020
*
x_PM_SKY130_FD_SC_LP__ISOLATCH_LP%D N_D_M1001_g N_D_M1010_g N_D_c_141_n
+ N_D_c_145_n N_D_c_146_n N_D_c_147_n D D N_D_c_143_n
diff --git a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.spice b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.spice
index e3c86af..4bb5023 100644
--- a/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.spice
+++ b/cells/isolatch/sky130_fd_sc_lp__isolatch_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__isolatch_lp.spice
-* Created: Fri Aug 28 10:42:08 2020
+* Created: Wed Sep 2 09:58:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.lvs.report b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.lvs.report
new file mode 100644
index 0000000..4984c44
--- /dev/null
+++ b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__lsbuf_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__lsbuf_lp.sp ('sky130_fd_sc_lp__lsbuf_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.spice ('sky130_fd_sc_lp__lsbuf_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:58:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__lsbuf_lp sky130_fd_sc_lp__lsbuf_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__lsbuf_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__lsbuf_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 18 18
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 18 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 2 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VGND VPB DESTVPB A VPWR DESTPWR X
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pex.spice b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pex.spice
index 96167f5..a6b10cd 100644
--- a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pex.spice
+++ b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbuf_lp.pex.spice
-* Created: Fri Aug 28 10:42:16 2020
+* Created: Wed Sep 2 09:58:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pxi.spice b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pxi.spice
index 48e8e0d..6dfec36 100644
--- a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pxi.spice
+++ b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbuf_lp.pxi.spice
-* Created: Fri Aug 28 10:42:16 2020
+* Created: Wed Sep 2 09:58:57 2020
*
x_PM_SKY130_FD_SC_LP__LSBUF_LP%VGND N_VGND_M1011_s N_VGND_M1005_d N_VGND_M1000_s
+ N_VGND_M1011_b N_VGND_c_17_p N_VGND_c_21_p N_VGND_c_7_p N_VGND_c_18_p VGND
diff --git a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.spice b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.spice
index 2f8041f..e9815ab 100644
--- a/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.spice
+++ b/cells/lsbuf/sky130_fd_sc_lp__lsbuf_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbuf_lp.spice
-* Created: Fri Aug 28 10:42:16 2020
+* Created: Wed Sep 2 09:58:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.lvs.report b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.lvs.report
new file mode 100644
index 0000000..118b25c
--- /dev/null
+++ b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__lsbufiso0p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__lsbufiso0p_lp.sp ('sky130_fd_sc_lp__lsbufiso0p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.spice ('sky130_fd_sc_lp__lsbufiso0p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__lsbufiso0p_lp sky130_fd_sc_lp__lsbufiso0p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__lsbufiso0p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__lsbufiso0p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 25 25
+
+ Instances: 13 13 MN (4 pins)
+ 11 11 MP (4 pins)
+ 2 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 26 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 13 13
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 13 13 0 0
+
+
+o Statistics:
+
+ 2 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VGND VPB DESTVPB A SLEEP VPWR DESTPWR X
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pex.spice b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pex.spice
index 3fe2e69..a994263 100644
--- a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pex.spice
+++ b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso0p_lp.pex.spice
-* Created: Fri Aug 28 10:42:23 2020
+* Created: Wed Sep 2 09:59:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pxi.spice b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pxi.spice
index 199a6dd..1920ddd 100644
--- a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pxi.spice
+++ b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso0p_lp.pxi.spice
-* Created: Fri Aug 28 10:42:23 2020
+* Created: Wed Sep 2 09:59:04 2020
*
x_PM_SKY130_FD_SC_LP__LSBUFISO0P_LP%VGND N_VGND_M1017_s N_VGND_M1022_d
+ N_VGND_M1018_s N_VGND_M1014_d N_VGND_M1017_b N_VGND_c_12_p N_VGND_c_7_p
diff --git a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.spice b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.spice
index 3689648..a726822 100644
--- a/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.spice
+++ b/cells/lsbufiso0p/sky130_fd_sc_lp__lsbufiso0p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso0p_lp.spice
-* Created: Fri Aug 28 10:42:23 2020
+* Created: Wed Sep 2 09:59:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.lvs.report b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.lvs.report
new file mode 100644
index 0000000..b696885
--- /dev/null
+++ b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__lsbufiso1p_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__lsbufiso1p_lp.sp ('sky130_fd_sc_lp__lsbufiso1p_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.spice ('sky130_fd_sc_lp__lsbufiso1p_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__lsbufiso1p_lp sky130_fd_sc_lp__lsbufiso1p_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__lsbufiso1p_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__lsbufiso1p_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 25 25
+
+ Instances: 11 11 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 26 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 6 6 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 13 13
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 6 6 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 13 13 0 0
+
+
+o Statistics:
+
+ 2 layout instances were filtered and their pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VGND VPB DESTVPB A SLEEP VPWR DESTPWR X
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pex.spice b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pex.spice
index 2c93a3a..0a16f36 100644
--- a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pex.spice
+++ b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso1p_lp.pex.spice
-* Created: Fri Aug 28 10:42:31 2020
+* Created: Wed Sep 2 09:59:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pxi.spice b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pxi.spice
index 789d496..21d80ea 100644
--- a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pxi.spice
+++ b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso1p_lp.pxi.spice
-* Created: Fri Aug 28 10:42:31 2020
+* Created: Wed Sep 2 09:59:10 2020
*
x_PM_SKY130_FD_SC_LP__LSBUFISO1P_LP%VGND N_VGND_M1014_s N_VGND_M1023_d
+ N_VGND_M1018_s N_VGND_M1012_s N_VGND_M1014_b N_VGND_c_12_p N_VGND_c_109_p
diff --git a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.spice b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.spice
index cfcf88c..83aba8e 100644
--- a/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.spice
+++ b/cells/lsbufiso1p/sky130_fd_sc_lp__lsbufiso1p_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__lsbufiso1p_lp.spice
-* Created: Fri Aug 28 10:42:31 2020
+* Created: Wed Sep 2 09:59:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_0.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_0.lvs.report
new file mode 100644
index 0000000..7c3425e
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_0.sp ('sky130_fd_sc_lp__maj3_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_0.spice ('sky130_fd_sc_lp__maj3_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_0 sky130_fd_sc_lp__maj3_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_0
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_0.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_0.pex.spice
index 37d33dc..28d3c44 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_0.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_0.pex.spice
-* Created: Fri Aug 28 10:42:39 2020
+* Created: Wed Sep 2 09:59:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_0.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_0.pxi.spice
index d2c7d16..7208694 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_0.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_0.pxi.spice
-* Created: Fri Aug 28 10:42:39 2020
+* Created: Wed Sep 2 09:59:17 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_0%A N_A_c_75_n N_A_M1012_g N_A_M1010_g N_A_c_70_n
+ N_A_M1001_g N_A_M1008_g N_A_c_78_n A A N_A_c_73_n N_A_c_74_n
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_0.spice b/cells/maj3/sky130_fd_sc_lp__maj3_0.spice
index 24ebaad..f42cbb9 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_0.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_0.spice
-* Created: Fri Aug 28 10:42:39 2020
+* Created: Wed Sep 2 09:59:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_1.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_1.lvs.report
new file mode 100644
index 0000000..29b86d4
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_1.sp ('sky130_fd_sc_lp__maj3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_1.spice ('sky130_fd_sc_lp__maj3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_1 sky130_fd_sc_lp__maj3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_1.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_1.pex.spice
index d2654f2..c650587 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_1.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_1.pex.spice
-* Created: Fri Aug 28 10:42:53 2020
+* Created: Wed Sep 2 09:59:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_1.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_1.pxi.spice
index d96eacc..cfe0298 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_1.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_1.pxi.spice
-* Created: Fri Aug 28 10:42:53 2020
+* Created: Wed Sep 2 09:59:24 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_1%A N_A_M1002_g N_A_M1003_g N_A_M1013_g N_A_M1006_g A
+ A N_A_c_71_n PM_SKY130_FD_SC_LP__MAJ3_1%A
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_1.spice b/cells/maj3/sky130_fd_sc_lp__maj3_1.spice
index 464c569..746df6a 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_1.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_1.spice
-* Created: Fri Aug 28 10:42:53 2020
+* Created: Wed Sep 2 09:59:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_2.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_2.lvs.report
new file mode 100644
index 0000000..3a5eddd
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_2.sp ('sky130_fd_sc_lp__maj3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_2.spice ('sky130_fd_sc_lp__maj3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_2 sky130_fd_sc_lp__maj3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_2
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_2.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_2.pex.spice
index 208374b..9e08d03 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_2.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_2.pex.spice
-* Created: Fri Aug 28 10:43:01 2020
+* Created: Wed Sep 2 09:59:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_2.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_2.pxi.spice
index 6351b79..7715bbb 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_2.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_2.pxi.spice
-* Created: Fri Aug 28 10:43:01 2020
+* Created: Wed Sep 2 09:59:31 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_2%C N_C_M1008_g N_C_M1002_g N_C_M1011_g N_C_M1015_g
+ N_C_c_82_n N_C_c_89_n N_C_c_83_n N_C_c_84_n N_C_c_91_n C C N_C_c_93_n
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_2.spice b/cells/maj3/sky130_fd_sc_lp__maj3_2.spice
index e9471bd..edf874f 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_2.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_2.spice
-* Created: Fri Aug 28 10:43:01 2020
+* Created: Wed Sep 2 09:59:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_4.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_4.lvs.report
new file mode 100644
index 0000000..d2b29aa
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_4.sp ('sky130_fd_sc_lp__maj3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_4.spice ('sky130_fd_sc_lp__maj3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_4 sky130_fd_sc_lp__maj3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_4
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_4.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_4.pex.spice
index bfbc3d9..6b94a4e 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_4.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_4.pex.spice
-* Created: Fri Aug 28 10:43:11 2020
+* Created: Wed Sep 2 09:59:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_4.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_4.pxi.spice
index db6d2e4..72f58d2 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_4.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_4.pxi.spice
-* Created: Fri Aug 28 10:43:11 2020
+* Created: Wed Sep 2 09:59:38 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_4%C N_C_M1002_g N_C_M1014_g N_C_M1016_g N_C_M1019_g
+ N_C_c_97_n N_C_c_112_p N_C_c_133_p N_C_c_98_n N_C_c_99_n N_C_c_100_n C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_4.spice b/cells/maj3/sky130_fd_sc_lp__maj3_4.spice
index 5446bcd..2adafcf 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_4.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_4.spice
-* Created: Fri Aug 28 10:43:11 2020
+* Created: Wed Sep 2 09:59:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_lp.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_lp.lvs.report
new file mode 100644
index 0000000..5a18c06
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_lp.sp ('sky130_fd_sc_lp__maj3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_lp.spice ('sky130_fd_sc_lp__maj3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_lp sky130_fd_sc_lp__maj3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_lp.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_lp.pex.spice
index 51d9787..ef40413 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_lp.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_lp.pex.spice
-* Created: Fri Aug 28 10:43:18 2020
+* Created: Wed Sep 2 09:59:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_lp.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_lp.pxi.spice
index e257d5f..b0b3c48 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_lp.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_lp.pxi.spice
-* Created: Fri Aug 28 10:43:18 2020
+* Created: Wed Sep 2 09:59:44 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_LP%A N_A_M1013_g N_A_M1010_g N_A_M1012_g N_A_M1014_g
+ A A N_A_c_85_n PM_SKY130_FD_SC_LP__MAJ3_LP%A
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_lp.spice b/cells/maj3/sky130_fd_sc_lp__maj3_lp.spice
index 07a44e5..6e24b20 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_lp.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_lp.spice
-* Created: Fri Aug 28 10:43:18 2020
+* Created: Wed Sep 2 09:59:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_m.lvs.report b/cells/maj3/sky130_fd_sc_lp__maj3_m.lvs.report
new file mode 100644
index 0000000..60f774e
--- /dev/null
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__maj3_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__maj3_m.sp ('sky130_fd_sc_lp__maj3_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/maj3/sky130_fd_sc_lp__maj3_m.spice ('sky130_fd_sc_lp__maj3_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__maj3_m sky130_fd_sc_lp__maj3_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__maj3_m
+SOURCE CELL NAME: sky130_fd_sc_lp__maj3_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_m.pex.spice b/cells/maj3/sky130_fd_sc_lp__maj3_m.pex.spice
index 04ffe70..3b7b979 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_m.pex.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_m.pex.spice
-* Created: Fri Aug 28 10:43:26 2020
+* Created: Wed Sep 2 09:59:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_m.pxi.spice b/cells/maj3/sky130_fd_sc_lp__maj3_m.pxi.spice
index 54fe552..97f0a45 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_m.pxi.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_m.pxi.spice
-* Created: Fri Aug 28 10:43:26 2020
+* Created: Wed Sep 2 09:59:51 2020
*
x_PM_SKY130_FD_SC_LP__MAJ3_M%A N_A_M1013_g N_A_M1010_g N_A_M1007_g N_A_M1002_g A
+ A N_A_c_72_n PM_SKY130_FD_SC_LP__MAJ3_M%A
diff --git a/cells/maj3/sky130_fd_sc_lp__maj3_m.spice b/cells/maj3/sky130_fd_sc_lp__maj3_m.spice
index 9fc9198..04089bc 100644
--- a/cells/maj3/sky130_fd_sc_lp__maj3_m.spice
+++ b/cells/maj3/sky130_fd_sc_lp__maj3_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__maj3_m.spice
-* Created: Fri Aug 28 10:43:26 2020
+* Created: Wed Sep 2 09:59:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_0.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_0.lvs.report
new file mode 100644
index 0000000..dad1312
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_0.sp ('sky130_fd_sc_lp__mux2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_0.spice ('sky130_fd_sc_lp__mux2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 09:59:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_0 sky130_fd_sc_lp__mux2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_0.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_0.pex.spice
index b70943c..cf57e0b 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_0.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_0.pex.spice
-* Created: Fri Aug 28 10:43:33 2020
+* Created: Wed Sep 2 09:59:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_0.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_0.pxi.spice
index b0e83a5..b2fa25b 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_0.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_0.pxi.spice
-* Created: Fri Aug 28 10:43:33 2020
+* Created: Wed Sep 2 09:59:58 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_0%A_89_200# N_A_89_200#_M1008_d N_A_89_200#_M1005_d
+ N_A_89_200#_M1001_g N_A_89_200#_M1009_g N_A_89_200#_c_87_n N_A_89_200#_c_88_n
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_0.spice b/cells/mux2/sky130_fd_sc_lp__mux2_0.spice
index de1ea16..68b6b55 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_0.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_0.spice
-* Created: Fri Aug 28 10:43:33 2020
+* Created: Wed Sep 2 09:59:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_1.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_1.lvs.report
new file mode 100644
index 0000000..4f0dd37
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_1.sp ('sky130_fd_sc_lp__mux2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_1.spice ('sky130_fd_sc_lp__mux2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_1 sky130_fd_sc_lp__mux2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_1.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_1.pex.spice
index 83af4e4..09a8979 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_1.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_1.pex.spice
-* Created: Fri Aug 28 10:43:41 2020
+* Created: Wed Sep 2 10:00:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_1.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_1.pxi.spice
index 6f5cfaf..c63275b 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_1.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_1.pxi.spice
-* Created: Fri Aug 28 10:43:41 2020
+* Created: Wed Sep 2 10:00:05 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_1%A_105_22# N_A_105_22#_M1001_d N_A_105_22#_M1005_d
+ N_A_105_22#_M1002_g N_A_105_22#_M1006_g N_A_105_22#_c_71_n N_A_105_22#_c_72_n
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_1.spice b/cells/mux2/sky130_fd_sc_lp__mux2_1.spice
index 99545ad..7544a47 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_1.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_1.spice
-* Created: Fri Aug 28 10:43:41 2020
+* Created: Wed Sep 2 10:00:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_2.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_2.lvs.report
new file mode 100644
index 0000000..6318bc1
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_2.sp ('sky130_fd_sc_lp__mux2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_2.spice ('sky130_fd_sc_lp__mux2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_2 sky130_fd_sc_lp__mux2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 S VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_2.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_2.pex.spice
index 2653e0d..8f28e01 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_2.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_2.pex.spice
-* Created: Fri Aug 28 10:43:55 2020
+* Created: Wed Sep 2 10:00:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_2.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_2.pxi.spice
index d1b1a82..d691c53 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_2.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_2.pxi.spice
-* Created: Fri Aug 28 10:43:55 2020
+* Created: Wed Sep 2 10:00:12 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_2%A_86_21# N_A_86_21#_M1013_d N_A_86_21#_M1010_d
+ N_A_86_21#_M1007_g N_A_86_21#_M1006_g N_A_86_21#_M1008_g N_A_86_21#_M1011_g
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_2.spice b/cells/mux2/sky130_fd_sc_lp__mux2_2.spice
index 6a56fdc..6d21e68 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_2.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_2.spice
-* Created: Fri Aug 28 10:43:55 2020
+* Created: Wed Sep 2 10:00:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_4.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_4.lvs.report
new file mode 100644
index 0000000..95b3563
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_4.sp ('sky130_fd_sc_lp__mux2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_4.spice ('sky130_fd_sc_lp__mux2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_4 sky130_fd_sc_lp__mux2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_4.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_4.pex.spice
index bf18341..f676db0 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_4.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_4.pex.spice
-* Created: Fri Aug 28 10:44:04 2020
+* Created: Wed Sep 2 10:00:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_4.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_4.pxi.spice
index b3115b8..0824ee2 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_4.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_4.pxi.spice
-* Created: Fri Aug 28 10:44:04 2020
+* Created: Wed Sep 2 10:00:19 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_4%S N_S_c_101_n N_S_M1013_g N_S_c_102_n N_S_M1007_g
+ N_S_c_103_n N_S_M1004_g N_S_M1009_g N_S_c_110_n N_S_c_111_n N_S_c_112_n S S
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_4.spice b/cells/mux2/sky130_fd_sc_lp__mux2_4.spice
index 7cf3f50..bfc666e 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_4.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_4.spice
-* Created: Fri Aug 28 10:44:04 2020
+* Created: Wed Sep 2 10:00:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_8.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_8.lvs.report
new file mode 100644
index 0000000..7bb2316
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_8.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_8.sp ('sky130_fd_sc_lp__mux2_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_8.spice ('sky130_fd_sc_lp__mux2_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_8 sky130_fd_sc_lp__mux2_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_8
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 10.
+ 22 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 10.
+ 22 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_8.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_8.pex.spice
index 84b372b..dd72806 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_8.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_8.pex.spice
-* Created: Fri Aug 28 10:44:13 2020
+* Created: Wed Sep 2 10:00:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_8.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_8.pxi.spice
index 4678e51..7f8a538 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_8.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_8.pxi.spice
-* Created: Fri Aug 28 10:44:13 2020
+* Created: Wed Sep 2 10:00:26 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_8%A_84_21# N_A_84_21#_M1016_s N_A_84_21#_M1008_s
+ N_A_84_21#_M1002_s N_A_84_21#_M1017_d N_A_84_21#_M1004_g N_A_84_21#_M1006_g
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_8.spice b/cells/mux2/sky130_fd_sc_lp__mux2_8.spice
index 19b07e5..75c096a 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_8.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_8.spice
-* Created: Fri Aug 28 10:44:13 2020
+* Created: Wed Sep 2 10:00:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_lp.lvs.report
new file mode 100644
index 0000000..07aa575
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_lp.sp ('sky130_fd_sc_lp__mux2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_lp.spice ('sky130_fd_sc_lp__mux2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_lp sky130_fd_sc_lp__mux2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A0 S X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp.pex.spice
index c3e7af0..ecdb269 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp.pex.spice
-* Created: Fri Aug 28 10:44:29 2020
+* Created: Wed Sep 2 10:00:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp.pxi.spice
index 7cf738e..b9846ec 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp.pxi.spice
-* Created: Fri Aug 28 10:44:29 2020
+* Created: Wed Sep 2 10:00:40 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_LP%A_84_29# N_A_84_29#_M1006_d N_A_84_29#_M1001_d
+ N_A_84_29#_M1009_g N_A_84_29#_c_92_n N_A_84_29#_c_103_n N_A_84_29#_M1000_g
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp.spice
index 03abc49..bdb2335 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp.spice
-* Created: Fri Aug 28 10:44:29 2020
+* Created: Wed Sep 2 10:00:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.lvs.report
new file mode 100644
index 0000000..42b7109
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_lp2.sp ('sky130_fd_sc_lp__mux2_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_lp2.spice ('sky130_fd_sc_lp__mux2_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_lp2 sky130_fd_sc_lp__mux2_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A0 S X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pex.spice
index a9f94df..c12cb58 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp2.pex.spice
-* Created: Fri Aug 28 10:44:21 2020
+* Created: Wed Sep 2 10:00:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pxi.spice
index 39d46db..5cd6a8d 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp2.pxi.spice
-* Created: Fri Aug 28 10:44:21 2020
+* Created: Wed Sep 2 10:00:33 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_LP2%A_84_259# N_A_84_259#_M1006_d N_A_84_259#_M1003_d
+ N_A_84_259#_c_76_n N_A_84_259#_M1010_g N_A_84_259#_M1001_g N_A_84_259#_M1007_g
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.spice b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.spice
index 6ab29be..3bc6bf8 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_lp2.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_lp2.spice
-* Created: Fri Aug 28 10:44:21 2020
+* Created: Wed Sep 2 10:00:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_m.lvs.report b/cells/mux2/sky130_fd_sc_lp__mux2_m.lvs.report
new file mode 100644
index 0000000..2d04587
--- /dev/null
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2_m.sp ('sky130_fd_sc_lp__mux2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2/sky130_fd_sc_lp__mux2_m.spice ('sky130_fd_sc_lp__mux2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2_m sky130_fd_sc_lp__mux2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_m.pex.spice b/cells/mux2/sky130_fd_sc_lp__mux2_m.pex.spice
index 3ecc4e4..922f383 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_m.pex.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_m.pex.spice
-* Created: Fri Aug 28 10:44:36 2020
+* Created: Wed Sep 2 10:00:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_m.pxi.spice b/cells/mux2/sky130_fd_sc_lp__mux2_m.pxi.spice
index 5a54d2d..0f96f2f 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_m.pxi.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_m.pxi.spice
-* Created: Fri Aug 28 10:44:36 2020
+* Created: Wed Sep 2 10:00:47 2020
*
x_PM_SKY130_FD_SC_LP__MUX2_M%A_123_269# N_A_123_269#_M1004_d
+ N_A_123_269#_M1001_d N_A_123_269#_M1010_g N_A_123_269#_M1000_g
diff --git a/cells/mux2/sky130_fd_sc_lp__mux2_m.spice b/cells/mux2/sky130_fd_sc_lp__mux2_m.spice
index 281973b..65f5774 100644
--- a/cells/mux2/sky130_fd_sc_lp__mux2_m.spice
+++ b/cells/mux2/sky130_fd_sc_lp__mux2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2_m.spice
-* Created: Fri Aug 28 10:44:36 2020
+* Created: Wed Sep 2 10:00:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.lvs.report
new file mode 100644
index 0000000..96d7656
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_0.sp ('sky130_fd_sc_lp__mux2i_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_0.spice ('sky130_fd_sc_lp__mux2i_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_0 sky130_fd_sc_lp__mux2i_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_0
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pex.spice
index 6058ce9..5e2889b 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_0.pex.spice
-* Created: Fri Aug 28 10:44:45 2020
+* Created: Wed Sep 2 10:00:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pxi.spice
index dd4ffbe..bbe2893 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_0.pxi.spice
-* Created: Fri Aug 28 10:44:45 2020
+* Created: Wed Sep 2 10:00:55 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_0%S N_S_M1006_g N_S_M1002_g N_S_c_68_n N_S_M1003_g
+ N_S_M1004_g N_S_c_69_n N_S_c_77_n N_S_c_78_n N_S_c_111_p N_S_c_124_p
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.spice
index 9c845e7..7dbc1ea 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_0.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_0.spice
-* Created: Fri Aug 28 10:44:45 2020
+* Created: Wed Sep 2 10:00:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.lvs.report
new file mode 100644
index 0000000..11b5520
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_1.sp ('sky130_fd_sc_lp__mux2i_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_1.spice ('sky130_fd_sc_lp__mux2i_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:00:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_1 sky130_fd_sc_lp__mux2i_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_1
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 S Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pex.spice
index d8d9863..f37e10e 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_1.pex.spice
-* Created: Fri Aug 28 10:44:59 2020
+* Created: Wed Sep 2 10:01:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pxi.spice
index 62a26b1..99efb5a 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_1.pxi.spice
-* Created: Fri Aug 28 10:44:59 2020
+* Created: Wed Sep 2 10:01:02 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_1%A0 N_A0_M1005_g N_A0_M1002_g A0 N_A0_c_66_n
+ N_A0_c_67_n PM_SKY130_FD_SC_LP__MUX2I_1%A0
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.spice
index d99655d..d414a39 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_1.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_1.spice
-* Created: Fri Aug 28 10:44:59 2020
+* Created: Wed Sep 2 10:01:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.lvs.report
new file mode 100644
index 0000000..d269527
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_2.sp ('sky130_fd_sc_lp__mux2i_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_2.spice ('sky130_fd_sc_lp__mux2i_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_2 sky130_fd_sc_lp__mux2i_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_2
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pex.spice
index 4844384..0c984a0 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_2.pex.spice
-* Created: Fri Aug 28 10:45:08 2020
+* Created: Wed Sep 2 10:01:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pxi.spice
index 7c1174b..720db97 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_2.pxi.spice
-* Created: Fri Aug 28 10:45:08 2020
+* Created: Wed Sep 2 10:01:10 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_2%S N_S_M1006_g N_S_M1012_g N_S_M1003_g N_S_M1004_g
+ N_S_M1010_g N_S_M1014_g N_S_c_135_p N_S_c_91_n N_S_c_100_n N_S_c_92_n
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.spice
index dafb2a8..adaa6bb 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_2.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_2.spice
-* Created: Fri Aug 28 10:45:08 2020
+* Created: Wed Sep 2 10:01:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.lvs.report
new file mode 100644
index 0000000..4b8220c
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_4.sp ('sky130_fd_sc_lp__mux2i_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_4.spice ('sky130_fd_sc_lp__mux2i_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_4 sky130_fd_sc_lp__mux2i_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_4
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A0 A1 S Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pex.spice
index 884b0ca..fe2f1a0 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_4.pex.spice
-* Created: Fri Aug 28 10:45:18 2020
+* Created: Wed Sep 2 10:01:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pxi.spice
index 27bd980..ae79739 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_4.pxi.spice
-* Created: Fri Aug 28 10:45:18 2020
+* Created: Wed Sep 2 10:01:17 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_4%A0 N_A0_M1005_g N_A0_M1001_g N_A0_M1020_g
+ N_A0_M1014_g N_A0_M1024_g N_A0_M1016_g N_A0_M1029_g N_A0_M1025_g A0 A0 A0
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.spice
index dc6fcd6..c828916 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_4.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_4.spice
-* Created: Fri Aug 28 10:45:18 2020
+* Created: Wed Sep 2 10:01:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.lvs.report
new file mode 100644
index 0000000..4cba361
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_lp.sp ('sky130_fd_sc_lp__mux2i_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.spice ('sky130_fd_sc_lp__mux2i_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_lp sky130_fd_sc_lp__mux2i_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 3 3 SMN2 (4 pins)
+ 3 3 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 3 3 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pex.spice
index ff28700..870866b 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp.pex.spice
-* Created: Fri Aug 28 10:45:33 2020
+* Created: Wed Sep 2 10:01:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pxi.spice
index 633bfb9..7c425c8 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp.pxi.spice
-* Created: Fri Aug 28 10:45:33 2020
+* Created: Wed Sep 2 10:01:30 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_LP%S N_S_c_70_n N_S_c_85_n N_S_c_86_n N_S_M1001_g
+ N_S_M1010_g N_S_c_72_n N_S_M1003_g N_S_M1011_g N_S_M1000_g N_S_c_75_n
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.spice
index e3a520a..992bbf5 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp.spice
-* Created: Fri Aug 28 10:45:33 2020
+* Created: Wed Sep 2 10:01:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.lvs.report
new file mode 100644
index 0000000..a3d948c
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_lp2.sp ('sky130_fd_sc_lp__mux2i_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.spice ('sky130_fd_sc_lp__mux2i_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_lp2 sky130_fd_sc_lp__mux2i_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A0 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pex.spice
index bbdc1f8..43fa276 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp2.pex.spice
-* Created: Fri Aug 28 10:45:25 2020
+* Created: Wed Sep 2 10:01:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pxi.spice
index c473be2..39979bf 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp2.pxi.spice
-* Created: Fri Aug 28 10:45:25 2020
+* Created: Wed Sep 2 10:01:24 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_LP2%S N_S_M1006_g N_S_c_72_n N_S_c_73_n N_S_M1005_g
+ N_S_c_75_n N_S_M1000_g N_S_c_76_n N_S_M1003_g N_S_c_78_n N_S_M1009_g
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.spice
index 0d7de97..1ffb966 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_lp2.spice
-* Created: Fri Aug 28 10:45:25 2020
+* Created: Wed Sep 2 10:01:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.lvs.report b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.lvs.report
new file mode 100644
index 0000000..808081c
--- /dev/null
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux2i_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux2i_m.sp ('sky130_fd_sc_lp__mux2i_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux2i/sky130_fd_sc_lp__mux2i_m.spice ('sky130_fd_sc_lp__mux2i_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux2i_m sky130_fd_sc_lp__mux2i_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux2i_m
+SOURCE CELL NAME: sky130_fd_sc_lp__mux2i_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S A1 A0 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pex.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pex.spice
index b691319..370914a 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pex.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_m.pex.spice
-* Created: Fri Aug 28 10:45:41 2020
+* Created: Wed Sep 2 10:01:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pxi.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pxi.spice
index 37317f9..539e33b 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pxi.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_m.pxi.spice
-* Created: Fri Aug 28 10:45:41 2020
+* Created: Wed Sep 2 10:01:37 2020
*
x_PM_SKY130_FD_SC_LP__MUX2I_M%S N_S_M1004_g N_S_M1005_g N_S_c_76_n N_S_M1000_g
+ N_S_c_83_n N_S_M1003_g N_S_c_77_n N_S_c_78_n N_S_c_85_n N_S_c_86_n N_S_c_87_n
diff --git a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.spice b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.spice
index d142f02..19e58b9 100644
--- a/cells/mux2i/sky130_fd_sc_lp__mux2i_m.spice
+++ b/cells/mux2i/sky130_fd_sc_lp__mux2i_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux2i_m.spice
-* Created: Fri Aug 28 10:45:41 2020
+* Created: Wed Sep 2 10:01:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_0.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_0.lvs.report
new file mode 100644
index 0000000..b67f77a
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_0.sp ('sky130_fd_sc_lp__mux4_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_0.spice ('sky130_fd_sc_lp__mux4_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_0 sky130_fd_sc_lp__mux4_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_0
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 S0 A3 A1 A0 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_0.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_0.pex.spice
index 1e64309..422c689 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_0.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_0.pex.spice
-* Created: Fri Aug 28 10:45:49 2020
+* Created: Wed Sep 2 10:01:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_0.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_0.pxi.spice
index f3180ad..90f876f 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_0.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_0.pxi.spice
-* Created: Fri Aug 28 10:45:49 2020
+* Created: Wed Sep 2 10:01:45 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_0%A2 N_A2_c_177_n N_A2_c_178_n N_A2_M1017_g
+ N_A2_M1015_g N_A2_c_176_n A2 N_A2_c_181_n PM_SKY130_FD_SC_LP__MUX4_0%A2
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_0.spice b/cells/mux4/sky130_fd_sc_lp__mux4_0.spice
index af16ce1..be39b4e 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_0.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_0.spice
-* Created: Fri Aug 28 10:45:49 2020
+* Created: Wed Sep 2 10:01:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_1.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_1.lvs.report
new file mode 100644
index 0000000..78820e0
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_1.sp ('sky130_fd_sc_lp__mux4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_1.spice ('sky130_fd_sc_lp__mux4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_1 sky130_fd_sc_lp__mux4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_1
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A0 S0 A3 A2 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_1.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_1.pex.spice
index 9a537aa..25cedb3 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_1.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_1.pex.spice
-* Created: Fri Aug 28 10:46:03 2020
+* Created: Wed Sep 2 10:01:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_1.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_1.pxi.spice
index 4c733cc..33715c2 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_1.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_1.pxi.spice
-* Created: Fri Aug 28 10:46:03 2020
+* Created: Wed Sep 2 10:01:52 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_1%A1 N_A1_c_219_n N_A1_M1000_g N_A1_M1014_g
+ N_A1_c_225_n A1 A1 A1 N_A1_c_222_n PM_SKY130_FD_SC_LP__MUX4_1%A1
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_1.spice b/cells/mux4/sky130_fd_sc_lp__mux4_1.spice
index 7fb7d0f..40e2fb4 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_1.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_1.spice
-* Created: Fri Aug 28 10:46:03 2020
+* Created: Wed Sep 2 10:01:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_2.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_2.lvs.report
new file mode 100644
index 0000000..dc60935
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_2.sp ('sky130_fd_sc_lp__mux4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_2.spice ('sky130_fd_sc_lp__mux4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:01:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_2 sky130_fd_sc_lp__mux4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_2
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S1 A3 A2 A1 A0 S0 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_2.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_2.pex.spice
index 365741f..38fc346 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_2.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_2.pex.spice
-* Created: Fri Aug 28 10:46:12 2020
+* Created: Wed Sep 2 10:01:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_2.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_2.pxi.spice
index 1b70af5..47305c1 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_2.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_2.pxi.spice
-* Created: Fri Aug 28 10:46:12 2020
+* Created: Wed Sep 2 10:01:59 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_2%A_80_293# N_A_80_293#_M1023_s N_A_80_293#_M1025_s
+ N_A_80_293#_M1005_g N_A_80_293#_c_163_n N_A_80_293#_c_164_n
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_2.spice b/cells/mux4/sky130_fd_sc_lp__mux4_2.spice
index 3e97625..17462c0 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_2.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_2.spice
-* Created: Fri Aug 28 10:46:12 2020
+* Created: Wed Sep 2 10:01:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_4.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_4.lvs.report
new file mode 100644
index 0000000..7ce73c8
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_4.sp ('sky130_fd_sc_lp__mux4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_4.spice ('sky130_fd_sc_lp__mux4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_4 sky130_fd_sc_lp__mux4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_4
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S1 A1 A0 A3 A2 S0 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_4.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_4.pex.spice
index fc9ad4b..07d3b0e 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_4.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_4.pex.spice
-* Created: Fri Aug 28 10:46:22 2020
+* Created: Wed Sep 2 10:02:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_4.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_4.pxi.spice
index 2059e71..36126e2 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_4.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_4.pxi.spice
-* Created: Fri Aug 28 10:46:22 2020
+* Created: Wed Sep 2 10:02:07 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_4%A_84_277# N_A_84_277#_M1007_s N_A_84_277#_M1016_s
+ N_A_84_277#_M1031_g N_A_84_277#_c_177_n N_A_84_277#_c_178_n
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_4.spice b/cells/mux4/sky130_fd_sc_lp__mux4_4.spice
index ad4da85..075c02d 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_4.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_4.spice
-* Created: Fri Aug 28 10:46:22 2020
+* Created: Wed Sep 2 10:02:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_lp.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_lp.lvs.report
new file mode 100644
index 0000000..0e3498e
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_lp.sp ('sky130_fd_sc_lp__mux4_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_lp.spice ('sky130_fd_sc_lp__mux4_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_lp sky130_fd_sc_lp__mux4_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 27 27
+
+ Instances: 16 16 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 30 29
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 2 2 MN (4 pins)
+ 5 5 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB S1 A3 S0 A2 A1 A0 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_lp.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_lp.pex.spice
index ccbce9e..b9604bd 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_lp.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_lp.pex.spice
-* Created: Fri Aug 28 10:46:30 2020
+* Created: Wed Sep 2 10:02:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_lp.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_lp.pxi.spice
index 26d8c1e..438dff8 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_lp.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_lp.pxi.spice
-* Created: Fri Aug 28 10:46:30 2020
+* Created: Wed Sep 2 10:02:14 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_LP%A_84_21# N_A_84_21#_M1016_d N_A_84_21#_M1013_d
+ N_A_84_21#_M1006_g N_A_84_21#_M1005_g N_A_84_21#_c_207_n N_A_84_21#_c_208_n
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_lp.spice b/cells/mux4/sky130_fd_sc_lp__mux4_lp.spice
index 33b5737..3b8b060 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_lp.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_lp.spice
-* Created: Fri Aug 28 10:46:30 2020
+* Created: Wed Sep 2 10:02:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_m.lvs.report b/cells/mux4/sky130_fd_sc_lp__mux4_m.lvs.report
new file mode 100644
index 0000000..4ca5152
--- /dev/null
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__mux4_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__mux4_m.sp ('sky130_fd_sc_lp__mux4_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/mux4/sky130_fd_sc_lp__mux4_m.spice ('sky130_fd_sc_lp__mux4_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__mux4_m sky130_fd_sc_lp__mux4_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__mux4_m
+SOURCE CELL NAME: sky130_fd_sc_lp__mux4_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 24 24
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A3 A1 S0 A0 S1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_m.pex.spice b/cells/mux4/sky130_fd_sc_lp__mux4_m.pex.spice
index c88dbb1..873beda 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_m.pex.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_m.pex.spice
-* Created: Fri Aug 28 10:46:37 2020
+* Created: Wed Sep 2 10:02:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_m.pxi.spice b/cells/mux4/sky130_fd_sc_lp__mux4_m.pxi.spice
index 4fc3f67..3b484ef 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_m.pxi.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_m.pxi.spice
-* Created: Fri Aug 28 10:46:37 2020
+* Created: Wed Sep 2 10:02:21 2020
*
x_PM_SKY130_FD_SC_LP__MUX4_M%A2 N_A2_M1001_g N_A2_M1024_g N_A2_c_180_n
+ N_A2_c_181_n A2 A2 A2 A2 N_A2_c_178_n PM_SKY130_FD_SC_LP__MUX4_M%A2
diff --git a/cells/mux4/sky130_fd_sc_lp__mux4_m.spice b/cells/mux4/sky130_fd_sc_lp__mux4_m.spice
index f4d6991..ac57d06 100644
--- a/cells/mux4/sky130_fd_sc_lp__mux4_m.spice
+++ b/cells/mux4/sky130_fd_sc_lp__mux4_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__mux4_m.spice
-* Created: Fri Aug 28 10:46:37 2020
+* Created: Wed Sep 2 10:02:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_0.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_0.lvs.report
new file mode 100644
index 0000000..12c53f7
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_0.sp ('sky130_fd_sc_lp__nand2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_0.spice ('sky130_fd_sc_lp__nand2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_0 sky130_fd_sc_lp__nand2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_0.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_0.pex.spice
index 9699849..33e991d 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_0.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_0.pex.spice
-* Created: Fri Aug 28 10:46:45 2020
+* Created: Wed Sep 2 10:02:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_0.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_0.pxi.spice
index 90dcc16..ff5430e 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_0.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_0.pxi.spice
-* Created: Fri Aug 28 10:46:45 2020
+* Created: Wed Sep 2 10:02:28 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_0%B N_B_c_31_n N_B_M1000_g N_B_M1003_g N_B_c_34_n B
+ B B B N_B_c_36_n PM_SKY130_FD_SC_LP__NAND2_0%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_0.spice b/cells/nand2/sky130_fd_sc_lp__nand2_0.spice
index a06bdd1..627ba8a 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_0.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_0.spice
-* Created: Fri Aug 28 10:46:45 2020
+* Created: Wed Sep 2 10:02:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_1.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_1.lvs.report
new file mode 100644
index 0000000..559d2fc
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_1.sp ('sky130_fd_sc_lp__nand2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_1.spice ('sky130_fd_sc_lp__nand2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_1 sky130_fd_sc_lp__nand2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_1.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_1.pex.spice
index eacb3ad..e919a03 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_1.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_1.pex.spice
-* Created: Fri Aug 28 10:46:53 2020
+* Created: Wed Sep 2 10:02:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_1.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_1.pxi.spice
index 120127f..ed15edf 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_1.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_1.pxi.spice
-* Created: Fri Aug 28 10:46:53 2020
+* Created: Wed Sep 2 10:02:36 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_1%B N_B_M1000_g N_B_M1003_g B B N_B_c_29_n
+ N_B_c_30_n PM_SKY130_FD_SC_LP__NAND2_1%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_1.spice b/cells/nand2/sky130_fd_sc_lp__nand2_1.spice
index 911fab7..a0b7e5a 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_1.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_1.spice
-* Created: Fri Aug 28 10:46:53 2020
+* Created: Wed Sep 2 10:02:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_2.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_2.lvs.report
new file mode 100644
index 0000000..c1b4f38
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_2.sp ('sky130_fd_sc_lp__nand2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_2.spice ('sky130_fd_sc_lp__nand2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_2 sky130_fd_sc_lp__nand2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_2.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_2.pex.spice
index d265be2..dd0505f 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_2.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_2.pex.spice
-* Created: Fri Aug 28 10:47:07 2020
+* Created: Wed Sep 2 10:02:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_2.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_2.pxi.spice
index 4d88c4b..fd04db8 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_2.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_2.pxi.spice
-* Created: Fri Aug 28 10:47:07 2020
+* Created: Wed Sep 2 10:02:43 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_2%B N_B_M1001_g N_B_M1003_g N_B_M1005_g N_B_M1006_g
+ B B N_B_c_46_n PM_SKY130_FD_SC_LP__NAND2_2%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_2.spice b/cells/nand2/sky130_fd_sc_lp__nand2_2.spice
index e4a1319..2ed4aed 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_2.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_2.spice
-* Created: Fri Aug 28 10:47:07 2020
+* Created: Wed Sep 2 10:02:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_4.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_4.lvs.report
new file mode 100644
index 0000000..0d76834
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_4.sp ('sky130_fd_sc_lp__nand2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_4.spice ('sky130_fd_sc_lp__nand2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_4 sky130_fd_sc_lp__nand2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_4.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_4.pex.spice
index 991e3ae..c56a39d 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_4.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_4.pex.spice
-* Created: Fri Aug 28 10:47:16 2020
+* Created: Wed Sep 2 10:02:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_4.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_4.pxi.spice
index 4c8a04d..a55d930 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_4.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_4.pxi.spice
-* Created: Fri Aug 28 10:47:16 2020
+* Created: Wed Sep 2 10:02:50 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_4%B N_B_M1005_g N_B_M1000_g N_B_M1006_g N_B_M1001_g
+ N_B_M1013_g N_B_M1008_g N_B_M1015_g N_B_M1010_g B B B B N_B_c_68_n
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_4.spice b/cells/nand2/sky130_fd_sc_lp__nand2_4.spice
index 6c1e92d..cb99657 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_4.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_4.spice
-* Created: Fri Aug 28 10:47:16 2020
+* Created: Wed Sep 2 10:02:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_8.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_8.lvs.report
new file mode 100644
index 0000000..5d39ae7
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_8.sp ('sky130_fd_sc_lp__nand2_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_8.spice ('sky130_fd_sc_lp__nand2_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:02:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_8 sky130_fd_sc_lp__nand2_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_8
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_8.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_8.pex.spice
index 79cbf50..de10f9e 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_8.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_8.pex.spice
-* Created: Fri Aug 28 10:47:26 2020
+* Created: Wed Sep 2 10:02:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_8.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_8.pxi.spice
index dcd627b..105543e 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_8.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_8.pxi.spice
-* Created: Fri Aug 28 10:47:26 2020
+* Created: Wed Sep 2 10:02:57 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_8%B N_B_M1001_g N_B_M1000_g N_B_M1008_g N_B_M1004_g
+ N_B_M1012_g N_B_M1010_g N_B_M1014_g N_B_M1015_g N_B_M1019_g N_B_M1021_g
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_8.spice b/cells/nand2/sky130_fd_sc_lp__nand2_8.spice
index 84d8a6e..6d26e95 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_8.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_8.spice
-* Created: Fri Aug 28 10:47:26 2020
+* Created: Wed Sep 2 10:02:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_lp.lvs.report
new file mode 100644
index 0000000..00b06cf
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_lp.sp ('sky130_fd_sc_lp__nand2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_lp.spice ('sky130_fd_sc_lp__nand2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_lp sky130_fd_sc_lp__nand2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 1 1 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 1 1 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp.pex.spice
index 33454c0..9e5a154 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp.pex.spice
-* Created: Fri Aug 28 10:47:41 2020
+* Created: Wed Sep 2 10:03:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp.pxi.spice
index 41b11bd..27315eb 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp.pxi.spice
-* Created: Fri Aug 28 10:47:41 2020
+* Created: Wed Sep 2 10:03:12 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_LP%B N_B_M1000_g N_B_M1003_g N_B_M1002_g B B B B B
+ N_B_c_31_n N_B_c_32_n PM_SKY130_FD_SC_LP__NAND2_LP%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp.spice
index 9a04167..406cf9c 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp.spice
-* Created: Fri Aug 28 10:47:41 2020
+* Created: Wed Sep 2 10:03:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.lvs.report
new file mode 100644
index 0000000..66961ca
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_lp2.sp ('sky130_fd_sc_lp__nand2_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_lp2.spice ('sky130_fd_sc_lp__nand2_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_lp2 sky130_fd_sc_lp__nand2_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pex.spice
index a6616c3..026643b 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp2.pex.spice
-* Created: Fri Aug 28 10:47:33 2020
+* Created: Wed Sep 2 10:03:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pxi.spice
index 4fb2761..da597a8 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp2.pxi.spice
-* Created: Fri Aug 28 10:47:33 2020
+* Created: Wed Sep 2 10:03:04 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_LP2%B N_B_M1003_g N_B_M1001_g B B N_B_c_34_n
+ N_B_c_35_n PM_SKY130_FD_SC_LP__NAND2_LP2%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.spice b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.spice
index 6994fec..f754b5f 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_lp2.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_lp2.spice
-* Created: Fri Aug 28 10:47:33 2020
+* Created: Wed Sep 2 10:03:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_m.lvs.report b/cells/nand2/sky130_fd_sc_lp__nand2_m.lvs.report
new file mode 100644
index 0000000..3bb2c26
--- /dev/null
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2_m.sp ('sky130_fd_sc_lp__nand2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2/sky130_fd_sc_lp__nand2_m.spice ('sky130_fd_sc_lp__nand2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2_m sky130_fd_sc_lp__nand2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_m.pex.spice b/cells/nand2/sky130_fd_sc_lp__nand2_m.pex.spice
index 70cd514..e1a81df 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_m.pex.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_m.pex.spice
-* Created: Fri Aug 28 10:47:49 2020
+* Created: Wed Sep 2 10:03:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_m.pxi.spice b/cells/nand2/sky130_fd_sc_lp__nand2_m.pxi.spice
index 5843c05..08889a4 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_m.pxi.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_m.pxi.spice
-* Created: Fri Aug 28 10:47:49 2020
+* Created: Wed Sep 2 10:03:19 2020
*
x_PM_SKY130_FD_SC_LP__NAND2_M%B N_B_c_31_n N_B_M1000_g N_B_M1003_g N_B_c_34_n B
+ B B B N_B_c_36_n PM_SKY130_FD_SC_LP__NAND2_M%B
diff --git a/cells/nand2/sky130_fd_sc_lp__nand2_m.spice b/cells/nand2/sky130_fd_sc_lp__nand2_m.spice
index 4bc15b1..2ebe31c 100644
--- a/cells/nand2/sky130_fd_sc_lp__nand2_m.spice
+++ b/cells/nand2/sky130_fd_sc_lp__nand2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2_m.spice
-* Created: Fri Aug 28 10:47:49 2020
+* Created: Wed Sep 2 10:03:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.lvs.report b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.lvs.report
new file mode 100644
index 0000000..40d5c54
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2b_1.sp ('sky130_fd_sc_lp__nand2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2b/sky130_fd_sc_lp__nand2b_1.spice ('sky130_fd_sc_lp__nand2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2b_1 sky130_fd_sc_lp__nand2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pex.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pex.spice
index a4019e8..1be8299 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_1.pex.spice
-* Created: Fri Aug 28 10:47:58 2020
+* Created: Wed Sep 2 10:03:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pxi.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pxi.spice
index 2baceda..491ad6a 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_1.pxi.spice
-* Created: Fri Aug 28 10:47:58 2020
+* Created: Wed Sep 2 10:03:26 2020
*
x_PM_SKY130_FD_SC_LP__NAND2B_1%A_N N_A_N_M1004_g N_A_N_M1000_g N_A_N_c_49_n
+ N_A_N_c_50_n A_N N_A_N_c_51_n N_A_N_c_52_n PM_SKY130_FD_SC_LP__NAND2B_1%A_N
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.spice
index 520e188..154d1eb 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_1.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_1.spice
-* Created: Fri Aug 28 10:47:58 2020
+* Created: Wed Sep 2 10:03:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.lvs.report b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.lvs.report
new file mode 100644
index 0000000..a986858
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2b_2.sp ('sky130_fd_sc_lp__nand2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2b/sky130_fd_sc_lp__nand2b_2.spice ('sky130_fd_sc_lp__nand2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2b_2 sky130_fd_sc_lp__nand2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pex.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pex.spice
index d3285fc..cf70d26 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_2.pex.spice
-* Created: Fri Aug 28 10:48:12 2020
+* Created: Wed Sep 2 10:03:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pxi.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pxi.spice
index ead7fc2..c951c37 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_2.pxi.spice
-* Created: Fri Aug 28 10:48:12 2020
+* Created: Wed Sep 2 10:03:33 2020
*
x_PM_SKY130_FD_SC_LP__NAND2B_2%A_N N_A_N_c_53_n N_A_N_M1008_g N_A_N_c_54_n
+ N_A_N_M1001_g A_N PM_SKY130_FD_SC_LP__NAND2B_2%A_N
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.spice
index 9b9a831..5911621 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_2.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_2.spice
-* Created: Fri Aug 28 10:48:12 2020
+* Created: Wed Sep 2 10:03:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.lvs.report b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.lvs.report
new file mode 100644
index 0000000..63951a0
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2b_4.sp ('sky130_fd_sc_lp__nand2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2b/sky130_fd_sc_lp__nand2b_4.spice ('sky130_fd_sc_lp__nand2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2b_4 sky130_fd_sc_lp__nand2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pex.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pex.spice
index 42749ba..0a81070 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_4.pex.spice
-* Created: Fri Aug 28 10:48:21 2020
+* Created: Wed Sep 2 10:03:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pxi.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pxi.spice
index c6e4d24..58dbaff 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_4.pxi.spice
-* Created: Fri Aug 28 10:48:21 2020
+* Created: Wed Sep 2 10:03:40 2020
*
x_PM_SKY130_FD_SC_LP__NAND2B_4%A_N N_A_N_M1011_g N_A_N_M1016_g A_N N_A_N_c_90_n
+ N_A_N_c_91_n PM_SKY130_FD_SC_LP__NAND2B_4%A_N
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.spice
index 70f146b..d179e91 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_4.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_4.spice
-* Created: Fri Aug 28 10:48:21 2020
+* Created: Wed Sep 2 10:03:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.lvs.report b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.lvs.report
new file mode 100644
index 0000000..3e2b04f
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2b_lp.sp ('sky130_fd_sc_lp__nand2b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.spice ('sky130_fd_sc_lp__nand2b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2b_lp sky130_fd_sc_lp__nand2b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 8 7
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pex.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pex.spice
index 1f53bbf..f4498a5 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_lp.pex.spice
-* Created: Fri Aug 28 10:48:31 2020
+* Created: Wed Sep 2 10:03:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pxi.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pxi.spice
index f547be7..802cc75 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_lp.pxi.spice
-* Created: Fri Aug 28 10:48:31 2020
+* Created: Wed Sep 2 10:03:47 2020
*
x_PM_SKY130_FD_SC_LP__NAND2B_LP%A_N N_A_N_c_52_n N_A_N_M1000_g N_A_N_c_53_n
+ N_A_N_M1003_g N_A_N_c_54_n N_A_N_c_55_n N_A_N_M1005_g N_A_N_c_56_n
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.spice
index aa27bbf..993f558 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_lp.spice
-* Created: Fri Aug 28 10:48:31 2020
+* Created: Wed Sep 2 10:03:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.lvs.report b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.lvs.report
new file mode 100644
index 0000000..4cea201
--- /dev/null
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand2b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand2b_m.sp ('sky130_fd_sc_lp__nand2b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand2b/sky130_fd_sc_lp__nand2b_m.spice ('sky130_fd_sc_lp__nand2b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand2b_m sky130_fd_sc_lp__nand2b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand2b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand2b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pex.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pex.spice
index 2d47e69..cf114f7 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pex.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_m.pex.spice
-* Created: Fri Aug 28 10:48:39 2020
+* Created: Wed Sep 2 10:03:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pxi.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pxi.spice
index 2b3a654..700ec64 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pxi.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_m.pxi.spice
-* Created: Fri Aug 28 10:48:39 2020
+* Created: Wed Sep 2 10:03:54 2020
*
x_PM_SKY130_FD_SC_LP__NAND2B_M%A_N N_A_N_M1004_g N_A_N_c_54_n N_A_N_M1005_g
+ N_A_N_c_55_n A_N A_N A_N A_N A_N N_A_N_c_57_n PM_SKY130_FD_SC_LP__NAND2B_M%A_N
diff --git a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.spice b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.spice
index d2f86b0..91a09c9 100644
--- a/cells/nand2b/sky130_fd_sc_lp__nand2b_m.spice
+++ b/cells/nand2b/sky130_fd_sc_lp__nand2b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand2b_m.spice
-* Created: Fri Aug 28 10:48:39 2020
+* Created: Wed Sep 2 10:03:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_0.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_0.lvs.report
new file mode 100644
index 0000000..2472078
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_0.sp ('sky130_fd_sc_lp__nand3_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_0.spice ('sky130_fd_sc_lp__nand3_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:03:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_0 sky130_fd_sc_lp__nand3_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_0.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_0.pex.spice
index 10094ee..097476e 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_0.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_0.pex.spice
-* Created: Fri Aug 28 10:48:47 2020
+* Created: Wed Sep 2 10:04:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_0.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_0.pxi.spice
index 414eda5..0d78637 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_0.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_0.pxi.spice
-* Created: Fri Aug 28 10:48:47 2020
+* Created: Wed Sep 2 10:04:02 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_0%C N_C_c_45_n N_C_M1001_g N_C_M1000_g N_C_c_47_n
+ N_C_c_48_n N_C_c_53_n C C C C N_C_c_50_n PM_SKY130_FD_SC_LP__NAND3_0%C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_0.spice b/cells/nand3/sky130_fd_sc_lp__nand3_0.spice
index 39f1c00..ce9aac9 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_0.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_0.spice
-* Created: Fri Aug 28 10:48:47 2020
+* Created: Wed Sep 2 10:04:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_1.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_1.lvs.report
new file mode 100644
index 0000000..9880765
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_1.sp ('sky130_fd_sc_lp__nand3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_1.spice ('sky130_fd_sc_lp__nand3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_1 sky130_fd_sc_lp__nand3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_1.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_1.pex.spice
index ccc7f84..b8c20cf 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_1.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_1.pex.spice
-* Created: Fri Aug 28 10:48:55 2020
+* Created: Wed Sep 2 10:04:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_1.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_1.pxi.spice
index 7f6e325..f201afa 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_1.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_1.pxi.spice
-* Created: Fri Aug 28 10:48:55 2020
+* Created: Wed Sep 2 10:04:09 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_1%C N_C_M1005_g N_C_M1000_g C C N_C_c_36_n
+ N_C_c_37_n PM_SKY130_FD_SC_LP__NAND3_1%C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_1.spice b/cells/nand3/sky130_fd_sc_lp__nand3_1.spice
index e486cf0..8d3c612 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_1.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_1.spice
-* Created: Fri Aug 28 10:48:55 2020
+* Created: Wed Sep 2 10:04:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_2.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_2.lvs.report
new file mode 100644
index 0000000..2b9ca27
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_2.sp ('sky130_fd_sc_lp__nand3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_2.spice ('sky130_fd_sc_lp__nand3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_2 sky130_fd_sc_lp__nand3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_2.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_2.pex.spice
index 15acaf0..db20bf6 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_2.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_2.pex.spice
-* Created: Fri Aug 28 10:49:03 2020
+* Created: Wed Sep 2 10:04:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_2.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_2.pxi.spice
index bef5787..e739952 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_2.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_2.pxi.spice
-* Created: Fri Aug 28 10:49:03 2020
+* Created: Wed Sep 2 10:04:16 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_2%A N_A_c_62_n N_A_M1009_g N_A_M1004_g N_A_c_64_n
+ N_A_c_65_n N_A_M1010_g N_A_M1008_g N_A_c_67_n A A N_A_c_69_n
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_2.spice b/cells/nand3/sky130_fd_sc_lp__nand3_2.spice
index 16b14f4..55f13aa 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_2.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_2.spice
-* Created: Fri Aug 28 10:49:03 2020
+* Created: Wed Sep 2 10:04:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_4.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_4.lvs.report
new file mode 100644
index 0000000..9d9810e
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_4.sp ('sky130_fd_sc_lp__nand3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_4.spice ('sky130_fd_sc_lp__nand3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_4 sky130_fd_sc_lp__nand3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_4.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_4.pex.spice
index c4edf13..3b808e9 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_4.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_4.pex.spice
-* Created: Fri Aug 28 10:49:18 2020
+* Created: Wed Sep 2 10:04:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_4.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_4.pxi.spice
index 8183edb..0abb4ed 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_4.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_4.pxi.spice
-* Created: Fri Aug 28 10:49:18 2020
+* Created: Wed Sep 2 10:04:24 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_4%A N_A_M1006_g N_A_M1000_g N_A_M1014_g N_A_M1009_g
+ N_A_M1018_g N_A_M1016_g N_A_M1019_g N_A_M1023_g A A A N_A_c_97_n
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_4.spice b/cells/nand3/sky130_fd_sc_lp__nand3_4.spice
index 4b422aa..58f1c9f 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_4.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_4.spice
-* Created: Fri Aug 28 10:49:18 2020
+* Created: Wed Sep 2 10:04:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_lp.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_lp.lvs.report
new file mode 100644
index 0000000..f6f1a1a
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_lp.sp ('sky130_fd_sc_lp__nand3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_lp.spice ('sky130_fd_sc_lp__nand3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_lp sky130_fd_sc_lp__nand3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_lp.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_lp.pex.spice
index 3e1de64..5258b0a 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_lp.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_lp.pex.spice
-* Created: Fri Aug 28 10:49:27 2020
+* Created: Wed Sep 2 10:04:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_lp.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_lp.pxi.spice
index 6b28adc..073e9fd 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_lp.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_lp.pxi.spice
-* Created: Fri Aug 28 10:49:27 2020
+* Created: Wed Sep 2 10:04:31 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_LP%C N_C_M1000_g N_C_M1004_g N_C_c_45_n N_C_c_46_n C
+ C N_C_c_48_n PM_SKY130_FD_SC_LP__NAND3_LP%C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_lp.spice b/cells/nand3/sky130_fd_sc_lp__nand3_lp.spice
index dfebf27..468f170 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_lp.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_lp.spice
-* Created: Fri Aug 28 10:49:27 2020
+* Created: Wed Sep 2 10:04:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_m.lvs.report b/cells/nand3/sky130_fd_sc_lp__nand3_m.lvs.report
new file mode 100644
index 0000000..dd50b78
--- /dev/null
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3_m.sp ('sky130_fd_sc_lp__nand3_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3/sky130_fd_sc_lp__nand3_m.spice ('sky130_fd_sc_lp__nand3_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3_m sky130_fd_sc_lp__nand3_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_m.pex.spice b/cells/nand3/sky130_fd_sc_lp__nand3_m.pex.spice
index 80720fc..3088484 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_m.pex.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_m.pex.spice
-* Created: Fri Aug 28 10:49:36 2020
+* Created: Wed Sep 2 10:04:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_m.pxi.spice b/cells/nand3/sky130_fd_sc_lp__nand3_m.pxi.spice
index fa1ef64..2cdf798 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_m.pxi.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_m.pxi.spice
-* Created: Fri Aug 28 10:49:36 2020
+* Created: Wed Sep 2 10:04:37 2020
*
x_PM_SKY130_FD_SC_LP__NAND3_M%C N_C_c_44_n N_C_M1001_g N_C_M1000_g N_C_c_46_n
+ N_C_c_47_n N_C_c_52_n C C C C N_C_c_49_n PM_SKY130_FD_SC_LP__NAND3_M%C
diff --git a/cells/nand3/sky130_fd_sc_lp__nand3_m.spice b/cells/nand3/sky130_fd_sc_lp__nand3_m.spice
index 7d75d37..45ea4c3 100644
--- a/cells/nand3/sky130_fd_sc_lp__nand3_m.spice
+++ b/cells/nand3/sky130_fd_sc_lp__nand3_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3_m.spice
-* Created: Fri Aug 28 10:49:36 2020
+* Created: Wed Sep 2 10:04:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.lvs.report b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.lvs.report
new file mode 100644
index 0000000..57c5ecf
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3b_1.sp ('sky130_fd_sc_lp__nand3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3b/sky130_fd_sc_lp__nand3b_1.spice ('sky130_fd_sc_lp__nand3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3b_1 sky130_fd_sc_lp__nand3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pex.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pex.spice
index d492ece..7da0a7e 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_1.pex.spice
-* Created: Fri Aug 28 10:49:44 2020
+* Created: Wed Sep 2 10:04:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pxi.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pxi.spice
index 229be6d..b94f013 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_1.pxi.spice
-* Created: Fri Aug 28 10:49:44 2020
+* Created: Wed Sep 2 10:04:45 2020
*
x_PM_SKY130_FD_SC_LP__NAND3B_1%A_N N_A_N_M1005_g N_A_N_M1004_g A_N N_A_N_c_47_n
+ N_A_N_c_48_n PM_SKY130_FD_SC_LP__NAND3B_1%A_N
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.spice
index 660dbe1..44c4aa4 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_1.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_1.spice
-* Created: Fri Aug 28 10:49:44 2020
+* Created: Wed Sep 2 10:04:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.lvs.report b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.lvs.report
new file mode 100644
index 0000000..354ee16
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3b_2.sp ('sky130_fd_sc_lp__nand3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3b/sky130_fd_sc_lp__nand3b_2.spice ('sky130_fd_sc_lp__nand3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3b_2 sky130_fd_sc_lp__nand3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pex.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pex.spice
index 64d2464..f28185f 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_2.pex.spice
-* Created: Fri Aug 28 10:49:52 2020
+* Created: Wed Sep 2 10:04:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pxi.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pxi.spice
index 87fbf40..a35ad7d 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_2.pxi.spice
-* Created: Fri Aug 28 10:49:52 2020
+* Created: Wed Sep 2 10:04:52 2020
*
x_PM_SKY130_FD_SC_LP__NAND3B_2%A_N N_A_N_M1009_g N_A_N_M1004_g A_N N_A_N_c_79_n
+ PM_SKY130_FD_SC_LP__NAND3B_2%A_N
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.spice
index db72014..21e5b40 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_2.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_2.spice
-* Created: Fri Aug 28 10:49:52 2020
+* Created: Wed Sep 2 10:04:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.lvs.report b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.lvs.report
new file mode 100644
index 0000000..2e3ccfd
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3b_4.sp ('sky130_fd_sc_lp__nand3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3b/sky130_fd_sc_lp__nand3b_4.spice ('sky130_fd_sc_lp__nand3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:04:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3b_4 sky130_fd_sc_lp__nand3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pex.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pex.spice
index 52188c6..cacb1a8 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_4.pex.spice
-* Created: Fri Aug 28 10:49:59 2020
+* Created: Wed Sep 2 10:04:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pxi.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pxi.spice
index 63a3d5d..9cfb215 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_4.pxi.spice
-* Created: Fri Aug 28 10:49:59 2020
+* Created: Wed Sep 2 10:04:59 2020
*
x_PM_SKY130_FD_SC_LP__NAND3B_4%A_N N_A_N_c_109_n N_A_N_M1013_g N_A_N_c_112_n
+ N_A_N_M1016_g A_N A_N N_A_N_c_111_n PM_SKY130_FD_SC_LP__NAND3B_4%A_N
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.spice
index 04421af..17c4083 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_4.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_4.spice
-* Created: Fri Aug 28 10:49:59 2020
+* Created: Wed Sep 2 10:04:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.lvs.report b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.lvs.report
new file mode 100644
index 0000000..447ea9f
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3b_lp.sp ('sky130_fd_sc_lp__nand3b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.spice ('sky130_fd_sc_lp__nand3b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3b_lp sky130_fd_sc_lp__nand3b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B C A_N Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pex.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pex.spice
index 0227ea5..5a60d5c 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_lp.pex.spice
-* Created: Fri Aug 28 10:50:08 2020
+* Created: Wed Sep 2 10:05:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pxi.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pxi.spice
index c92d209..06751e8 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_lp.pxi.spice
-* Created: Fri Aug 28 10:50:08 2020
+* Created: Wed Sep 2 10:05:06 2020
*
x_PM_SKY130_FD_SC_LP__NAND3B_LP%A_90_247# N_A_90_247#_M1004_d
+ N_A_90_247#_M1008_d N_A_90_247#_M1007_g N_A_90_247#_M1000_g N_A_90_247#_c_55_n
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.spice
index e6d53ea..b2a1724 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_lp.spice
-* Created: Fri Aug 28 10:50:08 2020
+* Created: Wed Sep 2 10:05:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.lvs.report b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.lvs.report
new file mode 100644
index 0000000..7c7506e
--- /dev/null
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand3b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand3b_m.sp ('sky130_fd_sc_lp__nand3b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand3b/sky130_fd_sc_lp__nand3b_m.spice ('sky130_fd_sc_lp__nand3b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand3b_m sky130_fd_sc_lp__nand3b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand3b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand3b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pex.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pex.spice
index 4894f4a..f77fab2 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pex.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_m.pex.spice
-* Created: Fri Aug 28 10:50:22 2020
+* Created: Wed Sep 2 10:05:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pxi.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pxi.spice
index 36be2ad..a0461fd 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pxi.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_m.pxi.spice
-* Created: Fri Aug 28 10:50:22 2020
+* Created: Wed Sep 2 10:05:13 2020
*
x_PM_SKY130_FD_SC_LP__NAND3B_M%A_N N_A_N_M1001_g N_A_N_M1000_g N_A_N_c_58_n
+ N_A_N_c_59_n A_N A_N A_N N_A_N_c_61_n PM_SKY130_FD_SC_LP__NAND3B_M%A_N
diff --git a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.spice b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.spice
index 8349151..a059048 100644
--- a/cells/nand3b/sky130_fd_sc_lp__nand3b_m.spice
+++ b/cells/nand3b/sky130_fd_sc_lp__nand3b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand3b_m.spice
-* Created: Fri Aug 28 10:50:22 2020
+* Created: Wed Sep 2 10:05:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_0.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_0.lvs.report
new file mode 100644
index 0000000..fc8ea8b
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_0.sp ('sky130_fd_sc_lp__nand4_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_0.spice ('sky130_fd_sc_lp__nand4_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_0 sky130_fd_sc_lp__nand4_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_0.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_0.pex.spice
index 960e945..8fbb077 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_0.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_0.pex.spice
-* Created: Fri Aug 28 10:50:31 2020
+* Created: Wed Sep 2 10:05:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_0.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_0.pxi.spice
index e4016e1..93cb04a 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_0.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_0.pxi.spice
-* Created: Fri Aug 28 10:50:31 2020
+* Created: Wed Sep 2 10:05:21 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_0%D N_D_M1004_g N_D_M1001_g N_D_c_62_n N_D_c_67_n D
+ D D D N_D_c_64_n PM_SKY130_FD_SC_LP__NAND4_0%D
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_0.spice b/cells/nand4/sky130_fd_sc_lp__nand4_0.spice
index 8d88c0b..5f3432a 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_0.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_0.spice
-* Created: Fri Aug 28 10:50:31 2020
+* Created: Wed Sep 2 10:05:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_1.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_1.lvs.report
new file mode 100644
index 0000000..dbe5240
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_1.sp ('sky130_fd_sc_lp__nand4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_1.spice ('sky130_fd_sc_lp__nand4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_1 sky130_fd_sc_lp__nand4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_1.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_1.pex.spice
index c400e78..0c2da45 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_1.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_1.pex.spice
-* Created: Fri Aug 28 10:50:41 2020
+* Created: Wed Sep 2 10:05:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_1.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_1.pxi.spice
index 3771b45..003c4ff 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_1.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_1.pxi.spice
-* Created: Fri Aug 28 10:50:41 2020
+* Created: Wed Sep 2 10:05:28 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_1%D N_D_M1007_g N_D_M1004_g D D N_D_c_43_n
+ N_D_c_44_n PM_SKY130_FD_SC_LP__NAND4_1%D
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_1.spice b/cells/nand4/sky130_fd_sc_lp__nand4_1.spice
index 775e150..78574be 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_1.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_1.spice
-* Created: Fri Aug 28 10:50:41 2020
+* Created: Wed Sep 2 10:05:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_2.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_2.lvs.report
new file mode 100644
index 0000000..4b37d88
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_2.sp ('sky130_fd_sc_lp__nand4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_2.spice ('sky130_fd_sc_lp__nand4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_2 sky130_fd_sc_lp__nand4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_2.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_2.pex.spice
index 6e1f580..e15785f 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_2.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_2.pex.spice
-* Created: Fri Aug 28 10:50:53 2020
+* Created: Wed Sep 2 10:05:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_2.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_2.pxi.spice
index d2aa47a..916aeaf 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_2.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_2.pxi.spice
-* Created: Fri Aug 28 10:50:53 2020
+* Created: Wed Sep 2 10:05:35 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_2%D N_D_M1004_g N_D_c_77_n N_D_M1000_g N_D_M1011_g
+ N_D_c_78_n N_D_M1005_g D D N_D_c_76_n PM_SKY130_FD_SC_LP__NAND4_2%D
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_2.spice b/cells/nand4/sky130_fd_sc_lp__nand4_2.spice
index 5795d47..e7b77f3 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_2.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_2.spice
-* Created: Fri Aug 28 10:50:53 2020
+* Created: Wed Sep 2 10:05:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_4.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_4.lvs.report
new file mode 100644
index 0000000..8d4cb57
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_4.sp ('sky130_fd_sc_lp__nand4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_4.spice ('sky130_fd_sc_lp__nand4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_4 sky130_fd_sc_lp__nand4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_4.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_4.pex.spice
index fc2070f..ab60352 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_4.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_4.pex.spice
-* Created: Fri Aug 28 10:51:03 2020
+* Created: Wed Sep 2 10:05:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_4.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_4.pxi.spice
index e34701b..3d602e2 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_4.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_4.pxi.spice
-* Created: Fri Aug 28 10:51:03 2020
+* Created: Wed Sep 2 10:05:41 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_4%D N_D_M1001_g N_D_M1000_g N_D_M1011_g N_D_M1012_g
+ N_D_M1023_g N_D_M1019_g N_D_M1031_g N_D_M1027_g D D D D N_D_c_118_n
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_4.spice b/cells/nand4/sky130_fd_sc_lp__nand4_4.spice
index 5c6a8e9..16eb18b 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_4.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_4.spice
-* Created: Fri Aug 28 10:51:03 2020
+* Created: Wed Sep 2 10:05:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_lp.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_lp.lvs.report
new file mode 100644
index 0000000..5eea675
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_lp.sp ('sky130_fd_sc_lp__nand4_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_lp.spice ('sky130_fd_sc_lp__nand4_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_lp sky130_fd_sc_lp__nand4_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_lp.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_lp.pex.spice
index 7498086..f24bb1e 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_lp.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_lp.pex.spice
-* Created: Fri Aug 28 10:51:11 2020
+* Created: Wed Sep 2 10:05:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_lp.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_lp.pxi.spice
index 72df1e3..d8d7db9 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_lp.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_lp.pxi.spice
-* Created: Fri Aug 28 10:51:11 2020
+* Created: Wed Sep 2 10:05:48 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_LP%D N_D_M1005_g N_D_M1002_g D N_D_c_51_n N_D_c_52_n
+ PM_SKY130_FD_SC_LP__NAND4_LP%D
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_lp.spice b/cells/nand4/sky130_fd_sc_lp__nand4_lp.spice
index a1feb86..a8bb220 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_lp.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_lp.spice
-* Created: Fri Aug 28 10:51:11 2020
+* Created: Wed Sep 2 10:05:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_m.lvs.report b/cells/nand4/sky130_fd_sc_lp__nand4_m.lvs.report
new file mode 100644
index 0000000..1a560b8
--- /dev/null
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4_m.sp ('sky130_fd_sc_lp__nand4_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4/sky130_fd_sc_lp__nand4_m.spice ('sky130_fd_sc_lp__nand4_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4_m sky130_fd_sc_lp__nand4_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_m.pex.spice b/cells/nand4/sky130_fd_sc_lp__nand4_m.pex.spice
index eff6f9d..e40e2b4 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_m.pex.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_m.pex.spice
-* Created: Fri Aug 28 10:51:21 2020
+* Created: Wed Sep 2 10:05:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_m.pxi.spice b/cells/nand4/sky130_fd_sc_lp__nand4_m.pxi.spice
index 904d85b..dc48cd6 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_m.pxi.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_m.pxi.spice
-* Created: Fri Aug 28 10:51:21 2020
+* Created: Wed Sep 2 10:05:56 2020
*
x_PM_SKY130_FD_SC_LP__NAND4_M%D N_D_M1004_g N_D_M1001_g N_D_c_61_n N_D_c_66_n D
+ D D D N_D_c_63_n PM_SKY130_FD_SC_LP__NAND4_M%D
diff --git a/cells/nand4/sky130_fd_sc_lp__nand4_m.spice b/cells/nand4/sky130_fd_sc_lp__nand4_m.spice
index 636d975..d31a0e2 100644
--- a/cells/nand4/sky130_fd_sc_lp__nand4_m.spice
+++ b/cells/nand4/sky130_fd_sc_lp__nand4_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4_m.spice
-* Created: Fri Aug 28 10:51:21 2020
+* Created: Wed Sep 2 10:05:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.lvs.report b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.lvs.report
new file mode 100644
index 0000000..85cb75e
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4b_1.sp ('sky130_fd_sc_lp__nand4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4b/sky130_fd_sc_lp__nand4b_1.spice ('sky130_fd_sc_lp__nand4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:05:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4b_1 sky130_fd_sc_lp__nand4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pex.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pex.spice
index 49d9298..614b937 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_1.pex.spice
-* Created: Fri Aug 28 10:51:33 2020
+* Created: Wed Sep 2 10:06:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pxi.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pxi.spice
index a80cc4a..79991e2 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_1.pxi.spice
-* Created: Fri Aug 28 10:51:33 2020
+* Created: Wed Sep 2 10:06:03 2020
*
x_PM_SKY130_FD_SC_LP__NAND4B_1%A_N N_A_N_M1003_g N_A_N_M1006_g A_N N_A_N_c_56_n
+ N_A_N_c_57_n PM_SKY130_FD_SC_LP__NAND4B_1%A_N
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.spice
index 00784ae..0523643 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_1.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_1.spice
-* Created: Fri Aug 28 10:51:33 2020
+* Created: Wed Sep 2 10:06:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.lvs.report b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.lvs.report
new file mode 100644
index 0000000..a0eec43
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4b_2.sp ('sky130_fd_sc_lp__nand4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4b/sky130_fd_sc_lp__nand4b_2.spice ('sky130_fd_sc_lp__nand4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:06 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4b_2 sky130_fd_sc_lp__nand4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pex.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pex.spice
index ee46ed4..8b9d175 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_2.pex.spice
-* Created: Fri Aug 28 10:51:41 2020
+* Created: Wed Sep 2 10:06:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pxi.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pxi.spice
index e6eae6c..1e8ae62 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_2.pxi.spice
-* Created: Fri Aug 28 10:51:41 2020
+* Created: Wed Sep 2 10:06:10 2020
*
x_PM_SKY130_FD_SC_LP__NAND4B_2%A_N N_A_N_c_89_n N_A_N_M1013_g N_A_N_c_91_n
+ N_A_N_c_92_n N_A_N_M1010_g A_N N_A_N_c_94_n N_A_N_c_95_n
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.spice
index dfb31ff..98faed0 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_2.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_2.spice
-* Created: Fri Aug 28 10:51:41 2020
+* Created: Wed Sep 2 10:06:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.lvs.report b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.lvs.report
new file mode 100644
index 0000000..bc69f76
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4b_4.sp ('sky130_fd_sc_lp__nand4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4b/sky130_fd_sc_lp__nand4b_4.spice ('sky130_fd_sc_lp__nand4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4b_4 sky130_fd_sc_lp__nand4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pex.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pex.spice
index 1943f7f..7a9465c 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_4.pex.spice
-* Created: Fri Aug 28 10:51:49 2020
+* Created: Wed Sep 2 10:06:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pxi.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pxi.spice
index 8de34db..b60229d 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_4.pxi.spice
-* Created: Fri Aug 28 10:51:49 2020
+* Created: Wed Sep 2 10:06:17 2020
*
x_PM_SKY130_FD_SC_LP__NAND4B_4%A_N N_A_N_M1027_g N_A_N_M1000_g A_N N_A_N_c_138_n
+ N_A_N_c_139_n PM_SKY130_FD_SC_LP__NAND4B_4%A_N
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.spice
index 1a1f363..0919527 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_4.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_4.spice
-* Created: Fri Aug 28 10:51:49 2020
+* Created: Wed Sep 2 10:06:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.lvs.report b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.lvs.report
new file mode 100644
index 0000000..af8ae01
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4b_lp.sp ('sky130_fd_sc_lp__nand4b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.spice ('sky130_fd_sc_lp__nand4b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4b_lp sky130_fd_sc_lp__nand4b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B C D A_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pex.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pex.spice
index 7b3de9f..0b42cdd 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_lp.pex.spice
-* Created: Fri Aug 28 10:51:57 2020
+* Created: Wed Sep 2 10:06:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pxi.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pxi.spice
index 54c0dbc..894fc24 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_lp.pxi.spice
-* Created: Fri Aug 28 10:51:57 2020
+* Created: Wed Sep 2 10:06:24 2020
*
x_PM_SKY130_FD_SC_LP__NAND4B_LP%A_87_231# N_A_87_231#_M1010_d
+ N_A_87_231#_M1001_d N_A_87_231#_c_74_n N_A_87_231#_M1008_g N_A_87_231#_M1000_g
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.spice
index 3b02bf2..dc23bdd 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_lp.spice
-* Created: Fri Aug 28 10:51:57 2020
+* Created: Wed Sep 2 10:06:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.lvs.report b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.lvs.report
new file mode 100644
index 0000000..a3be224
--- /dev/null
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4b_m.sp ('sky130_fd_sc_lp__nand4b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4b/sky130_fd_sc_lp__nand4b_m.spice ('sky130_fd_sc_lp__nand4b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4b_m sky130_fd_sc_lp__nand4b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 5 5 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N D C B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pex.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pex.spice
index 2f3f13e..623c2a5 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pex.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_m.pex.spice
-* Created: Fri Aug 28 10:52:06 2020
+* Created: Wed Sep 2 10:06:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pxi.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pxi.spice
index 6f9975a..9ff3441 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pxi.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_m.pxi.spice
-* Created: Fri Aug 28 10:52:06 2020
+* Created: Wed Sep 2 10:06:31 2020
*
x_PM_SKY130_FD_SC_LP__NAND4B_M%A_N N_A_N_M1005_g N_A_N_M1003_g N_A_N_c_68_n
+ N_A_N_c_69_n A_N A_N A_N A_N A_N N_A_N_c_71_n PM_SKY130_FD_SC_LP__NAND4B_M%A_N
diff --git a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.spice b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.spice
index 7d47d8b..c1f6dad 100644
--- a/cells/nand4b/sky130_fd_sc_lp__nand4b_m.spice
+++ b/cells/nand4b/sky130_fd_sc_lp__nand4b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4b_m.spice
-* Created: Fri Aug 28 10:52:06 2020
+* Created: Wed Sep 2 10:06:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.lvs.report b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.lvs.report
new file mode 100644
index 0000000..3f1132f
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4bb_1.sp ('sky130_fd_sc_lp__nand4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.spice ('sky130_fd_sc_lp__nand4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4bb_1 sky130_fd_sc_lp__nand4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4bb_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N D C A_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pex.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pex.spice
index 76636e6..e374794 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_1.pex.spice
-* Created: Fri Aug 28 10:52:18 2020
+* Created: Wed Sep 2 10:06:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pxi.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pxi.spice
index 11a2d81..e7d8ab6 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_1.pxi.spice
-* Created: Fri Aug 28 10:52:18 2020
+* Created: Wed Sep 2 10:06:39 2020
*
x_PM_SKY130_FD_SC_LP__NAND4BB_1%B_N N_B_N_M1007_g N_B_N_M1006_g B_N B_N B_N B_N
+ B_N N_B_N_c_75_n PM_SKY130_FD_SC_LP__NAND4BB_1%B_N
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.spice
index f65203b..6d6f33a 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_1.spice
-* Created: Fri Aug 28 10:52:18 2020
+* Created: Wed Sep 2 10:06:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.lvs.report b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.lvs.report
new file mode 100644
index 0000000..2c678c1
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4bb_2.sp ('sky130_fd_sc_lp__nand4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.spice ('sky130_fd_sc_lp__nand4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4bb_2 sky130_fd_sc_lp__nand4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4bb_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pex.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pex.spice
index ef27e8a..c31fa1e 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_2.pex.spice
-* Created: Fri Aug 28 10:52:27 2020
+* Created: Wed Sep 2 10:06:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pxi.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pxi.spice
index 6be4440..0345d2b 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_2.pxi.spice
-* Created: Fri Aug 28 10:52:27 2020
+* Created: Wed Sep 2 10:06:46 2020
*
x_PM_SKY130_FD_SC_LP__NAND4BB_2%B_N N_B_N_M1000_g N_B_N_M1015_g N_B_N_c_115_n
+ N_B_N_c_116_n N_B_N_c_117_n B_N B_N N_B_N_c_119_n
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.spice
index d77bc55..4439074 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_2.spice
-* Created: Fri Aug 28 10:52:27 2020
+* Created: Wed Sep 2 10:06:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.lvs.report b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.lvs.report
new file mode 100644
index 0000000..d10104d
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4bb_4.sp ('sky130_fd_sc_lp__nand4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.spice ('sky130_fd_sc_lp__nand4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4bb_4 sky130_fd_sc_lp__nand4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4bb_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N B_N C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pex.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pex.spice
index 80ca50d..88e0b16 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_4.pex.spice
-* Created: Fri Aug 28 10:52:36 2020
+* Created: Wed Sep 2 10:06:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pxi.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pxi.spice
index 85dd4ad..9c947c5 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_4.pxi.spice
-* Created: Fri Aug 28 10:52:36 2020
+* Created: Wed Sep 2 10:06:54 2020
*
x_PM_SKY130_FD_SC_LP__NAND4BB_4%A_N N_A_N_M1032_g N_A_N_M1002_g A_N A_N
+ N_A_N_c_152_n N_A_N_c_153_n PM_SKY130_FD_SC_LP__NAND4BB_4%A_N
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.spice
index 4111f17..1002ac5 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_4.spice
-* Created: Fri Aug 28 10:52:36 2020
+* Created: Wed Sep 2 10:06:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.lvs.report b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.lvs.report
new file mode 100644
index 0000000..8ad9941
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4bb_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4bb_lp.sp ('sky130_fd_sc_lp__nand4bb_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.spice ('sky130_fd_sc_lp__nand4bb_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:06:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4bb_lp sky130_fd_sc_lp__nand4bb_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4bb_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4bb_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A_N C D B_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pex.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pex.spice
index 6d70bc1..ccf29ac 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_lp.pex.spice
-* Created: Fri Aug 28 10:52:44 2020
+* Created: Wed Sep 2 10:07:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pxi.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pxi.spice
index edb6afa..3111f2b 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_lp.pxi.spice
-* Created: Fri Aug 28 10:52:44 2020
+* Created: Wed Sep 2 10:07:01 2020
*
x_PM_SKY130_FD_SC_LP__NAND4BB_LP%A_N N_A_N_M1002_g N_A_N_M1008_g N_A_N_M1011_g
+ N_A_N_c_83_n N_A_N_c_84_n A_N N_A_N_c_85_n N_A_N_c_86_n
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.spice
index bc48910..94bf921 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_lp.spice
-* Created: Fri Aug 28 10:52:44 2020
+* Created: Wed Sep 2 10:07:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.lvs.report b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.lvs.report
new file mode 100644
index 0000000..736e63d
--- /dev/null
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nand4bb_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nand4bb_m.sp ('sky130_fd_sc_lp__nand4bb_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.spice ('sky130_fd_sc_lp__nand4bb_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nand4bb_m sky130_fd_sc_lp__nand4bb_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nand4bb_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nand4bb_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 1 SMN4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 6 6 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N D C A_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pex.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pex.spice
index 2d2d1ab..e84f615 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pex.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_m.pex.spice
-* Created: Fri Aug 28 10:52:55 2020
+* Created: Wed Sep 2 10:07:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pxi.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pxi.spice
index 79d06db..2e1369c 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pxi.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_m.pxi.spice
-* Created: Fri Aug 28 10:52:55 2020
+* Created: Wed Sep 2 10:07:08 2020
*
x_PM_SKY130_FD_SC_LP__NAND4BB_M%B_N N_B_N_M1005_g N_B_N_M1003_g B_N B_N
+ N_B_N_c_76_n N_B_N_c_77_n PM_SKY130_FD_SC_LP__NAND4BB_M%B_N
diff --git a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.spice b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.spice
index 7767008..4fb3095 100644
--- a/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.spice
+++ b/cells/nand4bb/sky130_fd_sc_lp__nand4bb_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nand4bb_m.spice
-* Created: Fri Aug 28 10:52:55 2020
+* Created: Wed Sep 2 10:07:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_0.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_0.lvs.report
new file mode 100644
index 0000000..fbd2c2d
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_0.sp ('sky130_fd_sc_lp__nor2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_0.spice ('sky130_fd_sc_lp__nor2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_0 sky130_fd_sc_lp__nor2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_0.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_0.pex.spice
index 24e7fbc..ce40bc5 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_0.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_0.pex.spice
-* Created: Fri Aug 28 10:53:06 2020
+* Created: Wed Sep 2 10:07:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_0.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_0.pxi.spice
index e752b04..038ef42 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_0.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_0.pxi.spice
-* Created: Fri Aug 28 10:53:06 2020
+* Created: Wed Sep 2 10:07:16 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_0%A N_A_c_29_n N_A_M1003_g N_A_M1001_g N_A_c_31_n A A
+ A A N_A_c_33_n N_A_c_34_n PM_SKY130_FD_SC_LP__NOR2_0%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_0.spice b/cells/nor2/sky130_fd_sc_lp__nor2_0.spice
index e513564..33fd3d6 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_0.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_0.spice
-* Created: Fri Aug 28 10:53:06 2020
+* Created: Wed Sep 2 10:07:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_1.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_1.lvs.report
new file mode 100644
index 0000000..6a38ba9
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_1.sp ('sky130_fd_sc_lp__nor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_1.spice ('sky130_fd_sc_lp__nor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_1 sky130_fd_sc_lp__nor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_1.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_1.pex.spice
index 5981508..2b4208e 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_1.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_1.pex.spice
-* Created: Fri Aug 28 10:53:14 2020
+* Created: Wed Sep 2 10:07:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_1.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_1.pxi.spice
index 293d25e..431a783 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_1.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_1.pxi.spice
-* Created: Fri Aug 28 10:53:14 2020
+* Created: Wed Sep 2 10:07:23 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_1%A N_A_M1003_g N_A_M1000_g A A N_A_c_30_n N_A_c_31_n
+ PM_SKY130_FD_SC_LP__NOR2_1%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_1.spice b/cells/nor2/sky130_fd_sc_lp__nor2_1.spice
index cb0be0e..483a3a4 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_1.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_1.spice
-* Created: Fri Aug 28 10:53:14 2020
+* Created: Wed Sep 2 10:07:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_2.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_2.lvs.report
new file mode 100644
index 0000000..59c3daa
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_2.sp ('sky130_fd_sc_lp__nor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_2.spice ('sky130_fd_sc_lp__nor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_2 sky130_fd_sc_lp__nor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_2.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_2.pex.spice
index 2beb037..3073fd7 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_2.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_2.pex.spice
-* Created: Fri Aug 28 10:53:24 2020
+* Created: Wed Sep 2 10:07:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_2.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_2.pxi.spice
index b40a9fb..e307071 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_2.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_2.pxi.spice
-* Created: Fri Aug 28 10:53:24 2020
+* Created: Wed Sep 2 10:07:30 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_2%A N_A_c_42_n N_A_M1000_g N_A_M1003_g N_A_c_44_n
+ N_A_M1002_g N_A_M1006_g A A N_A_c_47_n PM_SKY130_FD_SC_LP__NOR2_2%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_2.spice b/cells/nor2/sky130_fd_sc_lp__nor2_2.spice
index 36eb9ff..36b1d7e 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_2.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_2.spice
-* Created: Fri Aug 28 10:53:24 2020
+* Created: Wed Sep 2 10:07:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_4.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_4.lvs.report
new file mode 100644
index 0000000..e55c1d5
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_4.sp ('sky130_fd_sc_lp__nor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_4.spice ('sky130_fd_sc_lp__nor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_4 sky130_fd_sc_lp__nor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_4.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_4.pex.spice
index a1be3f8..55536a1 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_4.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_4.pex.spice
-* Created: Fri Aug 28 10:53:36 2020
+* Created: Wed Sep 2 10:07:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_4.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_4.pxi.spice
index d9a0398..9840428 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_4.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_4.pxi.spice
-* Created: Fri Aug 28 10:53:36 2020
+* Created: Wed Sep 2 10:07:37 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_4%A N_A_c_69_n N_A_M1004_g N_A_M1000_g N_A_c_71_n
+ N_A_M1007_g N_A_M1003_g N_A_c_73_n N_A_M1013_g N_A_M1006_g N_A_c_75_n
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_4.spice b/cells/nor2/sky130_fd_sc_lp__nor2_4.spice
index 0469f74..83c22ff 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_4.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_4.spice
-* Created: Fri Aug 28 10:53:36 2020
+* Created: Wed Sep 2 10:07:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_8.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_8.lvs.report
new file mode 100644
index 0000000..90b6bff
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_8.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_8.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_8.sp ('sky130_fd_sc_lp__nor2_8')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_8.spice ('sky130_fd_sc_lp__nor2_8')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_8 sky130_fd_sc_lp__nor2_8
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_8
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_8
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 4.
+ 28 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_8.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_8.pex.spice
index 7a2a6fd..a4ae436 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_8.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_8.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_8.pex.spice
-* Created: Fri Aug 28 10:53:45 2020
+* Created: Wed Sep 2 10:07:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_8.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_8.pxi.spice
index 9dc6814..503b911 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_8.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_8.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_8.pxi.spice
-* Created: Fri Aug 28 10:53:45 2020
+* Created: Wed Sep 2 10:07:44 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_8%A N_A_M1006_g N_A_M1000_g N_A_M1008_g N_A_M1004_g
+ N_A_M1011_g N_A_M1005_g N_A_M1017_g N_A_M1010_g N_A_M1020_g N_A_M1012_g
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_8.spice b/cells/nor2/sky130_fd_sc_lp__nor2_8.spice
index 7874016..51135a5 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_8.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_8.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_8.spice
-* Created: Fri Aug 28 10:53:45 2020
+* Created: Wed Sep 2 10:07:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_lp.lvs.report
new file mode 100644
index 0000000..fbdb879
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp.lvs.report
@@ -0,0 +1,559 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_lp.sp ('sky130_fd_sc_lp__nor2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice ('sky130_fd_sc_lp__nor2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_lp__nor2_lp sky130_fd_sc_lp__nor2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 5 *
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 5 *
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VPB VPB
+ VPWR
+ --- 2 Connections On This Net --- --- 2 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VNB VNB
+ VGND
+ --- 3 Connections On This Net --- --- 3 Connections On This Net ---
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 ** missing net ** w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 4 ** missing net ** w_n38_331#
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 5 M4(0.500,2.450) MP(PHIGHVT) M1004 MP(PHIGHVT)
+ g: A g: A
+ b: VPB ** VPB **
+ ** missing net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 6 M5(0.890,2.450) MP(PHIGHVT) M1005 MP(PHIGHVT)
+ g: B g: B
+ b: VPB ** VPB **
+ ** missing net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 7 M2(1.320,0.560) MN(NSHORT) M1003 MN(NSHORT)
+ g: B g: B
+ b: VNB ** VNB **
+ ** missing net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 8 M3(1.710,0.560) MN(NSHORT) M1001 MN(NSHORT)
+ g: B g: B
+ b: VNB ** VNB **
+ ** missing net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 9 M0(0.500,0.560) MN(NSHORT) M1000 MN(NSHORT)
+ g: A g: A
+ b: VNB ** VNB **
+ ** missing net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 10 M1(0.890,0.560) MN(NSHORT) M1002 MN(NSHORT)
+ g: A g: A
+ b: VNB ** VNB **
+ ** missing net ** b: w_0_0#
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 5 0 0
+
+ Nets: 7 5 0 2
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Layout Names That Are Missing In The Source:
+
+ Ports: VPWR VGND
+ Nets: VPWR VGND
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B Y
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp.pex.spice
index b8b9490..50c1dd2 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp.pex.spice
-* Created: Fri Aug 28 10:54:05 2020
+* Created: Wed Sep 2 10:07:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp.pxi.spice
index 266eb67..c9c715a 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp.pxi.spice
-* Created: Fri Aug 28 10:54:05 2020
+* Created: Wed Sep 2 10:07:58 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_LP%A N_A_M1000_g N_A_M1004_g N_A_c_38_n N_A_M1002_g
+ N_A_c_40_n N_A_c_44_n A A A N_A_c_42_n PM_SKY130_FD_SC_LP__NOR2_LP%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice
index e4da06d..04dd7e1 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp.spice
-* Created: Fri Aug 28 10:54:05 2020
+* Created: Wed Sep 2 10:07:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.lvs.report
new file mode 100644
index 0000000..e2b4d04
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_lp2.sp ('sky130_fd_sc_lp__nor2_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_lp2.spice ('sky130_fd_sc_lp__nor2_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:07:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_lp2 sky130_fd_sc_lp__nor2_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pex.spice
index 8284203..aa56a5e 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp2.pex.spice
-* Created: Fri Aug 28 10:53:57 2020
+* Created: Wed Sep 2 10:07:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pxi.spice
index 95323d5..44ebccb 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp2.pxi.spice
-* Created: Fri Aug 28 10:53:57 2020
+* Created: Wed Sep 2 10:07:51 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_LP2%A N_A_M1005_g N_A_M1000_g N_A_c_39_n N_A_M1002_g
+ A A N_A_c_42_n PM_SKY130_FD_SC_LP__NOR2_LP2%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.spice b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.spice
index 06437c0..c08888d 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_lp2.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_lp2.spice
-* Created: Fri Aug 28 10:53:57 2020
+* Created: Wed Sep 2 10:07:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_m.lvs.report b/cells/nor2/sky130_fd_sc_lp__nor2_m.lvs.report
new file mode 100644
index 0000000..278e42e
--- /dev/null
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2_m.sp ('sky130_fd_sc_lp__nor2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2/sky130_fd_sc_lp__nor2_m.spice ('sky130_fd_sc_lp__nor2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2_m sky130_fd_sc_lp__nor2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 7 7
+
+ Instances: 2 2 MN (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 7 7 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_m.pex.spice b/cells/nor2/sky130_fd_sc_lp__nor2_m.pex.spice
index 46cb5ac..d8a4a1b 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_m.pex.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_m.pex.spice
-* Created: Fri Aug 28 10:54:16 2020
+* Created: Wed Sep 2 10:08:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_m.pxi.spice b/cells/nor2/sky130_fd_sc_lp__nor2_m.pxi.spice
index 9be8ab7..6ce594a 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_m.pxi.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_m.pxi.spice
-* Created: Fri Aug 28 10:54:16 2020
+* Created: Wed Sep 2 10:08:05 2020
*
x_PM_SKY130_FD_SC_LP__NOR2_M%A N_A_c_29_n N_A_M1003_g N_A_M1001_g N_A_c_31_n A A
+ A A N_A_c_33_n N_A_c_34_n PM_SKY130_FD_SC_LP__NOR2_M%A
diff --git a/cells/nor2/sky130_fd_sc_lp__nor2_m.spice b/cells/nor2/sky130_fd_sc_lp__nor2_m.spice
index ff1f017..64aaf9e 100644
--- a/cells/nor2/sky130_fd_sc_lp__nor2_m.spice
+++ b/cells/nor2/sky130_fd_sc_lp__nor2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2_m.spice
-* Created: Fri Aug 28 10:54:16 2020
+* Created: Wed Sep 2 10:08:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.lvs.report b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.lvs.report
new file mode 100644
index 0000000..3062643
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2b_1.sp ('sky130_fd_sc_lp__nor2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2b/sky130_fd_sc_lp__nor2b_1.spice ('sky130_fd_sc_lp__nor2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2b_1 sky130_fd_sc_lp__nor2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pex.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pex.spice
index 3013d10..499c026 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_1.pex.spice
-* Created: Fri Aug 28 10:54:27 2020
+* Created: Wed Sep 2 10:08:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pxi.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pxi.spice
index 811fcb7..221a17c 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_1.pxi.spice
-* Created: Fri Aug 28 10:54:27 2020
+* Created: Wed Sep 2 10:08:12 2020
*
x_PM_SKY130_FD_SC_LP__NOR2B_1%B_N N_B_N_M1002_g N_B_N_c_43_n N_B_N_M1003_g B_N
+ B_N PM_SKY130_FD_SC_LP__NOR2B_1%B_N
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.spice
index 65f6ef6..2b32870 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_1.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_1.spice
-* Created: Fri Aug 28 10:54:27 2020
+* Created: Wed Sep 2 10:08:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.lvs.report b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.lvs.report
new file mode 100644
index 0000000..a2e126e
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2b_2.sp ('sky130_fd_sc_lp__nor2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2b/sky130_fd_sc_lp__nor2b_2.spice ('sky130_fd_sc_lp__nor2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2b_2 sky130_fd_sc_lp__nor2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pex.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pex.spice
index 59885c5..99b7c5f 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_2.pex.spice
-* Created: Fri Aug 28 10:54:34 2020
+* Created: Wed Sep 2 10:08:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pxi.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pxi.spice
index 99cbee9..c6c27ff 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_2.pxi.spice
-* Created: Fri Aug 28 10:54:34 2020
+* Created: Wed Sep 2 10:08:20 2020
*
x_PM_SKY130_FD_SC_LP__NOR2B_2%B_N N_B_N_c_55_n N_B_N_M1001_g N_B_N_M1003_g B_N
+ N_B_N_c_58_n PM_SKY130_FD_SC_LP__NOR2B_2%B_N
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.spice
index 4f44b75..3ddc805 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_2.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_2.spice
-* Created: Fri Aug 28 10:54:34 2020
+* Created: Wed Sep 2 10:08:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.lvs.report b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.lvs.report
new file mode 100644
index 0000000..e143b91
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2b_4.sp ('sky130_fd_sc_lp__nor2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2b/sky130_fd_sc_lp__nor2b_4.spice ('sky130_fd_sc_lp__nor2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2b_4 sky130_fd_sc_lp__nor2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 4.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pex.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pex.spice
index cec9d93..3d1b294 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_4.pex.spice
-* Created: Fri Aug 28 10:54:42 2020
+* Created: Wed Sep 2 10:08:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pxi.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pxi.spice
index 71e6051..067d733 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_4.pxi.spice
-* Created: Fri Aug 28 10:54:42 2020
+* Created: Wed Sep 2 10:08:27 2020
*
x_PM_SKY130_FD_SC_LP__NOR2B_4%B_N N_B_N_M1012_g N_B_N_M1013_g N_B_N_c_85_n
+ N_B_N_c_86_n B_N N_B_N_c_87_n PM_SKY130_FD_SC_LP__NOR2B_4%B_N
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.spice
index f14fb90..60df6b7 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_4.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_4.spice
-* Created: Fri Aug 28 10:54:42 2020
+* Created: Wed Sep 2 10:08:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.lvs.report b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.lvs.report
new file mode 100644
index 0000000..7aa856d
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2b_lp.sp ('sky130_fd_sc_lp__nor2b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.spice ('sky130_fd_sc_lp__nor2b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2b_lp sky130_fd_sc_lp__nor2b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pex.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pex.spice
index c142819..a62439f 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_lp.pex.spice
-* Created: Fri Aug 28 10:54:51 2020
+* Created: Wed Sep 2 10:08:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pxi.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pxi.spice
index aa11d9d..7142470 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_lp.pxi.spice
-* Created: Fri Aug 28 10:54:51 2020
+* Created: Wed Sep 2 10:08:34 2020
*
x_PM_SKY130_FD_SC_LP__NOR2B_LP%A N_A_M1000_g N_A_M1004_g N_A_M1001_g N_A_c_67_n
+ N_A_c_68_n A A A N_A_c_70_n PM_SKY130_FD_SC_LP__NOR2B_LP%A
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.spice
index a7a795c..352c823 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_lp.spice
-* Created: Fri Aug 28 10:54:51 2020
+* Created: Wed Sep 2 10:08:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.lvs.report b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.lvs.report
new file mode 100644
index 0000000..c569823
--- /dev/null
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor2b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor2b_m.sp ('sky130_fd_sc_lp__nor2b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor2b/sky130_fd_sc_lp__nor2b_m.spice ('sky130_fd_sc_lp__nor2b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor2b_m sky130_fd_sc_lp__nor2b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor2b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor2b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pex.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pex.spice
index 13fb507..2639cde 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pex.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_m.pex.spice
-* Created: Fri Aug 28 10:54:59 2020
+* Created: Wed Sep 2 10:08:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pxi.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pxi.spice
index c21f6c1..68c7916 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pxi.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_m.pxi.spice
-* Created: Fri Aug 28 10:54:59 2020
+* Created: Wed Sep 2 10:08:42 2020
*
x_PM_SKY130_FD_SC_LP__NOR2B_M%B_N N_B_N_M1003_g N_B_N_M1004_g N_B_N_c_52_n
+ N_B_N_c_57_n B_N B_N B_N B_N B_N N_B_N_c_54_n PM_SKY130_FD_SC_LP__NOR2B_M%B_N
diff --git a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.spice b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.spice
index 08e27d0..418a880 100644
--- a/cells/nor2b/sky130_fd_sc_lp__nor2b_m.spice
+++ b/cells/nor2b/sky130_fd_sc_lp__nor2b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor2b_m.spice
-* Created: Fri Aug 28 10:54:59 2020
+* Created: Wed Sep 2 10:08:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_0.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_0.lvs.report
new file mode 100644
index 0000000..a17e880
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_0.sp ('sky130_fd_sc_lp__nor3_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_0.spice ('sky130_fd_sc_lp__nor3_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_0 sky130_fd_sc_lp__nor3_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_0.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_0.pex.spice
index 203311c..9054247 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_0.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_0.pex.spice
-* Created: Fri Aug 28 10:55:07 2020
+* Created: Wed Sep 2 10:08:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_0.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_0.pxi.spice
index 9de1ff6..c690f77 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_0.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_0.pxi.spice
-* Created: Fri Aug 28 10:55:07 2020
+* Created: Wed Sep 2 10:08:49 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_0%A N_A_c_49_n N_A_M1002_g N_A_c_56_n N_A_M1000_g
+ N_A_c_50_n N_A_c_51_n N_A_c_52_n N_A_c_57_n A A A A N_A_c_54_n
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_0.spice b/cells/nor3/sky130_fd_sc_lp__nor3_0.spice
index 08d63d3..f9248a9 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_0.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_0.spice
-* Created: Fri Aug 28 10:55:07 2020
+* Created: Wed Sep 2 10:08:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_1.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_1.lvs.report
new file mode 100644
index 0000000..ad2d1db
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_1.sp ('sky130_fd_sc_lp__nor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_1.spice ('sky130_fd_sc_lp__nor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:08:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_1 sky130_fd_sc_lp__nor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_1.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_1.pex.spice
index 4e29523..698ad14 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_1.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_1.pex.spice
-* Created: Fri Aug 28 10:55:19 2020
+* Created: Wed Sep 2 10:08:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_1.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_1.pxi.spice
index a797c13..6003954 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_1.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_1.pxi.spice
-* Created: Fri Aug 28 10:55:19 2020
+* Created: Wed Sep 2 10:08:57 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_1%A N_A_M1002_g N_A_M1005_g A A N_A_c_40_n N_A_c_41_n
+ PM_SKY130_FD_SC_LP__NOR3_1%A
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_1.spice b/cells/nor3/sky130_fd_sc_lp__nor3_1.spice
index d860a36..e720704 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_1.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_1.spice
-* Created: Fri Aug 28 10:55:19 2020
+* Created: Wed Sep 2 10:08:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_2.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_2.lvs.report
new file mode 100644
index 0000000..29d16d4
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_2.sp ('sky130_fd_sc_lp__nor3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_2.spice ('sky130_fd_sc_lp__nor3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_2 sky130_fd_sc_lp__nor3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_2.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_2.pex.spice
index 819c573..8d35076 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_2.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_2.pex.spice
-* Created: Fri Aug 28 10:55:33 2020
+* Created: Wed Sep 2 10:09:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_2.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_2.pxi.spice
index 43fc34b..d1fe8c7 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_2.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_2.pxi.spice
-* Created: Fri Aug 28 10:55:33 2020
+* Created: Wed Sep 2 10:09:04 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_2%A N_A_M1000_g N_A_c_59_n N_A_M1004_g N_A_c_60_n
+ N_A_M1006_g N_A_M1009_g A A N_A_c_62_n N_A_c_63_n PM_SKY130_FD_SC_LP__NOR3_2%A
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_2.spice b/cells/nor3/sky130_fd_sc_lp__nor3_2.spice
index a2f89f1..1a2e711 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_2.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_2.spice
-* Created: Fri Aug 28 10:55:33 2020
+* Created: Wed Sep 2 10:09:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_4.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_4.lvs.report
new file mode 100644
index 0000000..f3d0b40
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_4.sp ('sky130_fd_sc_lp__nor3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_4.spice ('sky130_fd_sc_lp__nor3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_4 sky130_fd_sc_lp__nor3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_4.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_4.pex.spice
index 46d724a..e86990f 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_4.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_4.pex.spice
-* Created: Fri Aug 28 10:55:42 2020
+* Created: Wed Sep 2 10:09:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_4.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_4.pxi.spice
index 9a5d7fb..29d1663 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_4.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_4.pxi.spice
-* Created: Fri Aug 28 10:55:42 2020
+* Created: Wed Sep 2 10:09:11 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_4%A N_A_c_90_n N_A_M1001_g N_A_M1006_g N_A_c_92_n
+ N_A_M1009_g N_A_M1010_g N_A_c_94_n N_A_M1017_g N_A_M1018_g N_A_c_96_n
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_4.spice b/cells/nor3/sky130_fd_sc_lp__nor3_4.spice
index e2cca63..2ee836f 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_4.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_4.spice
-* Created: Fri Aug 28 10:55:42 2020
+* Created: Wed Sep 2 10:09:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_lp.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_lp.lvs.report
new file mode 100644
index 0000000..d27e6de
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_lp.sp ('sky130_fd_sc_lp__nor3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_lp.spice ('sky130_fd_sc_lp__nor3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_lp sky130_fd_sc_lp__nor3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_lp.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_lp.pex.spice
index bd1723d..bea0ed1 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_lp.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_lp.pex.spice
-* Created: Fri Aug 28 10:55:51 2020
+* Created: Wed Sep 2 10:09:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_lp.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_lp.pxi.spice
index 1ab62fa..9d75d42 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_lp.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_lp.pxi.spice
-* Created: Fri Aug 28 10:55:51 2020
+* Created: Wed Sep 2 10:09:19 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_LP%C N_C_M1000_g N_C_c_52_n N_C_c_53_n N_C_M1002_g
+ N_C_c_58_n N_C_M1001_g N_C_c_55_n N_C_c_59_n C C N_C_c_57_n
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_lp.spice b/cells/nor3/sky130_fd_sc_lp__nor3_lp.spice
index 0752c47..5e751b2 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_lp.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_lp.spice
-* Created: Fri Aug 28 10:55:51 2020
+* Created: Wed Sep 2 10:09:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_m.lvs.report b/cells/nor3/sky130_fd_sc_lp__nor3_m.lvs.report
new file mode 100644
index 0000000..a678293
--- /dev/null
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3_m.sp ('sky130_fd_sc_lp__nor3_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3/sky130_fd_sc_lp__nor3_m.spice ('sky130_fd_sc_lp__nor3_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3_m sky130_fd_sc_lp__nor3_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_m.pex.spice b/cells/nor3/sky130_fd_sc_lp__nor3_m.pex.spice
index 4527ba8..894c99c 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_m.pex.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_m.pex.spice
-* Created: Fri Aug 28 10:56:01 2020
+* Created: Wed Sep 2 10:09:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_m.pxi.spice b/cells/nor3/sky130_fd_sc_lp__nor3_m.pxi.spice
index 32ef726..d2586ab 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_m.pxi.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_m.pxi.spice
-* Created: Fri Aug 28 10:56:01 2020
+* Created: Wed Sep 2 10:09:26 2020
*
x_PM_SKY130_FD_SC_LP__NOR3_M%A N_A_c_47_n N_A_M1002_g N_A_c_54_n N_A_M1000_g
+ N_A_c_48_n N_A_c_49_n N_A_c_50_n N_A_c_55_n A A A A N_A_c_52_n
diff --git a/cells/nor3/sky130_fd_sc_lp__nor3_m.spice b/cells/nor3/sky130_fd_sc_lp__nor3_m.spice
index 79f24d0..a91b935 100644
--- a/cells/nor3/sky130_fd_sc_lp__nor3_m.spice
+++ b/cells/nor3/sky130_fd_sc_lp__nor3_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3_m.spice
-* Created: Fri Aug 28 10:56:01 2020
+* Created: Wed Sep 2 10:09:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.lvs.report b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.lvs.report
new file mode 100644
index 0000000..30eda07
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3b_1.sp ('sky130_fd_sc_lp__nor3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3b/sky130_fd_sc_lp__nor3b_1.spice ('sky130_fd_sc_lp__nor3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3b_1 sky130_fd_sc_lp__nor3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pex.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pex.spice
index 47a7187..bf5a7fc 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_1.pex.spice
-* Created: Fri Aug 28 10:56:10 2020
+* Created: Wed Sep 2 10:09:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pxi.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pxi.spice
index 3254e0b..bff73b7 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_1.pxi.spice
-* Created: Fri Aug 28 10:56:10 2020
+* Created: Wed Sep 2 10:09:34 2020
*
x_PM_SKY130_FD_SC_LP__NOR3B_1%C_N N_C_N_c_52_n N_C_N_M1000_g N_C_N_c_53_n
+ N_C_N_M1004_g C_N C_N PM_SKY130_FD_SC_LP__NOR3B_1%C_N
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.spice
index 05b9862..c26ea88 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_1.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_1.spice
-* Created: Fri Aug 28 10:56:10 2020
+* Created: Wed Sep 2 10:09:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.lvs.report b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.lvs.report
new file mode 100644
index 0000000..08cc814
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3b_2.sp ('sky130_fd_sc_lp__nor3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3b/sky130_fd_sc_lp__nor3b_2.spice ('sky130_fd_sc_lp__nor3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3b_2 sky130_fd_sc_lp__nor3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pex.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pex.spice
index 2a9a427..a2b0455 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_2.pex.spice
-* Created: Fri Aug 28 10:56:25 2020
+* Created: Wed Sep 2 10:09:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pxi.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pxi.spice
index 3152db5..60f70d8 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_2.pxi.spice
-* Created: Fri Aug 28 10:56:25 2020
+* Created: Wed Sep 2 10:09:41 2020
*
x_PM_SKY130_FD_SC_LP__NOR3B_2%C_N N_C_N_M1012_g N_C_N_M1001_g N_C_N_c_79_n
+ N_C_N_c_84_n C_N C_N N_C_N_c_80_n N_C_N_c_81_n PM_SKY130_FD_SC_LP__NOR3B_2%C_N
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.spice
index 4d37c99..69e6381 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_2.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_2.spice
-* Created: Fri Aug 28 10:56:25 2020
+* Created: Wed Sep 2 10:09:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.lvs.report b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.lvs.report
new file mode 100644
index 0000000..8abfc8e
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3b_4.sp ('sky130_fd_sc_lp__nor3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3b/sky130_fd_sc_lp__nor3b_4.spice ('sky130_fd_sc_lp__nor3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3b_4 sky130_fd_sc_lp__nor3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pex.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pex.spice
index e3e0031..40bdb37 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_4.pex.spice
-* Created: Fri Aug 28 10:56:40 2020
+* Created: Wed Sep 2 10:09:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pxi.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pxi.spice
index 238bc8a..194b876 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_4.pxi.spice
-* Created: Fri Aug 28 10:56:40 2020
+* Created: Wed Sep 2 10:09:49 2020
*
x_PM_SKY130_FD_SC_LP__NOR3B_4%C_N N_C_N_M1013_g N_C_N_c_105_n N_C_N_M1007_g C_N
+ N_C_N_c_107_n PM_SKY130_FD_SC_LP__NOR3B_4%C_N
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.spice
index 434c4f3..4452830 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_4.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_4.spice
-* Created: Fri Aug 28 10:56:40 2020
+* Created: Wed Sep 2 10:09:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.lvs.report b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.lvs.report
new file mode 100644
index 0000000..765d79f
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3b_lp.sp ('sky130_fd_sc_lp__nor3b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.spice ('sky130_fd_sc_lp__nor3b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3b_lp sky130_fd_sc_lp__nor3b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pex.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pex.spice
index 48f711f..6aa1659 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_lp.pex.spice
-* Created: Fri Aug 28 10:56:49 2020
+* Created: Wed Sep 2 10:09:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pxi.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pxi.spice
index 43d944c..25994d7 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_lp.pxi.spice
-* Created: Fri Aug 28 10:56:49 2020
+* Created: Wed Sep 2 10:09:56 2020
*
x_PM_SKY130_FD_SC_LP__NOR3B_LP%A N_A_c_70_n N_A_M1001_g N_A_c_71_n N_A_c_72_n
+ N_A_M1010_g N_A_c_73_n N_A_M1011_g N_A_c_74_n N_A_c_75_n A A N_A_c_77_n
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.spice
index 50f47cf..d405fba 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_lp.spice
-* Created: Fri Aug 28 10:56:49 2020
+* Created: Wed Sep 2 10:09:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.lvs.report b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.lvs.report
new file mode 100644
index 0000000..d4f766e
--- /dev/null
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor3b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor3b_m.sp ('sky130_fd_sc_lp__nor3b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor3b/sky130_fd_sc_lp__nor3b_m.spice ('sky130_fd_sc_lp__nor3b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:09:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor3b_m sky130_fd_sc_lp__nor3b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor3b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor3b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pex.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pex.spice
index 39b39fd..98ed95c 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pex.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_m.pex.spice
-* Created: Fri Aug 28 10:56:58 2020
+* Created: Wed Sep 2 10:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pxi.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pxi.spice
index 42644ce..ba61a8e 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pxi.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_m.pxi.spice
-* Created: Fri Aug 28 10:56:58 2020
+* Created: Wed Sep 2 10:10:03 2020
*
x_PM_SKY130_FD_SC_LP__NOR3B_M%C_N N_C_N_c_67_n N_C_N_M1005_g N_C_N_c_61_n
+ N_C_N_M1003_g N_C_N_c_62_n N_C_N_c_63_n N_C_N_c_64_n C_N C_N N_C_N_c_66_n
diff --git a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.spice b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.spice
index d460f1a..5ac769c 100644
--- a/cells/nor3b/sky130_fd_sc_lp__nor3b_m.spice
+++ b/cells/nor3b/sky130_fd_sc_lp__nor3b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor3b_m.spice
-* Created: Fri Aug 28 10:56:58 2020
+* Created: Wed Sep 2 10:10:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_0.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_0.lvs.report
new file mode 100644
index 0000000..78077a1
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_0.sp ('sky130_fd_sc_lp__nor4_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_0.spice ('sky130_fd_sc_lp__nor4_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_0 sky130_fd_sc_lp__nor4_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_0
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_0.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_0.pex.spice
index 8bdd1d9..c217b34 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_0.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_0.pex.spice
-* Created: Fri Aug 28 10:57:08 2020
+* Created: Wed Sep 2 10:10:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_0.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_0.pxi.spice
index cb5798e..a7d438b 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_0.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_0.pxi.spice
-* Created: Fri Aug 28 10:57:08 2020
+* Created: Wed Sep 2 10:10:11 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_0%A N_A_M1006_g N_A_c_65_n N_A_M1003_g N_A_c_62_n
+ N_A_c_68_n N_A_c_69_n A A N_A_c_64_n PM_SKY130_FD_SC_LP__NOR4_0%A
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_0.spice b/cells/nor4/sky130_fd_sc_lp__nor4_0.spice
index 9f77f81..9c2b161 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_0.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_0.spice
-* Created: Fri Aug 28 10:57:08 2020
+* Created: Wed Sep 2 10:10:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_1.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_1.lvs.report
new file mode 100644
index 0000000..9d953ac
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_1.sp ('sky130_fd_sc_lp__nor4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_1.spice ('sky130_fd_sc_lp__nor4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_1 sky130_fd_sc_lp__nor4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_1.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_1.pex.spice
index 8a82012..ca87f6e 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_1.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_1.pex.spice
-* Created: Fri Aug 28 10:57:18 2020
+* Created: Wed Sep 2 10:10:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_1.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_1.pxi.spice
index 2c3dc15..399449d 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_1.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_1.pxi.spice
-* Created: Fri Aug 28 10:57:18 2020
+* Created: Wed Sep 2 10:10:18 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_1%A N_A_M1002_g N_A_M1007_g A N_A_c_50_n N_A_c_51_n
+ PM_SKY130_FD_SC_LP__NOR4_1%A
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_1.spice b/cells/nor4/sky130_fd_sc_lp__nor4_1.spice
index f337a61..c71387a 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_1.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_1.spice
-* Created: Fri Aug 28 10:57:18 2020
+* Created: Wed Sep 2 10:10:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_2.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_2.lvs.report
new file mode 100644
index 0000000..4ee4fcd
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_2.sp ('sky130_fd_sc_lp__nor4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_2.spice ('sky130_fd_sc_lp__nor4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_2 sky130_fd_sc_lp__nor4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_2.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_2.pex.spice
index 08cdbbc..7c915ee 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_2.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_2.pex.spice
-* Created: Fri Aug 28 10:57:30 2020
+* Created: Wed Sep 2 10:10:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_2.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_2.pxi.spice
index a01ade2..a0f6a92 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_2.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_2.pxi.spice
-* Created: Fri Aug 28 10:57:30 2020
+* Created: Wed Sep 2 10:10:25 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_2%B N_B_M1003_g N_B_M1007_g N_B_M1004_g N_B_M1015_g
+ N_B_c_86_n N_B_c_87_n N_B_c_88_n N_B_c_97_n N_B_c_89_n B B N_B_c_91_n
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_2.spice b/cells/nor4/sky130_fd_sc_lp__nor4_2.spice
index 2fe3b46..ac98f0b 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_2.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_2.spice
-* Created: Fri Aug 28 10:57:30 2020
+* Created: Wed Sep 2 10:10:25 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_4.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_4.lvs.report
new file mode 100644
index 0000000..bbf5a29
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_4.sp ('sky130_fd_sc_lp__nor4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_4.spice ('sky130_fd_sc_lp__nor4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_4 sky130_fd_sc_lp__nor4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_4.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_4.pex.spice
index a6e3b01..71f89b3 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_4.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_4.pex.spice
-* Created: Fri Aug 28 10:57:42 2020
+* Created: Wed Sep 2 10:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_4.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_4.pxi.spice
index 775e75f..d0efa75 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_4.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_4.pxi.spice
-* Created: Fri Aug 28 10:57:42 2020
+* Created: Wed Sep 2 10:10:32 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_4%A N_A_M1002_g N_A_c_117_n N_A_M1004_g N_A_M1006_g
+ N_A_c_119_n N_A_M1011_g N_A_M1014_g N_A_c_121_n N_A_M1012_g N_A_M1019_g
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_4.spice b/cells/nor4/sky130_fd_sc_lp__nor4_4.spice
index b0b280f..3c28ed4 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_4.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_4.spice
-* Created: Fri Aug 28 10:57:42 2020
+* Created: Wed Sep 2 10:10:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_lp.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_lp.lvs.report
new file mode 100644
index 0000000..c83f70b
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_lp.sp ('sky130_fd_sc_lp__nor4_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_lp.spice ('sky130_fd_sc_lp__nor4_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_lp sky130_fd_sc_lp__nor4_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C D B A Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_lp.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_lp.pex.spice
index f8d2e94..7c91a81 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_lp.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_lp.pex.spice
-* Created: Fri Aug 28 10:57:49 2020
+* Created: Wed Sep 2 10:10:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_lp.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_lp.pxi.spice
index 683c1ea..4a4e55b 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_lp.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_lp.pxi.spice
-* Created: Fri Aug 28 10:57:49 2020
+* Created: Wed Sep 2 10:10:40 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_LP%C N_C_M1005_g N_C_M1007_g N_C_c_72_n N_C_M1001_g
+ N_C_c_74_n N_C_c_75_n C C N_C_c_77_n PM_SKY130_FD_SC_LP__NOR4_LP%C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_lp.spice b/cells/nor4/sky130_fd_sc_lp__nor4_lp.spice
index 3b2d8b1..541e7e7 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_lp.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_lp.spice
-* Created: Fri Aug 28 10:57:49 2020
+* Created: Wed Sep 2 10:10:40 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_m.lvs.report b/cells/nor4/sky130_fd_sc_lp__nor4_m.lvs.report
new file mode 100644
index 0000000..38187a2
--- /dev/null
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4_m.sp ('sky130_fd_sc_lp__nor4_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4/sky130_fd_sc_lp__nor4_m.spice ('sky130_fd_sc_lp__nor4_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4_m sky130_fd_sc_lp__nor4_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_m.pex.spice b/cells/nor4/sky130_fd_sc_lp__nor4_m.pex.spice
index 51b115d..faf9247 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_m.pex.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_m.pex.spice
-* Created: Fri Aug 28 10:57:57 2020
+* Created: Wed Sep 2 10:10:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_m.pxi.spice b/cells/nor4/sky130_fd_sc_lp__nor4_m.pxi.spice
index fce52da..0635b56 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_m.pxi.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_m.pxi.spice
-* Created: Fri Aug 28 10:57:57 2020
+* Created: Wed Sep 2 10:10:47 2020
*
x_PM_SKY130_FD_SC_LP__NOR4_M%A N_A_M1003_g N_A_c_65_n N_A_M1002_g N_A_c_62_n
+ N_A_c_68_n N_A_c_69_n A A N_A_c_64_n PM_SKY130_FD_SC_LP__NOR4_M%A
diff --git a/cells/nor4/sky130_fd_sc_lp__nor4_m.spice b/cells/nor4/sky130_fd_sc_lp__nor4_m.spice
index 5fa4b2a..4cb1457 100644
--- a/cells/nor4/sky130_fd_sc_lp__nor4_m.spice
+++ b/cells/nor4/sky130_fd_sc_lp__nor4_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4_m.spice
-* Created: Fri Aug 28 10:57:57 2020
+* Created: Wed Sep 2 10:10:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.lvs.report b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.lvs.report
new file mode 100644
index 0000000..d3c2151
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4b_1.sp ('sky130_fd_sc_lp__nor4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4b/sky130_fd_sc_lp__nor4b_1.spice ('sky130_fd_sc_lp__nor4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4b_1 sky130_fd_sc_lp__nor4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pex.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pex.spice
index 99b694d..54aa9a5 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_1.pex.spice
-* Created: Fri Aug 28 10:58:06 2020
+* Created: Wed Sep 2 10:10:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pxi.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pxi.spice
index 51e3c44..adb6546 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_1.pxi.spice
-* Created: Fri Aug 28 10:58:06 2020
+* Created: Wed Sep 2 10:10:55 2020
*
x_PM_SKY130_FD_SC_LP__NOR4B_1%D_N N_D_N_M1005_g N_D_N_M1009_g N_D_N_c_63_n
+ N_D_N_c_64_n D_N N_D_N_c_65_n PM_SKY130_FD_SC_LP__NOR4B_1%D_N
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.spice
index 61853e1..3fe9715 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_1.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_1.spice
-* Created: Fri Aug 28 10:58:06 2020
+* Created: Wed Sep 2 10:10:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.lvs.report b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.lvs.report
new file mode 100644
index 0000000..4d4dd19
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4b_2.sp ('sky130_fd_sc_lp__nor4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4b/sky130_fd_sc_lp__nor4b_2.spice ('sky130_fd_sc_lp__nor4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:10:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4b_2 sky130_fd_sc_lp__nor4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pex.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pex.spice
index ac91dd6..869640a 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_2.pex.spice
-* Created: Fri Aug 28 10:58:15 2020
+* Created: Wed Sep 2 10:11:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pxi.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pxi.spice
index f87ba3e..d34d2c6 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_2.pxi.spice
-* Created: Fri Aug 28 10:58:15 2020
+* Created: Wed Sep 2 10:11:01 2020
*
x_PM_SKY130_FD_SC_LP__NOR4B_2%D_N N_D_N_M1012_g N_D_N_c_90_n N_D_N_M1008_g D_N
+ N_D_N_c_92_n PM_SKY130_FD_SC_LP__NOR4B_2%D_N
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.spice
index a16392b..cd21e27 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_2.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_2.spice
-* Created: Fri Aug 28 10:58:15 2020
+* Created: Wed Sep 2 10:11:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.lvs.report b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.lvs.report
new file mode 100644
index 0000000..b6b3afa
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4b_4.sp ('sky130_fd_sc_lp__nor4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4b/sky130_fd_sc_lp__nor4b_4.spice ('sky130_fd_sc_lp__nor4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4b_4 sky130_fd_sc_lp__nor4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pex.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pex.spice
index edfb056..33c0e37 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_4.pex.spice
-* Created: Fri Aug 28 10:58:23 2020
+* Created: Wed Sep 2 10:11:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pxi.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pxi.spice
index ad6e6db..5edbb79 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_4.pxi.spice
-* Created: Fri Aug 28 10:58:23 2020
+* Created: Wed Sep 2 10:11:09 2020
*
x_PM_SKY130_FD_SC_LP__NOR4B_4%D_N N_D_N_M1033_g N_D_N_M1027_g D_N N_D_N_c_146_n
+ N_D_N_c_147_n PM_SKY130_FD_SC_LP__NOR4B_4%D_N
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.spice
index 26d982e..c51aae0 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_4.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_4.spice
-* Created: Fri Aug 28 10:58:23 2020
+* Created: Wed Sep 2 10:11:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.lvs.report b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.lvs.report
new file mode 100644
index 0000000..8541557
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4b_lp.sp ('sky130_fd_sc_lp__nor4b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.spice ('sky130_fd_sc_lp__nor4b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4b_lp sky130_fd_sc_lp__nor4b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pex.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pex.spice
index 801e320..0f74f10 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_lp.pex.spice
-* Created: Fri Aug 28 10:58:34 2020
+* Created: Wed Sep 2 10:11:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pxi.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pxi.spice
index efa2a46..88e997d 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_lp.pxi.spice
-* Created: Fri Aug 28 10:58:34 2020
+* Created: Wed Sep 2 10:11:16 2020
*
x_PM_SKY130_FD_SC_LP__NOR4B_LP%D_N N_D_N_c_86_n N_D_N_M1013_g N_D_N_c_87_n
+ N_D_N_M1009_g N_D_N_c_88_n N_D_N_c_89_n N_D_N_M1006_g N_D_N_c_95_n
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.spice
index 38c0230..1fa12d3 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_lp.spice
-* Created: Fri Aug 28 10:58:34 2020
+* Created: Wed Sep 2 10:11:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.lvs.report b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.lvs.report
new file mode 100644
index 0000000..68f30f6
--- /dev/null
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4b_m.sp ('sky130_fd_sc_lp__nor4b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4b/sky130_fd_sc_lp__nor4b_m.spice ('sky130_fd_sc_lp__nor4b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4b_m sky130_fd_sc_lp__nor4b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N A B C VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pex.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pex.spice
index 6ca911f..abb0494 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pex.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_m.pex.spice
-* Created: Fri Aug 28 10:58:46 2020
+* Created: Wed Sep 2 10:11:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pxi.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pxi.spice
index c6edfc4..8ee579b 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pxi.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_m.pxi.spice
-* Created: Fri Aug 28 10:58:46 2020
+* Created: Wed Sep 2 10:11:24 2020
*
x_PM_SKY130_FD_SC_LP__NOR4B_M%D_N N_D_N_M1008_g N_D_N_M1001_g N_D_N_c_78_n
+ N_D_N_c_83_n D_N D_N D_N D_N D_N N_D_N_c_80_n PM_SKY130_FD_SC_LP__NOR4B_M%D_N
diff --git a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.spice b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.spice
index 84782ea..4c35cb5 100644
--- a/cells/nor4b/sky130_fd_sc_lp__nor4b_m.spice
+++ b/cells/nor4b/sky130_fd_sc_lp__nor4b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4b_m.spice
-* Created: Fri Aug 28 10:58:46 2020
+* Created: Wed Sep 2 10:11:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.lvs.report b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.lvs.report
new file mode 100644
index 0000000..190dadd
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4bb_1.sp ('sky130_fd_sc_lp__nor4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.spice ('sky130_fd_sc_lp__nor4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4bb_1 sky130_fd_sc_lp__nor4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4bb_1
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N B A C_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pex.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pex.spice
index 49d0f4a..6cf5a97 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_1.pex.spice
-* Created: Fri Aug 28 10:58:54 2020
+* Created: Wed Sep 2 10:11:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pxi.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pxi.spice
index 1b6107b..1974980 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_1.pxi.spice
-* Created: Fri Aug 28 10:58:54 2020
+* Created: Wed Sep 2 10:11:32 2020
*
x_PM_SKY130_FD_SC_LP__NOR4BB_1%D_N N_D_N_M1002_g N_D_N_M1006_g D_N D_N D_N
+ N_D_N_c_75_n PM_SKY130_FD_SC_LP__NOR4BB_1%D_N
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.spice
index 9ad7bb7..cc03114 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_1.spice
-* Created: Fri Aug 28 10:58:54 2020
+* Created: Wed Sep 2 10:11:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.lvs.report b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.lvs.report
new file mode 100644
index 0000000..4131662
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4bb_2.sp ('sky130_fd_sc_lp__nor4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.spice ('sky130_fd_sc_lp__nor4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4bb_2 sky130_fd_sc_lp__nor4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4bb_2
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N D_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pex.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pex.spice
index 8d82d93..a387ba3 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_2.pex.spice
-* Created: Fri Aug 28 10:59:02 2020
+* Created: Wed Sep 2 10:11:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pxi.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pxi.spice
index ac47175..c9d0ab7 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_2.pxi.spice
-* Created: Fri Aug 28 10:59:02 2020
+* Created: Wed Sep 2 10:11:39 2020
*
x_PM_SKY130_FD_SC_LP__NOR4BB_2%C_N N_C_N_M1006_g N_C_N_c_119_n N_C_N_M1014_g
+ N_C_N_c_121_n C_N C_N N_C_N_c_118_n PM_SKY130_FD_SC_LP__NOR4BB_2%C_N
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.spice
index cbc10e6..9dbcc52 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_2.spice
-* Created: Fri Aug 28 10:59:02 2020
+* Created: Wed Sep 2 10:11:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.lvs.report b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.lvs.report
new file mode 100644
index 0000000..c8bcc4c
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4bb_4.sp ('sky130_fd_sc_lp__nor4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.spice ('sky130_fd_sc_lp__nor4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4bb_4 sky130_fd_sc_lp__nor4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4bb_4
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C_N B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pex.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pex.spice
index 041314e..b175d15 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_4.pex.spice
-* Created: Fri Aug 28 10:59:11 2020
+* Created: Wed Sep 2 10:11:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pxi.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pxi.spice
index dfb6adf..5818ddc 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_4.pxi.spice
-* Created: Fri Aug 28 10:59:11 2020
+* Created: Wed Sep 2 10:11:46 2020
*
x_PM_SKY130_FD_SC_LP__NOR4BB_4%D_N N_D_N_M1015_g N_D_N_M1032_g D_N N_D_N_c_161_n
+ N_D_N_c_162_n PM_SKY130_FD_SC_LP__NOR4BB_4%D_N
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.spice
index a544c96..3e46f14 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_4.spice
-* Created: Fri Aug 28 10:59:11 2020
+* Created: Wed Sep 2 10:11:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.lvs.report b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.lvs.report
new file mode 100644
index 0000000..c518770
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4bb_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4bb_lp.sp ('sky130_fd_sc_lp__nor4bb_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.spice ('sky130_fd_sc_lp__nor4bb_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4bb_lp sky130_fd_sc_lp__nor4bb_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4bb_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4bb_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A D_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pex.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pex.spice
index d875c41..dc24884 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_lp.pex.spice
-* Created: Fri Aug 28 10:59:20 2020
+* Created: Wed Sep 2 10:11:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pxi.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pxi.spice
index 62da5a6..150b0a1 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_lp.pxi.spice
-* Created: Fri Aug 28 10:59:20 2020
+* Created: Wed Sep 2 10:11:54 2020
*
x_PM_SKY130_FD_SC_LP__NOR4BB_LP%C_N N_C_N_c_102_n N_C_N_M1005_g N_C_N_c_103_n
+ N_C_N_M1007_g N_C_N_c_104_n N_C_N_c_105_n N_C_N_M1001_g N_C_N_c_111_n
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.spice
index e2d377f..0fc52b1 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_lp.spice
-* Created: Fri Aug 28 10:59:20 2020
+* Created: Wed Sep 2 10:11:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.lvs.report b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.lvs.report
new file mode 100644
index 0000000..a60c583
--- /dev/null
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__nor4bb_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__nor4bb_m.sp ('sky130_fd_sc_lp__nor4bb_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.spice ('sky130_fd_sc_lp__nor4bb_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:11:58 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__nor4bb_m sky130_fd_sc_lp__nor4bb_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__nor4bb_m
+SOURCE CELL NAME: sky130_fd_sc_lp__nor4bb_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N B A C_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pex.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pex.spice
index 0c8d4ce..9dc9435 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pex.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_m.pex.spice
-* Created: Fri Aug 28 10:59:28 2020
+* Created: Wed Sep 2 10:12:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pxi.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pxi.spice
index fcbde01..41d4a52 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pxi.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_m.pxi.spice
-* Created: Fri Aug 28 10:59:28 2020
+* Created: Wed Sep 2 10:12:01 2020
*
x_PM_SKY130_FD_SC_LP__NOR4BB_M%D_N N_D_N_M1010_g N_D_N_M1002_g N_D_N_c_82_n
+ N_D_N_c_86_n D_N D_N N_D_N_c_88_n PM_SKY130_FD_SC_LP__NOR4BB_M%D_N
diff --git a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.spice b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.spice
index b262c59..e9cde5e 100644
--- a/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.spice
+++ b/cells/nor4bb/sky130_fd_sc_lp__nor4bb_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__nor4bb_m.spice
-* Created: Fri Aug 28 10:59:28 2020
+* Created: Wed Sep 2 10:12:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.lvs.report
new file mode 100644
index 0000000..fb5d1aa
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_0.sp ('sky130_fd_sc_lp__o2111a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_0.spice ('sky130_fd_sc_lp__o2111a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_0 sky130_fd_sc_lp__o2111a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pex.spice
index 08e1b23..5ac4d40 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_0.pex.spice
-* Created: Fri Aug 28 10:59:40 2020
+* Created: Wed Sep 2 10:12:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pxi.spice
index bbcf553..7e516bb 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_0.pxi.spice
-* Created: Fri Aug 28 10:59:40 2020
+* Created: Wed Sep 2 10:12:08 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_0%A_80_21# N_A_80_21#_M1001_s N_A_80_21#_M1008_d
+ N_A_80_21#_M1011_d N_A_80_21#_M1003_g N_A_80_21#_c_95_n N_A_80_21#_M1002_g
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.spice
index 2019eef..3a598a8 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_0.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_0.spice
-* Created: Fri Aug 28 10:59:40 2020
+* Created: Wed Sep 2 10:12:08 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.lvs.report
new file mode 100644
index 0000000..a68f0be
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_1.sp ('sky130_fd_sc_lp__o2111a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_1.spice ('sky130_fd_sc_lp__o2111a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_1 sky130_fd_sc_lp__o2111a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pex.spice
index 3386e23..be6382d 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_1.pex.spice
-* Created: Fri Aug 28 10:59:54 2020
+* Created: Wed Sep 2 10:12:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pxi.spice
index 060f180..eff5429 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_1.pxi.spice
-* Created: Fri Aug 28 10:59:54 2020
+* Created: Wed Sep 2 10:12:16 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_1%A_80_21# N_A_80_21#_M1005_s N_A_80_21#_M1010_d
+ N_A_80_21#_M1001_d N_A_80_21#_M1003_g N_A_80_21#_M1011_g N_A_80_21#_c_66_n
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.spice
index 7b4f8aa..de170af 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_1.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_1.spice
-* Created: Fri Aug 28 10:59:54 2020
+* Created: Wed Sep 2 10:12:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.lvs.report
new file mode 100644
index 0000000..5d93d62
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_2.sp ('sky130_fd_sc_lp__o2111a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_2.spice ('sky130_fd_sc_lp__o2111a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:19 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_2 sky130_fd_sc_lp__o2111a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pex.spice
index cca5277..ff97f3b 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_2.pex.spice
-* Created: Fri Aug 28 11:00:03 2020
+* Created: Wed Sep 2 10:12:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pxi.spice
index 2175d3c..95baf69 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_2.pxi.spice
-* Created: Fri Aug 28 11:00:03 2020
+* Created: Wed Sep 2 10:12:23 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_2%A_80_21# N_A_80_21#_M1001_s N_A_80_21#_M1003_d
+ N_A_80_21#_M1004_d N_A_80_21#_c_70_n N_A_80_21#_M1005_g N_A_80_21#_c_76_n
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.spice
index b34d969..a875d4f 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_2.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_2.spice
-* Created: Fri Aug 28 11:00:03 2020
+* Created: Wed Sep 2 10:12:23 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.lvs.report
new file mode 100644
index 0000000..eb14091
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_4.sp ('sky130_fd_sc_lp__o2111a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_4.spice ('sky130_fd_sc_lp__o2111a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:27 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_4 sky130_fd_sc_lp__o2111a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pex.spice
index b52676b..505a065 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_4.pex.spice
-* Created: Fri Aug 28 11:00:13 2020
+* Created: Wed Sep 2 10:12:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pxi.spice
index 65889b6..6ae285d 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_4.pxi.spice
-* Created: Fri Aug 28 11:00:13 2020
+* Created: Wed Sep 2 10:12:30 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_4%D1 N_D1_M1013_g N_D1_c_147_n N_D1_M1018_g
+ N_D1_M1026_g N_D1_c_149_n N_D1_M1021_g D1 N_D1_c_151_n
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.spice
index c04804a..84d789e 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_4.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_4.spice
-* Created: Fri Aug 28 11:00:13 2020
+* Created: Wed Sep 2 10:12:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.lvs.report
new file mode 100644
index 0000000..d8a945e
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_lp.sp ('sky130_fd_sc_lp__o2111a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.spice ('sky130_fd_sc_lp__o2111a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:34 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_lp sky130_fd_sc_lp__o2111a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 D1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pex.spice
index 87f56c1..734d9d1 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_lp.pex.spice
-* Created: Fri Aug 28 11:00:22 2020
+* Created: Wed Sep 2 10:12:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pxi.spice
index a7bd0e5..8c41659 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_lp.pxi.spice
-* Created: Fri Aug 28 11:00:22 2020
+* Created: Wed Sep 2 10:12:37 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_LP%A1 N_A1_M1011_g N_A1_M1012_g N_A1_c_83_n
+ N_A1_c_88_n A1 N_A1_c_84_n N_A1_c_85_n PM_SKY130_FD_SC_LP__O2111A_LP%A1
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.spice
index 2f785f2..772ad0b 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_lp.spice
-* Created: Fri Aug 28 11:00:22 2020
+* Created: Wed Sep 2 10:12:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.lvs.report b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.lvs.report
new file mode 100644
index 0000000..062dd46
--- /dev/null
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111a_m.sp ('sky130_fd_sc_lp__o2111a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111a/sky130_fd_sc_lp__o2111a_m.spice ('sky130_fd_sc_lp__o2111a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111a_m sky130_fd_sc_lp__o2111a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pex.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pex.spice
index d466e80..bf0c039 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pex.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_m.pex.spice
-* Created: Fri Aug 28 11:00:30 2020
+* Created: Wed Sep 2 10:12:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pxi.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pxi.spice
index 2029315..8708a2b 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pxi.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_m.pxi.spice
-* Created: Fri Aug 28 11:00:30 2020
+* Created: Wed Sep 2 10:12:44 2020
*
x_PM_SKY130_FD_SC_LP__O2111A_M%A_80_21# N_A_80_21#_M1000_s N_A_80_21#_M1011_d
+ N_A_80_21#_M1010_d N_A_80_21#_M1004_g N_A_80_21#_c_90_n N_A_80_21#_M1001_g
diff --git a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.spice b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.spice
index 56199f9..34cad27 100644
--- a/cells/o2111a/sky130_fd_sc_lp__o2111a_m.spice
+++ b/cells/o2111a/sky130_fd_sc_lp__o2111a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111a_m.spice
-* Created: Fri Aug 28 11:00:30 2020
+* Created: Wed Sep 2 10:12:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.lvs.report
new file mode 100644
index 0000000..c4fb4e4
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_0.sp ('sky130_fd_sc_lp__o2111ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.spice ('sky130_fd_sc_lp__o2111ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_0 sky130_fd_sc_lp__o2111ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pex.spice
index f5d1e7c..6de6101 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_0.pex.spice
-* Created: Fri Aug 28 11:00:42 2020
+* Created: Wed Sep 2 10:12:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pxi.spice
index 7858dc8..72feac8 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_0.pxi.spice
-* Created: Fri Aug 28 11:00:42 2020
+* Created: Wed Sep 2 10:12:52 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_0%D1 N_D1_M1003_g N_D1_M1006_g N_D1_c_74_n
+ N_D1_c_75_n N_D1_c_76_n D1 D1 D1 N_D1_c_78_n PM_SKY130_FD_SC_LP__O2111AI_0%D1
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.spice
index 783f827..37d7a2b 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_0.spice
-* Created: Fri Aug 28 11:00:42 2020
+* Created: Wed Sep 2 10:12:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.lvs.report
new file mode 100644
index 0000000..d150722
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_1.sp ('sky130_fd_sc_lp__o2111ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.spice ('sky130_fd_sc_lp__o2111ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:12:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_1 sky130_fd_sc_lp__o2111ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pex.spice
index 01a6c70..e851415 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_1.pex.spice
-* Created: Fri Aug 28 11:00:55 2020
+* Created: Wed Sep 2 10:13:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pxi.spice
index e55842e..6d44429 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_1.pxi.spice
-* Created: Fri Aug 28 11:00:55 2020
+* Created: Wed Sep 2 10:13:00 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_1%D1 N_D1_M1002_g N_D1_M1009_g D1 D1 N_D1_c_55_n
+ N_D1_c_56_n PM_SKY130_FD_SC_LP__O2111AI_1%D1
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.spice
index a9d2014..14c29ed 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_1.spice
-* Created: Fri Aug 28 11:00:55 2020
+* Created: Wed Sep 2 10:13:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.lvs.report
new file mode 100644
index 0000000..af8b62a
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_2.sp ('sky130_fd_sc_lp__o2111ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.spice ('sky130_fd_sc_lp__o2111ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_2 sky130_fd_sc_lp__o2111ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pex.spice
index 52fe279..09d8ac9 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_2.pex.spice
-* Created: Fri Aug 28 11:01:03 2020
+* Created: Wed Sep 2 10:13:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pxi.spice
index 9622489..e42bb0c 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_2.pxi.spice
-* Created: Fri Aug 28 11:01:03 2020
+* Created: Wed Sep 2 10:13:07 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_2%D1 N_D1_c_90_n N_D1_M1012_g N_D1_M1009_g
+ N_D1_c_92_n N_D1_M1015_g N_D1_M1018_g D1 D1 N_D1_c_95_n
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.spice
index 5bf6e56..c198d6d 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_2.spice
-* Created: Fri Aug 28 11:01:03 2020
+* Created: Wed Sep 2 10:13:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.lvs.report
new file mode 100644
index 0000000..9a56afc
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_4.sp ('sky130_fd_sc_lp__o2111ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.spice ('sky130_fd_sc_lp__o2111ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_4 sky130_fd_sc_lp__o2111ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pex.spice
index 414b55c..6c9894b 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_4.pex.spice
-* Created: Fri Aug 28 11:01:11 2020
+* Created: Wed Sep 2 10:13:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pxi.spice
index ed39c1c..58e876c 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_4.pxi.spice
-* Created: Fri Aug 28 11:01:11 2020
+* Created: Wed Sep 2 10:13:15 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_4%D1 N_D1_M1010_g N_D1_M1000_g N_D1_M1017_g
+ N_D1_M1011_g N_D1_M1019_g N_D1_M1024_g N_D1_M1037_g N_D1_M1036_g N_D1_c_160_n
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.spice
index e7d02ff..a6bc417 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_4.spice
-* Created: Fri Aug 28 11:01:11 2020
+* Created: Wed Sep 2 10:13:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.lvs.report
new file mode 100644
index 0000000..35b42f1
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_lp.sp ('sky130_fd_sc_lp__o2111ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.spice ('sky130_fd_sc_lp__o2111ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_lp sky130_fd_sc_lp__o2111ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pex.spice
index 22c5212..3f3a05b 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_lp.pex.spice
-* Created: Fri Aug 28 11:01:20 2020
+* Created: Wed Sep 2 10:13:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pxi.spice
index d5b3aab..f5e5c33 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_lp.pxi.spice
-* Created: Fri Aug 28 11:01:20 2020
+* Created: Wed Sep 2 10:13:22 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_LP%D1 N_D1_M1008_g N_D1_M1002_g N_D1_c_67_n
+ N_D1_c_68_n D1 N_D1_c_69_n N_D1_c_70_n PM_SKY130_FD_SC_LP__O2111AI_LP%D1
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.spice
index 306ff18..dcd1b9f 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_lp.spice
-* Created: Fri Aug 28 11:01:20 2020
+* Created: Wed Sep 2 10:13:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.lvs.report b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.lvs.report
new file mode 100644
index 0000000..ba9ffbe
--- /dev/null
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2111ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2111ai_m.sp ('sky130_fd_sc_lp__o2111ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.spice ('sky130_fd_sc_lp__o2111ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2111ai_m sky130_fd_sc_lp__o2111ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2111ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o2111ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D1 C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pex.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pex.spice
index e6331dc..95272b2 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pex.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_m.pex.spice
-* Created: Fri Aug 28 11:01:28 2020
+* Created: Wed Sep 2 10:13:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pxi.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pxi.spice
index 0a67530..8019efe 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pxi.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_m.pxi.spice
-* Created: Fri Aug 28 11:01:28 2020
+* Created: Wed Sep 2 10:13:29 2020
*
x_PM_SKY130_FD_SC_LP__O2111AI_M%D1 N_D1_c_72_n N_D1_c_73_n N_D1_c_74_n
+ N_D1_M1002_g N_D1_c_75_n N_D1_M1003_g N_D1_c_76_n N_D1_c_81_n D1 D1 D1 D1
diff --git a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.spice b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.spice
index 04f4bfd..407c3e3 100644
--- a/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.spice
+++ b/cells/o2111ai/sky130_fd_sc_lp__o2111ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2111ai_m.spice
-* Created: Fri Aug 28 11:01:28 2020
+* Created: Wed Sep 2 10:13:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_0.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_0.lvs.report
new file mode 100644
index 0000000..7e47b50
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_0.sp ('sky130_fd_sc_lp__o211a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_0.spice ('sky130_fd_sc_lp__o211a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_0 sky130_fd_sc_lp__o211a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_0.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_0.pex.spice
index 0b5023b..5645988 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_0.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_0.pex.spice
-* Created: Fri Aug 28 11:01:37 2020
+* Created: Wed Sep 2 10:13:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_0.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_0.pxi.spice
index c5f5830..c3fd211 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_0.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_0.pxi.spice
-* Created: Fri Aug 28 11:01:37 2020
+* Created: Wed Sep 2 10:13:37 2020
*
x_PM_SKY130_FD_SC_LP__O211A_0%A_80_21# N_A_80_21#_M1008_d N_A_80_21#_M1000_d
+ N_A_80_21#_M1006_d N_A_80_21#_M1003_g N_A_80_21#_c_81_n N_A_80_21#_c_82_n
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_0.spice b/cells/o211a/sky130_fd_sc_lp__o211a_0.spice
index 9e0e993..dd8f661 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_0.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_0.spice
-* Created: Fri Aug 28 11:01:37 2020
+* Created: Wed Sep 2 10:13:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_1.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_1.lvs.report
new file mode 100644
index 0000000..c15aee03c
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_1.sp ('sky130_fd_sc_lp__o211a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_1.spice ('sky130_fd_sc_lp__o211a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_1 sky130_fd_sc_lp__o211a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_1.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_1.pex.spice
index d683069..939fb8a 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_1.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_1.pex.spice
-* Created: Fri Aug 28 11:01:49 2020
+* Created: Wed Sep 2 10:13:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_1.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_1.pxi.spice
index 00bfa57..c7c8d51 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_1.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_1.pxi.spice
-* Created: Fri Aug 28 11:01:49 2020
+* Created: Wed Sep 2 10:13:45 2020
*
x_PM_SKY130_FD_SC_LP__O211A_1%A_80_237# N_A_80_237#_M1009_d N_A_80_237#_M1001_d
+ N_A_80_237#_M1006_d N_A_80_237#_c_59_n N_A_80_237#_M1003_g N_A_80_237#_M1007_g
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_1.spice b/cells/o211a/sky130_fd_sc_lp__o211a_1.spice
index cf8c54f..aeeb6b3 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_1.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_1.spice
-* Created: Fri Aug 28 11:01:49 2020
+* Created: Wed Sep 2 10:13:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_2.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_2.lvs.report
new file mode 100644
index 0000000..03a27c5
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_2.sp ('sky130_fd_sc_lp__o211a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_2.spice ('sky130_fd_sc_lp__o211a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_2 sky130_fd_sc_lp__o211a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_2.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_2.pex.spice
index 5ac7770..93196eb 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_2.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_2.pex.spice
-* Created: Fri Aug 28 11:02:02 2020
+* Created: Wed Sep 2 10:13:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_2.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_2.pxi.spice
index 025c0c4..f6b1b10 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_2.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_2.pxi.spice
-* Created: Fri Aug 28 11:02:02 2020
+* Created: Wed Sep 2 10:13:52 2020
*
x_PM_SKY130_FD_SC_LP__O211A_2%C1 N_C1_M1006_g N_C1_c_70_n N_C1_M1010_g C1
+ N_C1_c_69_n PM_SKY130_FD_SC_LP__O211A_2%C1
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_2.spice b/cells/o211a/sky130_fd_sc_lp__o211a_2.spice
index d59a9b8..5768d45 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_2.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_2.spice
-* Created: Fri Aug 28 11:02:02 2020
+* Created: Wed Sep 2 10:13:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_4.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_4.lvs.report
new file mode 100644
index 0000000..a9d6377
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_4.sp ('sky130_fd_sc_lp__o211a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_4.spice ('sky130_fd_sc_lp__o211a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:13:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_4 sky130_fd_sc_lp__o211a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 C1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_4.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_4.pex.spice
index df06b10..ac38a6f 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_4.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_4.pex.spice
-* Created: Fri Aug 28 11:02:10 2020
+* Created: Wed Sep 2 10:14:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_4.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_4.pxi.spice
index bf46eda..a86af22 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_4.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_4.pxi.spice
-* Created: Fri Aug 28 11:02:10 2020
+* Created: Wed Sep 2 10:14:00 2020
*
x_PM_SKY130_FD_SC_LP__O211A_4%A_80_21# N_A_80_21#_M1016_d N_A_80_21#_M1005_s
+ N_A_80_21#_M1022_s N_A_80_21#_M1007_s N_A_80_21#_M1011_g N_A_80_21#_M1002_g
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_4.spice b/cells/o211a/sky130_fd_sc_lp__o211a_4.spice
index b5d3806..fcaede6 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_4.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_4.spice
-* Created: Fri Aug 28 11:02:10 2020
+* Created: Wed Sep 2 10:14:00 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_lp.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_lp.lvs.report
new file mode 100644
index 0000000..9dacca0
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_lp.sp ('sky130_fd_sc_lp__o211a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_lp.spice ('sky130_fd_sc_lp__o211a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_lp sky130_fd_sc_lp__o211a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_lp.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_lp.pex.spice
index bc3fece..80e804c 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_lp.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_lp.pex.spice
-* Created: Fri Aug 28 11:02:18 2020
+* Created: Wed Sep 2 10:14:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_lp.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_lp.pxi.spice
index 1c90e44..f41de3c 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_lp.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_lp.pxi.spice
-* Created: Fri Aug 28 11:02:18 2020
+* Created: Wed Sep 2 10:14:07 2020
*
x_PM_SKY130_FD_SC_LP__O211A_LP%A1 N_A1_M1010_g N_A1_c_68_n N_A1_M1009_g
+ N_A1_c_69_n A1 A1 N_A1_c_66_n N_A1_c_67_n PM_SKY130_FD_SC_LP__O211A_LP%A1
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_lp.spice b/cells/o211a/sky130_fd_sc_lp__o211a_lp.spice
index dbf7b26..230e8dc 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_lp.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_lp.spice
-* Created: Fri Aug 28 11:02:18 2020
+* Created: Wed Sep 2 10:14:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_m.lvs.report b/cells/o211a/sky130_fd_sc_lp__o211a_m.lvs.report
new file mode 100644
index 0000000..242a47a
--- /dev/null
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211a_m.sp ('sky130_fd_sc_lp__o211a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211a/sky130_fd_sc_lp__o211a_m.spice ('sky130_fd_sc_lp__o211a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211a_m sky130_fd_sc_lp__o211a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o211a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_m.pex.spice b/cells/o211a/sky130_fd_sc_lp__o211a_m.pex.spice
index fa3fc9a..3718402 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_m.pex.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_m.pex.spice
-* Created: Fri Aug 28 11:02:27 2020
+* Created: Wed Sep 2 10:14:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_m.pxi.spice b/cells/o211a/sky130_fd_sc_lp__o211a_m.pxi.spice
index 00ebe1e..d9fbf9d 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_m.pxi.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_m.pxi.spice
-* Created: Fri Aug 28 11:02:27 2020
+* Created: Wed Sep 2 10:14:14 2020
*
x_PM_SKY130_FD_SC_LP__O211A_M%A_80_60# N_A_80_60#_M1006_d N_A_80_60#_M1009_d
+ N_A_80_60#_M1001_d N_A_80_60#_M1002_g N_A_80_60#_M1003_g N_A_80_60#_c_63_n
diff --git a/cells/o211a/sky130_fd_sc_lp__o211a_m.spice b/cells/o211a/sky130_fd_sc_lp__o211a_m.spice
index f4d2ab1..3dc9b8d 100644
--- a/cells/o211a/sky130_fd_sc_lp__o211a_m.spice
+++ b/cells/o211a/sky130_fd_sc_lp__o211a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211a_m.spice
-* Created: Fri Aug 28 11:02:27 2020
+* Created: Wed Sep 2 10:14:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.lvs.report
new file mode 100644
index 0000000..8316330
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_0.sp ('sky130_fd_sc_lp__o211ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_0.spice ('sky130_fd_sc_lp__o211ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_0 sky130_fd_sc_lp__o211ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pex.spice
index fd00883..9d66af2 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_0.pex.spice
-* Created: Fri Aug 28 11:02:36 2020
+* Created: Wed Sep 2 10:14:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pxi.spice
index 4b36b0a..c691ff7 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_0.pxi.spice
-* Created: Fri Aug 28 11:02:36 2020
+* Created: Wed Sep 2 10:14:22 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_0%A1 N_A1_c_58_n N_A1_M1004_g N_A1_M1002_g
+ N_A1_c_60_n N_A1_c_61_n A1 A1 N_A1_c_62_n PM_SKY130_FD_SC_LP__O211AI_0%A1
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.spice
index f9c6205..ed94958 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_0.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_0.spice
-* Created: Fri Aug 28 11:02:36 2020
+* Created: Wed Sep 2 10:14:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.lvs.report
new file mode 100644
index 0000000..e8bfdd1
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_1.sp ('sky130_fd_sc_lp__o211ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_1.spice ('sky130_fd_sc_lp__o211ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_1 sky130_fd_sc_lp__o211ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pex.spice
index 9414adb..f517601 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_1.pex.spice
-* Created: Fri Aug 28 11:02:44 2020
+* Created: Wed Sep 2 10:14:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pxi.spice
index 300b116..6f0d28a 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_1.pxi.spice
-* Created: Fri Aug 28 11:02:44 2020
+* Created: Wed Sep 2 10:14:29 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_1%A1 N_A1_M1001_g N_A1_M1007_g A1 A1 N_A1_c_50_n
+ PM_SKY130_FD_SC_LP__O211AI_1%A1
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.spice
index cd90878..2e4cf81 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_1.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_1.spice
-* Created: Fri Aug 28 11:02:44 2020
+* Created: Wed Sep 2 10:14:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.lvs.report
new file mode 100644
index 0000000..d72dc3e
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_2.sp ('sky130_fd_sc_lp__o211ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_2.spice ('sky130_fd_sc_lp__o211ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_2 sky130_fd_sc_lp__o211ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pex.spice
index c6dc9ba..1a81db8 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_2.pex.spice
-* Created: Fri Aug 28 11:02:56 2020
+* Created: Wed Sep 2 10:14:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pxi.spice
index b239102..92308f7 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_2.pxi.spice
-* Created: Fri Aug 28 11:02:56 2020
+* Created: Wed Sep 2 10:14:36 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_2%C1 N_C1_c_82_n N_C1_M1009_g N_C1_M1008_g
+ N_C1_c_84_n N_C1_M1010_g N_C1_M1015_g C1 C1 N_C1_c_87_n
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.spice
index 5ef034d..5163e93 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_2.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_2.spice
-* Created: Fri Aug 28 11:02:56 2020
+* Created: Wed Sep 2 10:14:36 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.lvs.report
new file mode 100644
index 0000000..4df0e5a
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_4.sp ('sky130_fd_sc_lp__o211ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_4.spice ('sky130_fd_sc_lp__o211ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_4 sky130_fd_sc_lp__o211ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pex.spice
index 0d1e987..dd5322f 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_4.pex.spice
-* Created: Fri Aug 28 11:03:09 2020
+* Created: Wed Sep 2 10:14:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pxi.spice
index cdf3033..20db75c 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_4.pxi.spice
-* Created: Fri Aug 28 11:03:09 2020
+* Created: Wed Sep 2 10:14:44 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_4%A1 N_A1_M1010_g N_A1_M1004_g N_A1_M1020_g
+ N_A1_M1005_g N_A1_M1027_g N_A1_M1013_g N_A1_M1031_g N_A1_M1028_g N_A1_c_122_n
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.spice
index c0fcf3f..b9d7502 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_4.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_4.spice
-* Created: Fri Aug 28 11:03:09 2020
+* Created: Wed Sep 2 10:14:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.lvs.report
new file mode 100644
index 0000000..3a23d34
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_lp.sp ('sky130_fd_sc_lp__o211ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.spice ('sky130_fd_sc_lp__o211ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_lp sky130_fd_sc_lp__o211ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pex.spice
index 9ac4431..a610040 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_lp.pex.spice
-* Created: Fri Aug 28 11:03:17 2020
+* Created: Wed Sep 2 10:14:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pxi.spice
index f058744..481b543 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_lp.pxi.spice
-* Created: Fri Aug 28 11:03:17 2020
+* Created: Wed Sep 2 10:14:51 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_LP%A1 N_A1_M1007_g N_A1_M1004_g N_A1_c_61_n
+ N_A1_c_66_n A1 A1 N_A1_c_63_n PM_SKY130_FD_SC_LP__O211AI_LP%A1
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.spice
index 756e0df..81ed83f 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_lp.spice
-* Created: Fri Aug 28 11:03:17 2020
+* Created: Wed Sep 2 10:14:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.lvs.report b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.lvs.report
new file mode 100644
index 0000000..cd16b41
--- /dev/null
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o211ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o211ai_m.sp ('sky130_fd_sc_lp__o211ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o211ai/sky130_fd_sc_lp__o211ai_m.spice ('sky130_fd_sc_lp__o211ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:14:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o211ai_m sky130_fd_sc_lp__o211ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o211ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o211ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pex.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pex.spice
index de8fb66..abd4ad4 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pex.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_m.pex.spice
-* Created: Fri Aug 28 11:03:25 2020
+* Created: Wed Sep 2 10:14:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pxi.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pxi.spice
index 5013286..61f7847 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pxi.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_m.pxi.spice
-* Created: Fri Aug 28 11:03:25 2020
+* Created: Wed Sep 2 10:14:58 2020
*
x_PM_SKY130_FD_SC_LP__O211AI_M%A1 N_A1_M1007_g N_A1_M1000_g N_A1_c_58_n
+ N_A1_c_62_n A1 A1 A1 A1 N_A1_c_60_n PM_SKY130_FD_SC_LP__O211AI_M%A1
diff --git a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.spice b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.spice
index d13db63..c04d063 100644
--- a/cells/o211ai/sky130_fd_sc_lp__o211ai_m.spice
+++ b/cells/o211ai/sky130_fd_sc_lp__o211ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o211ai_m.spice
-* Created: Fri Aug 28 11:03:25 2020
+* Created: Wed Sep 2 10:14:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_0.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_0.lvs.report
new file mode 100644
index 0000000..1aff8d2
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_0.sp ('sky130_fd_sc_lp__o21a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_0.spice ('sky130_fd_sc_lp__o21a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_0 sky130_fd_sc_lp__o21a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_0.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_0.pex.spice
index b0dce96..00de23a 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_0.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_0.pex.spice
-* Created: Fri Aug 28 11:03:33 2020
+* Created: Wed Sep 2 10:15:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_0.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_0.pxi.spice
index 97f71c9..b6a12a8 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_0.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_0.pxi.spice
-* Created: Fri Aug 28 11:03:33 2020
+* Created: Wed Sep 2 10:15:06 2020
*
x_PM_SKY130_FD_SC_LP__O21A_0%A_80_23# N_A_80_23#_M1002_s N_A_80_23#_M1006_d
+ N_A_80_23#_M1004_g N_A_80_23#_c_65_n N_A_80_23#_M1003_g N_A_80_23#_c_67_n
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_0.spice b/cells/o21a/sky130_fd_sc_lp__o21a_0.spice
index 5204f42..dbee81c 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_0.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_0.spice
-* Created: Fri Aug 28 11:03:33 2020
+* Created: Wed Sep 2 10:15:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_1.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_1.lvs.report
new file mode 100644
index 0000000..ab143c4
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_1.sp ('sky130_fd_sc_lp__o21a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_1.spice ('sky130_fd_sc_lp__o21a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_1 sky130_fd_sc_lp__o21a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_1.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_1.pex.spice
index 0e46eaa..03578ac 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_1.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_1.pex.spice
-* Created: Fri Aug 28 11:03:42 2020
+* Created: Wed Sep 2 10:15:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_1.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_1.pxi.spice
index edc31f5..d18df06 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_1.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_1.pxi.spice
-* Created: Fri Aug 28 11:03:42 2020
+* Created: Wed Sep 2 10:15:13 2020
*
x_PM_SKY130_FD_SC_LP__O21A_1%A_80_21# N_A_80_21#_M1005_s N_A_80_21#_M1007_d
+ N_A_80_21#_c_50_n N_A_80_21#_M1003_g N_A_80_21#_M1002_g N_A_80_21#_c_52_n
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_1.spice b/cells/o21a/sky130_fd_sc_lp__o21a_1.spice
index f300883..3953491 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_1.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_1.spice
-* Created: Fri Aug 28 11:03:42 2020
+* Created: Wed Sep 2 10:15:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_2.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_2.lvs.report
new file mode 100644
index 0000000..531ddbf
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_2.sp ('sky130_fd_sc_lp__o21a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_2.spice ('sky130_fd_sc_lp__o21a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_2 sky130_fd_sc_lp__o21a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_2.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_2.pex.spice
index 0d84903..a60e858 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_2.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_2.pex.spice
-* Created: Fri Aug 28 11:03:49 2020
+* Created: Wed Sep 2 10:15:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_2.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_2.pxi.spice
index 93a4b78..a51380b 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_2.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_2.pxi.spice
-* Created: Fri Aug 28 11:03:49 2020
+* Created: Wed Sep 2 10:15:20 2020
*
x_PM_SKY130_FD_SC_LP__O21A_2%A_86_21# N_A_86_21#_M1000_s N_A_86_21#_M1001_d
+ N_A_86_21#_c_59_n N_A_86_21#_M1004_g N_A_86_21#_M1003_g N_A_86_21#_c_61_n
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_2.spice b/cells/o21a/sky130_fd_sc_lp__o21a_2.spice
index 79b73f7..6aab1d3 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_2.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_2.spice
-* Created: Fri Aug 28 11:03:49 2020
+* Created: Wed Sep 2 10:15:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_4.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_4.lvs.report
new file mode 100644
index 0000000..f0ee092
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_4.sp ('sky130_fd_sc_lp__o21a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_4.spice ('sky130_fd_sc_lp__o21a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_4 sky130_fd_sc_lp__o21a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_4.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_4.pex.spice
index 2247861..c94cc6e 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_4.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_4.pex.spice
-* Created: Fri Aug 28 11:04:02 2020
+* Created: Wed Sep 2 10:15:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_4.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_4.pxi.spice
index 98d120e..066a39a 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_4.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_4.pxi.spice
-* Created: Fri Aug 28 11:04:02 2020
+* Created: Wed Sep 2 10:15:27 2020
*
x_PM_SKY130_FD_SC_LP__O21A_4%A_90_23# N_A_90_23#_M1007_d N_A_90_23#_M1008_s
+ N_A_90_23#_M1006_s N_A_90_23#_M1001_g N_A_90_23#_M1002_g N_A_90_23#_M1003_g
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_4.spice b/cells/o21a/sky130_fd_sc_lp__o21a_4.spice
index 846febf..08d6a8e 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_4.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_4.spice
-* Created: Fri Aug 28 11:04:02 2020
+* Created: Wed Sep 2 10:15:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_lp.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_lp.lvs.report
new file mode 100644
index 0000000..36eda17
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_lp.sp ('sky130_fd_sc_lp__o21a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_lp.spice ('sky130_fd_sc_lp__o21a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_lp sky130_fd_sc_lp__o21a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_lp.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_lp.pex.spice
index 10fd846..7bdc60a 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_lp.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_lp.pex.spice
-* Created: Fri Aug 28 11:04:14 2020
+* Created: Wed Sep 2 10:15:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_lp.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_lp.pxi.spice
index a0cf72f..ea8edd0 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_lp.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_lp.pxi.spice
-* Created: Fri Aug 28 11:04:14 2020
+* Created: Wed Sep 2 10:15:35 2020
*
x_PM_SKY130_FD_SC_LP__O21A_LP%A1 N_A1_c_61_n N_A1_M1004_g N_A1_c_66_n
+ N_A1_M1000_g A1 A1 N_A1_c_64_n PM_SKY130_FD_SC_LP__O21A_LP%A1
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_lp.spice b/cells/o21a/sky130_fd_sc_lp__o21a_lp.spice
index af79d64..38573ed 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_lp.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_lp.spice
-* Created: Fri Aug 28 11:04:14 2020
+* Created: Wed Sep 2 10:15:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_m.lvs.report b/cells/o21a/sky130_fd_sc_lp__o21a_m.lvs.report
new file mode 100644
index 0000000..0d646c8
--- /dev/null
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21a_m.sp ('sky130_fd_sc_lp__o21a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21a/sky130_fd_sc_lp__o21a_m.spice ('sky130_fd_sc_lp__o21a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21a_m sky130_fd_sc_lp__o21a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o21a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_m.pex.spice b/cells/o21a/sky130_fd_sc_lp__o21a_m.pex.spice
index d05bb8e..a89e214 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_m.pex.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_m.pex.spice
-* Created: Fri Aug 28 11:04:22 2020
+* Created: Wed Sep 2 10:15:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_m.pxi.spice b/cells/o21a/sky130_fd_sc_lp__o21a_m.pxi.spice
index a97fb81..6deb6dd 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_m.pxi.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_m.pxi.spice
-* Created: Fri Aug 28 11:04:22 2020
+* Created: Wed Sep 2 10:15:43 2020
*
x_PM_SKY130_FD_SC_LP__O21A_M%A_80_23# N_A_80_23#_M1006_s N_A_80_23#_M1005_d
+ N_A_80_23#_M1002_g N_A_80_23#_c_67_n N_A_80_23#_c_68_n N_A_80_23#_M1000_g
diff --git a/cells/o21a/sky130_fd_sc_lp__o21a_m.spice b/cells/o21a/sky130_fd_sc_lp__o21a_m.spice
index 986e7f0..938cb53 100644
--- a/cells/o21a/sky130_fd_sc_lp__o21a_m.spice
+++ b/cells/o21a/sky130_fd_sc_lp__o21a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21a_m.spice
-* Created: Fri Aug 28 11:04:22 2020
+* Created: Wed Sep 2 10:15:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.lvs.report
new file mode 100644
index 0000000..4d81021
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_0.sp ('sky130_fd_sc_lp__o21ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_0.spice ('sky130_fd_sc_lp__o21ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_0 sky130_fd_sc_lp__o21ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pex.spice
index 29115b9..b64fcc1 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_0.pex.spice
-* Created: Fri Aug 28 11:04:30 2020
+* Created: Wed Sep 2 10:15:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pxi.spice
index ba86ea9..eee1dcb 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_0.pxi.spice
-* Created: Fri Aug 28 11:04:30 2020
+* Created: Wed Sep 2 10:15:50 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_0%A1 N_A1_c_51_n N_A1_c_58_n N_A1_c_59_n
+ N_A1_M1002_g N_A1_c_60_n N_A1_M1003_g N_A1_c_53_n N_A1_c_54_n A1 A1 A1
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.spice
index f45f65f..c0308d4 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_0.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_0.spice
-* Created: Fri Aug 28 11:04:30 2020
+* Created: Wed Sep 2 10:15:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.lvs.report
new file mode 100644
index 0000000..a935dae
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_1.sp ('sky130_fd_sc_lp__o21ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_1.spice ('sky130_fd_sc_lp__o21ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:15:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_1 sky130_fd_sc_lp__o21ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pex.spice
index 9860d1b..ff1bb44 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_1.pex.spice
-* Created: Fri Aug 28 11:04:39 2020
+* Created: Wed Sep 2 10:15:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pxi.spice
index caf1010..08a2f90 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_1.pxi.spice
-* Created: Fri Aug 28 11:04:39 2020
+* Created: Wed Sep 2 10:15:58 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_1%A1 N_A1_M1003_g N_A1_M1002_g A1 A1 N_A1_c_41_n
+ PM_SKY130_FD_SC_LP__O21AI_1%A1
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.spice
index ffb1985..64bab11 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_1.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_1.spice
-* Created: Fri Aug 28 11:04:39 2020
+* Created: Wed Sep 2 10:15:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.lvs.report
new file mode 100644
index 0000000..3df34b6
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_2.sp ('sky130_fd_sc_lp__o21ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_2.spice ('sky130_fd_sc_lp__o21ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_2 sky130_fd_sc_lp__o21ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pex.spice
index a4a145a..5c879b7 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_2.pex.spice
-* Created: Fri Aug 28 11:04:48 2020
+* Created: Wed Sep 2 10:16:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pxi.spice
index df4e740..f267bac 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_2.pxi.spice
-* Created: Fri Aug 28 11:04:48 2020
+* Created: Wed Sep 2 10:16:06 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_2%A1 N_A1_M1005_g N_A1_M1003_g N_A1_M1007_g
+ N_A1_M1010_g N_A1_c_61_n N_A1_c_69_n N_A1_c_62_n A1 A1 N_A1_c_64_n N_A1_c_65_n
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.spice
index 9129c6f..9f55604 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_2.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_2.spice
-* Created: Fri Aug 28 11:04:48 2020
+* Created: Wed Sep 2 10:16:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.lvs.report
new file mode 100644
index 0000000..fc45b86
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_4.sp ('sky130_fd_sc_lp__o21ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_4.spice ('sky130_fd_sc_lp__o21ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_4 sky130_fd_sc_lp__o21ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pex.spice
index faa5dfa..d93b140 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_4.pex.spice
-* Created: Fri Aug 28 11:04:56 2020
+* Created: Wed Sep 2 10:16:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pxi.spice
index db602c7..551efb0 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_4.pxi.spice
-* Created: Fri Aug 28 11:04:56 2020
+* Created: Wed Sep 2 10:16:13 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_4%A1 N_A1_c_87_n N_A1_M1011_g N_A1_M1006_g
+ N_A1_c_89_n N_A1_M1015_g N_A1_M1012_g N_A1_c_91_n N_A1_M1019_g N_A1_M1013_g
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.spice
index 77b47c5..d90a9c3 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_4.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_4.spice
-* Created: Fri Aug 28 11:04:56 2020
+* Created: Wed Sep 2 10:16:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.lvs.report
new file mode 100644
index 0000000..e3df30f
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_lp.sp ('sky130_fd_sc_lp__o21ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.spice ('sky130_fd_sc_lp__o21ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_lp sky130_fd_sc_lp__o21ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pex.spice
index dcc8288..bf3fd9c 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_lp.pex.spice
-* Created: Fri Aug 28 11:05:08 2020
+* Created: Wed Sep 2 10:16:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pxi.spice
index f63a62c..e174c7a 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_lp.pxi.spice
-* Created: Fri Aug 28 11:05:08 2020
+* Created: Wed Sep 2 10:16:20 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_LP%A1 N_A1_M1000_g N_A1_M1001_g N_A1_c_47_n
+ N_A1_c_48_n A1 A1 N_A1_c_50_n PM_SKY130_FD_SC_LP__O21AI_LP%A1
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.spice
index e793211..1847195 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_lp.spice
-* Created: Fri Aug 28 11:05:08 2020
+* Created: Wed Sep 2 10:16:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.lvs.report b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.lvs.report
new file mode 100644
index 0000000..7cc7bcb
--- /dev/null
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ai_m.sp ('sky130_fd_sc_lp__o21ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ai/sky130_fd_sc_lp__o21ai_m.spice ('sky130_fd_sc_lp__o21ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ai_m sky130_fd_sc_lp__o21ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pex.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pex.spice
index 1a25cbb..104a77a 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pex.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_m.pex.spice
-* Created: Fri Aug 28 11:05:20 2020
+* Created: Wed Sep 2 10:16:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pxi.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pxi.spice
index 1252727..cfd7433 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pxi.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_m.pxi.spice
-* Created: Fri Aug 28 11:05:20 2020
+* Created: Wed Sep 2 10:16:27 2020
*
x_PM_SKY130_FD_SC_LP__O21AI_M%A1 N_A1_c_44_n N_A1_M1004_g N_A1_M1005_g
+ N_A1_c_47_n A1 A1 A1 N_A1_c_48_n N_A1_c_49_n PM_SKY130_FD_SC_LP__O21AI_M%A1
diff --git a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.spice b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.spice
index c7a1141..d2ad1eb 100644
--- a/cells/o21ai/sky130_fd_sc_lp__o21ai_m.spice
+++ b/cells/o21ai/sky130_fd_sc_lp__o21ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ai_m.spice
-* Created: Fri Aug 28 11:05:20 2020
+* Created: Wed Sep 2 10:16:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.lvs.report
new file mode 100644
index 0000000..8807fa2
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_0.sp ('sky130_fd_sc_lp__o21ba_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_0.spice ('sky130_fd_sc_lp__o21ba_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_0 sky130_fd_sc_lp__o21ba_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pex.spice
index 138f8fc..aa9b5d7 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_0.pex.spice
-* Created: Fri Aug 28 11:05:28 2020
+* Created: Wed Sep 2 10:16:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pxi.spice
index a1c9994..1240002 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_0.pxi.spice
-* Created: Fri Aug 28 11:05:28 2020
+* Created: Wed Sep 2 10:16:35 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_0%A_80_225# N_A_80_225#_M1004_s N_A_80_225#_M1005_d
+ N_A_80_225#_c_77_n N_A_80_225#_M1001_g N_A_80_225#_M1002_g N_A_80_225#_c_79_n
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.spice
index 980d1eb..c712fde 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_0.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_0.spice
-* Created: Fri Aug 28 11:05:28 2020
+* Created: Wed Sep 2 10:16:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.lvs.report
new file mode 100644
index 0000000..52a7b48
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_1.sp ('sky130_fd_sc_lp__o21ba_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_1.spice ('sky130_fd_sc_lp__o21ba_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_1 sky130_fd_sc_lp__o21ba_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pex.spice
index 601dd92..dc4a1d2 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_1.pex.spice
-* Created: Fri Aug 28 11:05:36 2020
+* Created: Wed Sep 2 10:16:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pxi.spice
index d06e0ec..efda4d2 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_1.pxi.spice
-* Created: Fri Aug 28 11:05:36 2020
+* Created: Wed Sep 2 10:16:42 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_1%A_84_28# N_A_84_28#_M1002_s N_A_84_28#_M1001_d
+ N_A_84_28#_c_67_n N_A_84_28#_M1005_g N_A_84_28#_M1008_g N_A_84_28#_c_69_n
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.spice
index 9088825..823f93b 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_1.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_1.spice
-* Created: Fri Aug 28 11:05:36 2020
+* Created: Wed Sep 2 10:16:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.lvs.report
new file mode 100644
index 0000000..0db4593
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_2.sp ('sky130_fd_sc_lp__o21ba_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_2.spice ('sky130_fd_sc_lp__o21ba_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_2 sky130_fd_sc_lp__o21ba_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pex.spice
index dc12207..6363700 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_2.pex.spice
-* Created: Fri Aug 28 11:05:45 2020
+* Created: Wed Sep 2 10:16:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pxi.spice
index 0e790ed..c8546a9 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_2.pxi.spice
-* Created: Fri Aug 28 11:05:45 2020
+* Created: Wed Sep 2 10:16:50 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_2%B1_N N_B1_N_M1008_g N_B1_N_M1010_g B1_N B1_N
+ N_B1_N_c_71_n PM_SKY130_FD_SC_LP__O21BA_2%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.spice
index add39c9..4c7a0ca 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_2.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_2.spice
-* Created: Fri Aug 28 11:05:45 2020
+* Created: Wed Sep 2 10:16:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.lvs.report
new file mode 100644
index 0000000..66e3f6e
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_4.sp ('sky130_fd_sc_lp__o21ba_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_4.spice ('sky130_fd_sc_lp__o21ba_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:16:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_4 sky130_fd_sc_lp__o21ba_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 8.
+ 12 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pex.spice
index 474d4dd..02517b2 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_4.pex.spice
-* Created: Fri Aug 28 11:05:54 2020
+* Created: Wed Sep 2 10:16:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pxi.spice
index d267307..06b7068 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_4.pxi.spice
-* Created: Fri Aug 28 11:05:54 2020
+* Created: Wed Sep 2 10:16:57 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_4%B1_N N_B1_N_M1020_g N_B1_N_M1021_g B1_N B1_N
+ N_B1_N_c_108_n N_B1_N_c_109_n PM_SKY130_FD_SC_LP__O21BA_4%B1_N
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.spice
index 7c41522..aadeb16 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_4.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_4.spice
-* Created: Fri Aug 28 11:05:54 2020
+* Created: Wed Sep 2 10:16:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.lvs.report
new file mode 100644
index 0000000..fb7ef34
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_lp.sp ('sky130_fd_sc_lp__o21ba_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.spice ('sky130_fd_sc_lp__o21ba_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_lp sky130_fd_sc_lp__o21ba_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pex.spice
index 22de390..edbdb78 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_lp.pex.spice
-* Created: Fri Aug 28 11:06:02 2020
+* Created: Wed Sep 2 10:17:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pxi.spice
index 6ff055b..d516617 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_lp.pxi.spice
-* Created: Fri Aug 28 11:06:02 2020
+* Created: Wed Sep 2 10:17:04 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_LP%A1 N_A1_M1001_g N_A1_M1004_g A1 A1 N_A1_c_82_n
+ PM_SKY130_FD_SC_LP__O21BA_LP%A1
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.spice
index 5550acd..34117bd 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_lp.spice
-* Created: Fri Aug 28 11:06:02 2020
+* Created: Wed Sep 2 10:17:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.lvs.report b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.lvs.report
new file mode 100644
index 0000000..2cc47ea
--- /dev/null
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21ba_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21ba_m.sp ('sky130_fd_sc_lp__o21ba_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21ba/sky130_fd_sc_lp__o21ba_m.spice ('sky130_fd_sc_lp__o21ba_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21ba_m sky130_fd_sc_lp__o21ba_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21ba_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o21ba_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pex.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pex.spice
index 5151651..d2648e8 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pex.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_m.pex.spice
-* Created: Fri Aug 28 11:06:14 2020
+* Created: Wed Sep 2 10:17:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pxi.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pxi.spice
index 990ea00..9f17329 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pxi.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_m.pxi.spice
-* Created: Fri Aug 28 11:06:14 2020
+* Created: Wed Sep 2 10:17:11 2020
*
x_PM_SKY130_FD_SC_LP__O21BA_M%A_88_41# N_A_88_41#_M1007_s N_A_88_41#_M1009_d
+ N_A_88_41#_M1004_g N_A_88_41#_M1000_g N_A_88_41#_c_75_n N_A_88_41#_c_76_n
diff --git a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.spice b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.spice
index bbf8c2c..670c4a3 100644
--- a/cells/o21ba/sky130_fd_sc_lp__o21ba_m.spice
+++ b/cells/o21ba/sky130_fd_sc_lp__o21ba_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21ba_m.spice
-* Created: Fri Aug 28 11:06:14 2020
+* Created: Wed Sep 2 10:17:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.lvs.report
new file mode 100644
index 0000000..9ada3ca
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_0.sp ('sky130_fd_sc_lp__o21bai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_0.spice ('sky130_fd_sc_lp__o21bai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_0 sky130_fd_sc_lp__o21bai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pex.spice
index 41f8be7..bcece8f 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_0.pex.spice
-* Created: Fri Aug 28 11:06:27 2020
+* Created: Wed Sep 2 10:17:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pxi.spice
index 43595cc..541bd81 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_0.pxi.spice
-* Created: Fri Aug 28 11:06:27 2020
+* Created: Wed Sep 2 10:17:20 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_0%B1_N N_B1_N_c_72_n N_B1_N_c_79_n N_B1_N_c_80_n
+ N_B1_N_c_73_n N_B1_N_M1007_g N_B1_N_M1002_g N_B1_N_c_74_n N_B1_N_c_75_n B1_N
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.spice
index cf960b5..3949439 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_0.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_0.spice
-* Created: Fri Aug 28 11:06:27 2020
+* Created: Wed Sep 2 10:17:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.lvs.report
new file mode 100644
index 0000000..cb9e7eb
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_1.sp ('sky130_fd_sc_lp__o21bai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_1.spice ('sky130_fd_sc_lp__o21bai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_1 sky130_fd_sc_lp__o21bai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pex.spice
index 4b11bcd..15a35d5 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_1.pex.spice
-* Created: Fri Aug 28 11:06:35 2020
+* Created: Wed Sep 2 10:17:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pxi.spice
index a1c81b7..6e22dc9 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_1.pxi.spice
-* Created: Fri Aug 28 11:06:35 2020
+* Created: Wed Sep 2 10:17:28 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_1%B1_N N_B1_N_M1005_g N_B1_N_c_62_n N_B1_N_c_63_n
+ N_B1_N_c_64_n N_B1_N_M1000_g N_B1_N_c_59_n B1_N B1_N N_B1_N_c_61_n
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.spice
index 1f2957e..b26a7a1 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_1.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_1.spice
-* Created: Fri Aug 28 11:06:35 2020
+* Created: Wed Sep 2 10:17:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.lvs.report
new file mode 100644
index 0000000..db49757
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_2.sp ('sky130_fd_sc_lp__o21bai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_2.spice ('sky130_fd_sc_lp__o21bai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_2 sky130_fd_sc_lp__o21bai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pex.spice
index 75ed99d..bcd1f82 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_2.pex.spice
-* Created: Fri Aug 28 11:06:43 2020
+* Created: Wed Sep 2 10:17:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pxi.spice
index b8cca3e..3da3149 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_2.pxi.spice
-* Created: Fri Aug 28 11:06:43 2020
+* Created: Wed Sep 2 10:17:35 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_2%B1_N N_B1_N_c_79_n N_B1_N_M1013_g N_B1_N_c_80_n
+ N_B1_N_c_81_n N_B1_N_M1010_g B1_N B1_N N_B1_N_c_84_n N_B1_N_c_85_n
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.spice
index 0b9e309..6341e7e 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_2.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_2.spice
-* Created: Fri Aug 28 11:06:43 2020
+* Created: Wed Sep 2 10:17:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.lvs.report
new file mode 100644
index 0000000..95b66ca
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_4.sp ('sky130_fd_sc_lp__o21bai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_4.spice ('sky130_fd_sc_lp__o21bai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_4 sky130_fd_sc_lp__o21bai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 13 13 MN (4 pins)
+ 13 13 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 27 26
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 6.
+ 18 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pex.spice
index 127e475..38cd48c 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_4.pex.spice
-* Created: Fri Aug 28 11:06:51 2020
+* Created: Wed Sep 2 10:17:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pxi.spice
index 34b1811..6ba3ab4 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_4.pxi.spice
-* Created: Fri Aug 28 11:06:51 2020
+* Created: Wed Sep 2 10:17:43 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_4%B1_N N_B1_N_M1009_g N_B1_N_c_108_n N_B1_N_M1024_g
+ B1_N N_B1_N_c_109_n PM_SKY130_FD_SC_LP__O21BAI_4%B1_N
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.spice
index 3421b86..ee39436 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_4.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_4.spice
-* Created: Fri Aug 28 11:06:51 2020
+* Created: Wed Sep 2 10:17:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.lvs.report
new file mode 100644
index 0000000..8f9a20c
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_lp.sp ('sky130_fd_sc_lp__o21bai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.spice ('sky130_fd_sc_lp__o21bai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_lp sky130_fd_sc_lp__o21bai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pex.spice
index 0c72337..fa8af6c 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_lp.pex.spice
-* Created: Fri Aug 28 11:07:00 2020
+* Created: Wed Sep 2 10:17:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pxi.spice
index 4a72efd..4507ce3 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_lp.pxi.spice
-* Created: Fri Aug 28 11:07:00 2020
+* Created: Wed Sep 2 10:17:51 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_LP%A1 N_A1_c_61_n N_A1_M1003_g N_A1_M1002_g
+ N_A1_c_62_n N_A1_c_66_n A1 A1 N_A1_c_63_n N_A1_c_64_n
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.spice
index 6e9497e..d7cd057 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_lp.spice
-* Created: Fri Aug 28 11:07:00 2020
+* Created: Wed Sep 2 10:17:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.lvs.report b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.lvs.report
new file mode 100644
index 0000000..fb632e0
--- /dev/null
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o21bai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o21bai_m.sp ('sky130_fd_sc_lp__o21bai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o21bai/sky130_fd_sc_lp__o21bai_m.spice ('sky130_fd_sc_lp__o21bai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:17:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o21bai_m sky130_fd_sc_lp__o21bai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o21bai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o21bai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1_N A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pex.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pex.spice
index 2e366ab..c931c92 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pex.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_m.pex.spice
-* Created: Fri Aug 28 11:07:08 2020
+* Created: Wed Sep 2 10:17:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pxi.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pxi.spice
index f5d1704..f0a3664 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pxi.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_m.pxi.spice
-* Created: Fri Aug 28 11:07:08 2020
+* Created: Wed Sep 2 10:17:58 2020
*
x_PM_SKY130_FD_SC_LP__O21BAI_M%B1_N N_B1_N_M1002_g N_B1_N_M1005_g N_B1_N_c_64_n
+ N_B1_N_c_65_n N_B1_N_c_66_n B1_N B1_N N_B1_N_c_68_n
diff --git a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.spice b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.spice
index e541d02..1b0032e 100644
--- a/cells/o21bai/sky130_fd_sc_lp__o21bai_m.spice
+++ b/cells/o21bai/sky130_fd_sc_lp__o21bai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o21bai_m.spice
-* Created: Fri Aug 28 11:07:08 2020
+* Created: Wed Sep 2 10:17:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_0.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_0.lvs.report
new file mode 100644
index 0000000..1a393cb
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_0.sp ('sky130_fd_sc_lp__o221a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_0.spice ('sky130_fd_sc_lp__o221a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_0 sky130_fd_sc_lp__o221a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_0.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_0.pex.spice
index 2fed50f..5bed806 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_0.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_0.pex.spice
-* Created: Fri Aug 28 11:07:20 2020
+* Created: Wed Sep 2 10:18:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_0.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_0.pxi.spice
index 4a4c534..2f88c39 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_0.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_0.pxi.spice
-* Created: Fri Aug 28 11:07:20 2020
+* Created: Wed Sep 2 10:18:06 2020
*
x_PM_SKY130_FD_SC_LP__O221A_0%C1 N_C1_M1005_g N_C1_M1008_g N_C1_c_82_n
+ N_C1_c_87_n C1 C1 C1 N_C1_c_84_n PM_SKY130_FD_SC_LP__O221A_0%C1
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_0.spice b/cells/o221a/sky130_fd_sc_lp__o221a_0.spice
index 1a647b5..fd328a5 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_0.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_0.spice
-* Created: Fri Aug 28 11:07:20 2020
+* Created: Wed Sep 2 10:18:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_1.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_1.lvs.report
new file mode 100644
index 0000000..54d8841
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_1.sp ('sky130_fd_sc_lp__o221a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_1.spice ('sky130_fd_sc_lp__o221a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_1 sky130_fd_sc_lp__o221a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_1.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_1.pex.spice
index 5bbb0a9..a59fac1 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_1.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_1.pex.spice
-* Created: Fri Aug 28 11:07:32 2020
+* Created: Wed Sep 2 10:18:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_1.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_1.pxi.spice
index e52127a..4e2a077 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_1.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_1.pxi.spice
-* Created: Fri Aug 28 11:07:32 2020
+* Created: Wed Sep 2 10:18:13 2020
*
x_PM_SKY130_FD_SC_LP__O221A_1%C1 N_C1_M1002_g N_C1_M1003_g N_C1_c_69_n
+ N_C1_c_70_n C1 C1 C1 C1 N_C1_c_72_n C1 PM_SKY130_FD_SC_LP__O221A_1%C1
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_1.spice b/cells/o221a/sky130_fd_sc_lp__o221a_1.spice
index c0d9db7..53b1ac2 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_1.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_1.spice
-* Created: Fri Aug 28 11:07:32 2020
+* Created: Wed Sep 2 10:18:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_2.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_2.lvs.report
new file mode 100644
index 0000000..044bbef
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_2.sp ('sky130_fd_sc_lp__o221a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_2.spice ('sky130_fd_sc_lp__o221a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_2 sky130_fd_sc_lp__o221a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_2.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_2.pex.spice
index ae010c2..db216ae 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_2.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_2.pex.spice
-* Created: Fri Aug 28 11:07:41 2020
+* Created: Wed Sep 2 10:18:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_2.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_2.pxi.spice
index d582109..7682874 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_2.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_2.pxi.spice
-* Created: Fri Aug 28 11:07:41 2020
+* Created: Wed Sep 2 10:18:21 2020
*
x_PM_SKY130_FD_SC_LP__O221A_2%C1 N_C1_c_74_n N_C1_M1001_g N_C1_M1004_g C1 C1
+ N_C1_c_77_n PM_SKY130_FD_SC_LP__O221A_2%C1
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_2.spice b/cells/o221a/sky130_fd_sc_lp__o221a_2.spice
index 48da13a..861a0b0 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_2.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_2.spice
-* Created: Fri Aug 28 11:07:41 2020
+* Created: Wed Sep 2 10:18:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_4.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_4.lvs.report
new file mode 100644
index 0000000..1a8e913
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_4.sp ('sky130_fd_sc_lp__o221a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_4.spice ('sky130_fd_sc_lp__o221a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_4 sky130_fd_sc_lp__o221a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_4.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_4.pex.spice
index d585e92..83935c5 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_4.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_4.pex.spice
-* Created: Fri Aug 28 11:07:48 2020
+* Created: Wed Sep 2 10:18:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_4.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_4.pxi.spice
index f4d1a98..794b93c 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_4.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_4.pxi.spice
-* Created: Fri Aug 28 11:07:48 2020
+* Created: Wed Sep 2 10:18:29 2020
*
x_PM_SKY130_FD_SC_LP__O221A_4%C1 N_C1_c_119_n N_C1_M1005_g N_C1_M1006_g
+ N_C1_c_121_n N_C1_M1014_g N_C1_M1022_g C1 C1 N_C1_c_124_n
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_4.spice b/cells/o221a/sky130_fd_sc_lp__o221a_4.spice
index 37c0eb8..adf8a0a 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_4.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_4.spice
-* Created: Fri Aug 28 11:07:48 2020
+* Created: Wed Sep 2 10:18:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_lp.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_lp.lvs.report
new file mode 100644
index 0000000..76397f8
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_lp.sp ('sky130_fd_sc_lp__o221a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_lp.spice ('sky130_fd_sc_lp__o221a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_lp sky130_fd_sc_lp__o221a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B2 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_lp.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_lp.pex.spice
index a69804f..f2f078f 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_lp.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_lp.pex.spice
-* Created: Fri Aug 28 11:07:57 2020
+* Created: Wed Sep 2 10:18:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_lp.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_lp.pxi.spice
index 6925866..c49ee2f 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_lp.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_lp.pxi.spice
-* Created: Fri Aug 28 11:07:57 2020
+* Created: Wed Sep 2 10:18:37 2020
*
x_PM_SKY130_FD_SC_LP__O221A_LP%A_84_21# N_A_84_21#_M1012_d N_A_84_21#_M1001_d
+ N_A_84_21#_M1010_d N_A_84_21#_c_93_n N_A_84_21#_M1002_g N_A_84_21#_c_94_n
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_lp.spice b/cells/o221a/sky130_fd_sc_lp__o221a_lp.spice
index 59799b7..eb5fa4c 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_lp.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_lp.spice
-* Created: Fri Aug 28 11:07:57 2020
+* Created: Wed Sep 2 10:18:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_m.lvs.report b/cells/o221a/sky130_fd_sc_lp__o221a_m.lvs.report
new file mode 100644
index 0000000..6da7591
--- /dev/null
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221a_m.sp ('sky130_fd_sc_lp__o221a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221a/sky130_fd_sc_lp__o221a_m.spice ('sky130_fd_sc_lp__o221a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221a_m sky130_fd_sc_lp__o221a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o221a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_m.pex.spice b/cells/o221a/sky130_fd_sc_lp__o221a_m.pex.spice
index 23bfad5..ecaff71 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_m.pex.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_m.pex.spice
-* Created: Fri Aug 28 11:08:05 2020
+* Created: Wed Sep 2 10:18:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_m.pxi.spice b/cells/o221a/sky130_fd_sc_lp__o221a_m.pxi.spice
index d7cb17c..9f3b828 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_m.pxi.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_m.pxi.spice
-* Created: Fri Aug 28 11:08:05 2020
+* Created: Wed Sep 2 10:18:45 2020
*
x_PM_SKY130_FD_SC_LP__O221A_M%C1 N_C1_c_82_n N_C1_M1001_g N_C1_c_88_n
+ N_C1_M1010_g N_C1_c_84_n N_C1_c_89_n C1 C1 N_C1_c_86_n
diff --git a/cells/o221a/sky130_fd_sc_lp__o221a_m.spice b/cells/o221a/sky130_fd_sc_lp__o221a_m.spice
index 8327cd9..6625f56 100644
--- a/cells/o221a/sky130_fd_sc_lp__o221a_m.spice
+++ b/cells/o221a/sky130_fd_sc_lp__o221a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221a_m.spice
-* Created: Fri Aug 28 11:08:05 2020
+* Created: Wed Sep 2 10:18:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.lvs.report
new file mode 100644
index 0000000..41b2d7d
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_0.sp ('sky130_fd_sc_lp__o221ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_0.spice ('sky130_fd_sc_lp__o221ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:18:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_0 sky130_fd_sc_lp__o221ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pex.spice
index 608bd27..ab1c5b0 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_0.pex.spice
-* Created: Fri Aug 28 11:08:13 2020
+* Created: Wed Sep 2 10:18:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pxi.spice
index ada970f..ac7afea 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_0.pxi.spice
-* Created: Fri Aug 28 11:08:13 2020
+* Created: Wed Sep 2 10:18:55 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_0%C1 N_C1_M1002_g N_C1_M1001_g C1 N_C1_c_76_n
+ N_C1_c_77_n PM_SKY130_FD_SC_LP__O221AI_0%C1
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.spice
index 67f5b18..feea176 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_0.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_0.spice
-* Created: Fri Aug 28 11:08:13 2020
+* Created: Wed Sep 2 10:18:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.lvs.report
new file mode 100644
index 0000000..13125cc
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_1.sp ('sky130_fd_sc_lp__o221ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_1.spice ('sky130_fd_sc_lp__o221ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_1 sky130_fd_sc_lp__o221ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pex.spice
index ce7d506..cedd459 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_1.pex.spice
-* Created: Fri Aug 28 11:08:25 2020
+* Created: Wed Sep 2 10:19:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pxi.spice
index b7c3ac8..0e9f123 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_1.pxi.spice
-* Created: Fri Aug 28 11:08:25 2020
+* Created: Wed Sep 2 10:19:04 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_1%C1 N_C1_M1002_g N_C1_M1000_g C1 N_C1_c_61_n
+ N_C1_c_62_n PM_SKY130_FD_SC_LP__O221AI_1%C1
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.spice
index aad7af2..98f4494 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_1.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_1.spice
-* Created: Fri Aug 28 11:08:25 2020
+* Created: Wed Sep 2 10:19:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.lvs.report
new file mode 100644
index 0000000..6203d9e
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_2.sp ('sky130_fd_sc_lp__o221ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_2.spice ('sky130_fd_sc_lp__o221ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_2 sky130_fd_sc_lp__o221ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pex.spice
index 985ba03..851185b 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_2.pex.spice
-* Created: Fri Aug 28 11:08:37 2020
+* Created: Wed Sep 2 10:19:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pxi.spice
index 7a6d6a8..63488e3 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_2.pxi.spice
-* Created: Fri Aug 28 11:08:37 2020
+* Created: Wed Sep 2 10:19:11 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_2%C1 N_C1_c_90_n N_C1_M1002_g N_C1_M1004_g
+ N_C1_c_92_n N_C1_M1005_g N_C1_M1015_g C1 C1 N_C1_c_95_n
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.spice
index 8a74f12..6d26caa 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_2.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_2.spice
-* Created: Fri Aug 28 11:08:37 2020
+* Created: Wed Sep 2 10:19:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.lvs.report
new file mode 100644
index 0000000..549d299
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_4.sp ('sky130_fd_sc_lp__o221ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_4.spice ('sky130_fd_sc_lp__o221ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_4 sky130_fd_sc_lp__o221ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A1 A2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pex.spice
index 82548db..133a4f8 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_4.pex.spice
-* Created: Fri Aug 28 11:08:46 2020
+* Created: Wed Sep 2 10:19:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pxi.spice
index 2fc6986..e924764 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_4.pxi.spice
-* Created: Fri Aug 28 11:08:46 2020
+* Created: Wed Sep 2 10:19:18 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_4%C1 N_C1_M1005_g N_C1_M1018_g N_C1_M1001_g
+ N_C1_M1021_g N_C1_M1004_g N_C1_M1032_g N_C1_M1010_g N_C1_M1024_g C1 C1 C1 C1
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.spice
index 5508d5c..134bc95 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_4.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_4.spice
-* Created: Fri Aug 28 11:08:46 2020
+* Created: Wed Sep 2 10:19:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.lvs.report
new file mode 100644
index 0000000..27cb00c
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_lp.sp ('sky130_fd_sc_lp__o221ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.spice ('sky130_fd_sc_lp__o221ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_lp sky130_fd_sc_lp__o221ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 B2 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pex.spice
index 736c87b..13c95ad 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_lp.pex.spice
-* Created: Fri Aug 28 11:08:55 2020
+* Created: Wed Sep 2 10:19:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pxi.spice
index f25a6b4..6292c48 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_lp.pxi.spice
-* Created: Fri Aug 28 11:08:55 2020
+* Created: Wed Sep 2 10:19:26 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_LP%C1 N_C1_c_77_n N_C1_M1003_g N_C1_M1004_g C1
+ PM_SKY130_FD_SC_LP__O221AI_LP%C1
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.spice
index c5098e7..0b0304e 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_lp.spice
-* Created: Fri Aug 28 11:08:55 2020
+* Created: Wed Sep 2 10:19:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.lvs.report b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.lvs.report
new file mode 100644
index 0000000..8107e00
--- /dev/null
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o221ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o221ai_m.sp ('sky130_fd_sc_lp__o221ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o221ai/sky130_fd_sc_lp__o221ai_m.spice ('sky130_fd_sc_lp__o221ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o221ai_m sky130_fd_sc_lp__o221ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o221ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o221ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A2 A1 B2 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pex.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pex.spice
index 79c3d3a..54c1fa2 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pex.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_m.pex.spice
-* Created: Fri Aug 28 11:09:04 2020
+* Created: Wed Sep 2 10:19:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pxi.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pxi.spice
index 7d0eaeb..9b8aced 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pxi.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_m.pxi.spice
-* Created: Fri Aug 28 11:09:04 2020
+* Created: Wed Sep 2 10:19:33 2020
*
x_PM_SKY130_FD_SC_LP__O221AI_M%C1 N_C1_M1006_g N_C1_c_73_n N_C1_M1000_g
+ N_C1_c_74_n C1 N_C1_c_78_n N_C1_c_75_n PM_SKY130_FD_SC_LP__O221AI_M%C1
diff --git a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.spice b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.spice
index 075162c..60d8e15 100644
--- a/cells/o221ai/sky130_fd_sc_lp__o221ai_m.spice
+++ b/cells/o221ai/sky130_fd_sc_lp__o221ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o221ai_m.spice
-* Created: Fri Aug 28 11:09:04 2020
+* Created: Wed Sep 2 10:19:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_0.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_0.lvs.report
new file mode 100644
index 0000000..c727a1b
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_0.sp ('sky130_fd_sc_lp__o22a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_0.spice ('sky130_fd_sc_lp__o22a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_0 sky130_fd_sc_lp__o22a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B1 B2 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_0.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_0.pex.spice
index 2611346..52aa1c1 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_0.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_0.pex.spice
-* Created: Fri Aug 28 11:09:15 2020
+* Created: Wed Sep 2 10:19:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_0.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_0.pxi.spice
index 2c9898b..452274b 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_0.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_0.pxi.spice
-* Created: Fri Aug 28 11:09:15 2020
+* Created: Wed Sep 2 10:19:41 2020
*
x_PM_SKY130_FD_SC_LP__O22A_0%A_80_313# N_A_80_313#_M1003_d N_A_80_313#_M1001_d
+ N_A_80_313#_c_91_n N_A_80_313#_M1006_g N_A_80_313#_M1000_g N_A_80_313#_c_93_n
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_0.spice b/cells/o22a/sky130_fd_sc_lp__o22a_0.spice
index 711e1cc..c4ad366 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_0.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_0.spice
-* Created: Fri Aug 28 11:09:15 2020
+* Created: Wed Sep 2 10:19:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_1.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_1.lvs.report
new file mode 100644
index 0000000..ecdf43a
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_1.sp ('sky130_fd_sc_lp__o22a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_1.spice ('sky130_fd_sc_lp__o22a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_1 sky130_fd_sc_lp__o22a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_1.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_1.pex.spice
index 8431f65..e35c549 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_1.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_1.pex.spice
-* Created: Fri Aug 28 11:09:28 2020
+* Created: Wed Sep 2 10:19:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_1.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_1.pxi.spice
index d535f59..1243593 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_1.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_1.pxi.spice
-* Created: Fri Aug 28 11:09:28 2020
+* Created: Wed Sep 2 10:19:48 2020
*
x_PM_SKY130_FD_SC_LP__O22A_1%A_80_21# N_A_80_21#_M1000_d N_A_80_21#_M1009_d
+ N_A_80_21#_c_60_n N_A_80_21#_M1004_g N_A_80_21#_M1006_g N_A_80_21#_c_62_n
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_1.spice b/cells/o22a/sky130_fd_sc_lp__o22a_1.spice
index 442fbf9..afe527e 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_1.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_1.spice
-* Created: Fri Aug 28 11:09:28 2020
+* Created: Wed Sep 2 10:19:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_2.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_2.lvs.report
new file mode 100644
index 0000000..773ae36
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_2.sp ('sky130_fd_sc_lp__o22a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_2.spice ('sky130_fd_sc_lp__o22a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:19:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_2 sky130_fd_sc_lp__o22a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_2.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_2.pex.spice
index 983e7e8..098b949 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_2.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_2.pex.spice
-* Created: Fri Aug 28 11:09:43 2020
+* Created: Wed Sep 2 10:19:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_2.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_2.pxi.spice
index 40a9c79..848384a 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_2.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_2.pxi.spice
-* Created: Fri Aug 28 11:09:43 2020
+* Created: Wed Sep 2 10:19:56 2020
*
x_PM_SKY130_FD_SC_LP__O22A_2%A_80_23# N_A_80_23#_M1008_d N_A_80_23#_M1011_d
+ N_A_80_23#_M1005_g N_A_80_23#_M1000_g N_A_80_23#_M1007_g N_A_80_23#_M1003_g
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_2.spice b/cells/o22a/sky130_fd_sc_lp__o22a_2.spice
index c092578..9c417c8 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_2.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_2.spice
-* Created: Fri Aug 28 11:09:43 2020
+* Created: Wed Sep 2 10:19:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_4.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_4.lvs.report
new file mode 100644
index 0000000..a9857e1
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_4.sp ('sky130_fd_sc_lp__o22a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_4.spice ('sky130_fd_sc_lp__o22a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_4 sky130_fd_sc_lp__o22a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1 A2 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_4.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_4.pex.spice
index 220a81d..38bd465 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_4.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_4.pex.spice
-* Created: Fri Aug 28 11:09:53 2020
+* Created: Wed Sep 2 10:20:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_4.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_4.pxi.spice
index dbe142d..4cf197f 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_4.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_4.pxi.spice
-* Created: Fri Aug 28 11:09:53 2020
+* Created: Wed Sep 2 10:20:04 2020
*
x_PM_SKY130_FD_SC_LP__O22A_4%A_86_23# N_A_86_23#_M1010_d N_A_86_23#_M1021_d
+ N_A_86_23#_M1008_s N_A_86_23#_M1001_d N_A_86_23#_M1005_g N_A_86_23#_M1011_g
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_4.spice b/cells/o22a/sky130_fd_sc_lp__o22a_4.spice
index 01c8da9..83cadba 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_4.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_4.spice
-* Created: Fri Aug 28 11:09:53 2020
+* Created: Wed Sep 2 10:20:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_lp.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_lp.lvs.report
new file mode 100644
index 0000000..ea97ece
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_lp.sp ('sky130_fd_sc_lp__o22a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_lp.spice ('sky130_fd_sc_lp__o22a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_lp sky130_fd_sc_lp__o22a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_lp.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_lp.pex.spice
index 0ccd38a..76df9e1 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_lp.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_lp.pex.spice
-* Created: Fri Aug 28 11:10:02 2020
+* Created: Wed Sep 2 10:20:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_lp.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_lp.pxi.spice
index ce5354c..ff2d394 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_lp.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_lp.pxi.spice
-* Created: Fri Aug 28 11:10:02 2020
+* Created: Wed Sep 2 10:20:12 2020
*
x_PM_SKY130_FD_SC_LP__O22A_LP%A1 N_A1_c_66_n N_A1_M1008_g N_A1_M1007_g A1
+ N_A1_c_68_n PM_SKY130_FD_SC_LP__O22A_LP%A1
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_lp.spice b/cells/o22a/sky130_fd_sc_lp__o22a_lp.spice
index 41a61fa..67a071e 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_lp.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_lp.spice
-* Created: Fri Aug 28 11:10:02 2020
+* Created: Wed Sep 2 10:20:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_m.lvs.report b/cells/o22a/sky130_fd_sc_lp__o22a_m.lvs.report
new file mode 100644
index 0000000..68d0cd5
--- /dev/null
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22a_m.sp ('sky130_fd_sc_lp__o22a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22a/sky130_fd_sc_lp__o22a_m.spice ('sky130_fd_sc_lp__o22a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22a_m sky130_fd_sc_lp__o22a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o22a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 B1 B2 A2 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_m.pex.spice b/cells/o22a/sky130_fd_sc_lp__o22a_m.pex.spice
index 836a81c..2f9f4f6 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_m.pex.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_m.pex.spice
-* Created: Fri Aug 28 11:10:11 2020
+* Created: Wed Sep 2 10:20:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_m.pxi.spice b/cells/o22a/sky130_fd_sc_lp__o22a_m.pxi.spice
index dc6ac51..93fb987 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_m.pxi.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_m.pxi.spice
-* Created: Fri Aug 28 11:10:11 2020
+* Created: Wed Sep 2 10:20:19 2020
*
x_PM_SKY130_FD_SC_LP__O22A_M%A_88_187# N_A_88_187#_M1008_d N_A_88_187#_M1001_d
+ N_A_88_187#_c_62_n N_A_88_187#_M1000_g N_A_88_187#_M1002_g N_A_88_187#_c_64_n
diff --git a/cells/o22a/sky130_fd_sc_lp__o22a_m.spice b/cells/o22a/sky130_fd_sc_lp__o22a_m.spice
index 9a15832..971285b 100644
--- a/cells/o22a/sky130_fd_sc_lp__o22a_m.spice
+++ b/cells/o22a/sky130_fd_sc_lp__o22a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22a_m.spice
-* Created: Fri Aug 28 11:10:11 2020
+* Created: Wed Sep 2 10:20:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.lvs.report
new file mode 100644
index 0000000..2bccdd8
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_0.sp ('sky130_fd_sc_lp__o22ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_0.spice ('sky130_fd_sc_lp__o22ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_0 sky130_fd_sc_lp__o22ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pex.spice
index d03b755..aac52d7 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_0.pex.spice
-* Created: Fri Aug 28 11:10:22 2020
+* Created: Wed Sep 2 10:20:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pxi.spice
index 3d805fd..5ae2af4 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_0.pxi.spice
-* Created: Fri Aug 28 11:10:22 2020
+* Created: Wed Sep 2 10:20:28 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_0%B1 N_B1_M1004_g N_B1_c_53_n N_B1_M1001_g
+ N_B1_c_59_n B1 B1 B1 B1 N_B1_c_55_n N_B1_c_56_n PM_SKY130_FD_SC_LP__O22AI_0%B1
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.spice
index c871d04..9a4e350 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_0.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_0.spice
-* Created: Fri Aug 28 11:10:22 2020
+* Created: Wed Sep 2 10:20:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.lvs.report
new file mode 100644
index 0000000..1bf1bb9
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_1.sp ('sky130_fd_sc_lp__o22ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_1.spice ('sky130_fd_sc_lp__o22ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_1 sky130_fd_sc_lp__o22ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pex.spice
index b979d2a..3b5c136 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_1.pex.spice
-* Created: Fri Aug 28 11:10:38 2020
+* Created: Wed Sep 2 10:20:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pxi.spice
index bb418a9..b339c97 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_1.pxi.spice
-* Created: Fri Aug 28 11:10:38 2020
+* Created: Wed Sep 2 10:20:35 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_1%B1 N_B1_c_45_n N_B1_M1003_g N_B1_M1007_g B1 B1
+ N_B1_c_48_n PM_SKY130_FD_SC_LP__O22AI_1%B1
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.spice
index e8f5e56..2148c48 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_1.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_1.spice
-* Created: Fri Aug 28 11:10:38 2020
+* Created: Wed Sep 2 10:20:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.lvs.report
new file mode 100644
index 0000000..3129b4c
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_2.sp ('sky130_fd_sc_lp__o22ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_2.spice ('sky130_fd_sc_lp__o22ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_2 sky130_fd_sc_lp__o22ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pex.spice
index dbf123e..ffedb85 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_2.pex.spice
-* Created: Fri Aug 28 11:10:51 2020
+* Created: Wed Sep 2 10:20:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pxi.spice
index a97b8e5..3afc9b3 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_2.pxi.spice
-* Created: Fri Aug 28 11:10:51 2020
+* Created: Wed Sep 2 10:20:42 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_2%B1 N_B1_c_76_n N_B1_M1012_g N_B1_M1006_g
+ N_B1_c_78_n N_B1_M1013_g N_B1_M1011_g N_B1_c_87_p B1 N_B1_c_81_n
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.spice
index 6e4f990..84ab9aa 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_2.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_2.spice
-* Created: Fri Aug 28 11:10:51 2020
+* Created: Wed Sep 2 10:20:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.lvs.report
new file mode 100644
index 0000000..982a082
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.lvs.report
@@ -0,0 +1,469 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_4.sp ('sky130_fd_sc_lp__o22ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_4.spice ('sky130_fd_sc_lp__o22ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_4 sky130_fd_sc_lp__o22ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pex.spice
index 3bf7f04..51f197a 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_4.pex.spice
-* Created: Fri Aug 28 11:10:59 2020
+* Created: Wed Sep 2 10:20:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pxi.spice
index c3cd2fe..7c844a0 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_4.pxi.spice
-* Created: Fri Aug 28 11:10:59 2020
+* Created: Wed Sep 2 10:20:50 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_4%A1 N_A1_M1001_g N_A1_M1002_g N_A1_M1006_g
+ N_A1_M1005_g N_A1_M1016_g N_A1_M1012_g N_A1_M1017_g N_A1_M1025_g N_A1_c_124_n
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.spice
index a7d1448..187fb74 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_4.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_4.spice
-* Created: Fri Aug 28 11:10:59 2020
+* Created: Wed Sep 2 10:20:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.lvs.report
new file mode 100644
index 0000000..f6f6465
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_lp.sp ('sky130_fd_sc_lp__o22ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.spice ('sky130_fd_sc_lp__o22ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:20:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_lp sky130_fd_sc_lp__o22ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pex.spice
index b0da17c..2bd7fde 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_lp.pex.spice
-* Created: Fri Aug 28 11:11:08 2020
+* Created: Wed Sep 2 10:20:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pxi.spice
index dfc218c..f9e721a 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_lp.pxi.spice
-* Created: Fri Aug 28 11:11:08 2020
+* Created: Wed Sep 2 10:20:57 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_LP%B1 N_B1_M1005_g N_B1_M1007_g N_B1_c_61_n
+ N_B1_c_62_n B1 N_B1_c_64_n N_B1_c_65_n PM_SKY130_FD_SC_LP__O22AI_LP%B1
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.spice
index a32bffc..7fdd6fb 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_lp.spice
-* Created: Fri Aug 28 11:11:08 2020
+* Created: Wed Sep 2 10:20:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.lvs.report b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.lvs.report
new file mode 100644
index 0000000..a6deb2b
--- /dev/null
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o22ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o22ai_m.sp ('sky130_fd_sc_lp__o22ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o22ai/sky130_fd_sc_lp__o22ai_m.spice ('sky130_fd_sc_lp__o22ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o22ai_m sky130_fd_sc_lp__o22ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o22ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o22ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 2 2 SMP2 (4 pins)
+ 1 1 SPMN_2_2 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 SMP2
+ 1 1 0 0 SPMN_2_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pex.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pex.spice
index eea53cf..18ac6df 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pex.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_m.pex.spice
-* Created: Fri Aug 28 11:11:18 2020
+* Created: Wed Sep 2 10:21:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pxi.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pxi.spice
index a9352eb..730061e 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pxi.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_m.pxi.spice
-* Created: Fri Aug 28 11:11:18 2020
+* Created: Wed Sep 2 10:21:05 2020
*
x_PM_SKY130_FD_SC_LP__O22AI_M%B1 N_B1_c_62_n N_B1_c_63_n N_B1_c_64_n N_B1_c_70_n
+ N_B1_c_71_n N_B1_c_65_n N_B1_M1004_g N_B1_M1001_g N_B1_c_66_n B1 B1 B1 B1 B1
diff --git a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.spice b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.spice
index e7d9104..4cba935 100644
--- a/cells/o22ai/sky130_fd_sc_lp__o22ai_m.spice
+++ b/cells/o22ai/sky130_fd_sc_lp__o22ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o22ai_m.spice
-* Created: Fri Aug 28 11:11:18 2020
+* Created: Wed Sep 2 10:21:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.lvs.report
new file mode 100644
index 0000000..47f8a39
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_0.sp ('sky130_fd_sc_lp__o2bb2a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.spice ('sky130_fd_sc_lp__o2bb2a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_0 sky130_fd_sc_lp__o2bb2a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pex.spice
index cca7517..b6257bd 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_0.pex.spice
-* Created: Fri Aug 28 11:11:29 2020
+* Created: Wed Sep 2 10:21:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pxi.spice
index 6a5face..9b7c474 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_0.pxi.spice
-* Created: Fri Aug 28 11:11:29 2020
+* Created: Wed Sep 2 10:21:13 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_0%A_80_176# N_A_80_176#_M1001_s N_A_80_176#_M1011_d
+ N_A_80_176#_c_96_n N_A_80_176#_M1005_g N_A_80_176#_M1002_g N_A_80_176#_c_98_n
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.spice
index 3636495..4c1e3fe 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_0.spice
-* Created: Fri Aug 28 11:11:29 2020
+* Created: Wed Sep 2 10:21:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.lvs.report
new file mode 100644
index 0000000..ddf1415
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_1.sp ('sky130_fd_sc_lp__o2bb2a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.spice ('sky130_fd_sc_lp__o2bb2a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_1 sky130_fd_sc_lp__o2bb2a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pex.spice
index 8df050c..7f4865f 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_1.pex.spice
-* Created: Fri Aug 28 11:11:41 2020
+* Created: Wed Sep 2 10:21:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pxi.spice
index 28ab0a4..82407ca 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_1.pxi.spice
-* Created: Fri Aug 28 11:11:41 2020
+* Created: Wed Sep 2 10:21:20 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_1%A_80_21# N_A_80_21#_M1003_s N_A_80_21#_M1001_d
+ N_A_80_21#_M1005_g N_A_80_21#_M1011_g N_A_80_21#_c_82_n N_A_80_21#_c_83_n
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.spice
index 6f36405..1d7f29b 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_1.spice
-* Created: Fri Aug 28 11:11:41 2020
+* Created: Wed Sep 2 10:21:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.lvs.report
new file mode 100644
index 0000000..f42d5df
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_2.sp ('sky130_fd_sc_lp__o2bb2a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.spice ('sky130_fd_sc_lp__o2bb2a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_2 sky130_fd_sc_lp__o2bb2a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A2_N A1_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pex.spice
index 154c82f..5b918f8 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_2.pex.spice
-* Created: Fri Aug 28 11:11:53 2020
+* Created: Wed Sep 2 10:21:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pxi.spice
index 0775f98..bb0582c 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_2.pxi.spice
-* Created: Fri Aug 28 11:11:53 2020
+* Created: Wed Sep 2 10:21:28 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_2%B1 N_B1_M1004_g N_B1_M1001_g N_B1_c_91_n
+ N_B1_c_92_n B1 N_B1_c_94_n PM_SKY130_FD_SC_LP__O2BB2A_2%B1
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.spice
index 1aff4f0..f0b104c 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_2.spice
-* Created: Fri Aug 28 11:11:53 2020
+* Created: Wed Sep 2 10:21:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.lvs.report
new file mode 100644
index 0000000..7f8618e
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_4.sp ('sky130_fd_sc_lp__o2bb2a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.spice ('sky130_fd_sc_lp__o2bb2a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_4 sky130_fd_sc_lp__o2bb2a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1_N A2_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pex.spice
index 3dac14e..f610f25 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_4.pex.spice
-* Created: Fri Aug 28 11:12:01 2020
+* Created: Wed Sep 2 10:21:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pxi.spice
index d98e20a..650a98b 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_4.pxi.spice
-* Created: Fri Aug 28 11:12:01 2020
+* Created: Wed Sep 2 10:21:35 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_4%B1 N_B1_M1006_g N_B1_M1011_g N_B1_M1026_g
+ N_B1_M1009_g N_B1_c_132_n N_B1_c_133_n N_B1_c_139_n N_B1_c_140_n N_B1_c_134_n
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.spice
index ba29e92..1630862 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_4.spice
-* Created: Fri Aug 28 11:12:01 2020
+* Created: Wed Sep 2 10:21:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.lvs.report
new file mode 100644
index 0000000..f738d0c
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_lp.sp ('sky130_fd_sc_lp__o2bb2a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.spice ('sky130_fd_sc_lp__o2bb2a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_lp sky130_fd_sc_lp__o2bb2a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 4 4 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 4 4 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pex.spice
index 357b056..3c74183 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_lp.pex.spice
-* Created: Fri Aug 28 11:12:09 2020
+* Created: Wed Sep 2 10:21:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pxi.spice
index 7196aef..93f71af 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_lp.pxi.spice
-* Created: Fri Aug 28 11:12:09 2020
+* Created: Wed Sep 2 10:21:43 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_LP%A_86_22# N_A_86_22#_M1012_s N_A_86_22#_M1000_d
+ N_A_86_22#_M1009_g N_A_86_22#_c_80_n N_A_86_22#_M1005_g N_A_86_22#_M1006_g
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.spice
index 12cf5f5..62cd612 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_lp.spice
-* Created: Fri Aug 28 11:12:09 2020
+* Created: Wed Sep 2 10:21:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.lvs.report b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.lvs.report
new file mode 100644
index 0000000..7d710b9
--- /dev/null
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2a_m.sp ('sky130_fd_sc_lp__o2bb2a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.spice ('sky130_fd_sc_lp__o2bb2a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2a_m sky130_fd_sc_lp__o2bb2a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 4 4 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pex.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pex.spice
index 434ab9a..418d505 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pex.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_m.pex.spice
-* Created: Fri Aug 28 11:12:17 2020
+* Created: Wed Sep 2 10:21:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pxi.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pxi.spice
index 552edcb..42995f7 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pxi.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_m.pxi.spice
-* Created: Fri Aug 28 11:12:17 2020
+* Created: Wed Sep 2 10:21:51 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2A_M%A_85_187# N_A_85_187#_M1003_s N_A_85_187#_M1000_d
+ N_A_85_187#_M1001_g N_A_85_187#_M1006_g N_A_85_187#_c_82_n N_A_85_187#_c_83_n
diff --git a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.spice b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.spice
index 7706f13..6544753 100644
--- a/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.spice
+++ b/cells/o2bb2a/sky130_fd_sc_lp__o2bb2a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2a_m.spice
-* Created: Fri Aug 28 11:12:17 2020
+* Created: Wed Sep 2 10:21:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.lvs.report
new file mode 100644
index 0000000..a752507
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_0.sp ('sky130_fd_sc_lp__o2bb2ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.spice ('sky130_fd_sc_lp__o2bb2ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:21:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_0 sky130_fd_sc_lp__o2bb2ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pex.spice
index 814c24e..a1c58f9 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_0.pex.spice
-* Created: Fri Aug 28 11:12:26 2020
+* Created: Wed Sep 2 10:22:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pxi.spice
index d29f9a4..757af0c 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_0.pxi.spice
-* Created: Fri Aug 28 11:12:26 2020
+* Created: Wed Sep 2 10:22:02 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_0%A1_N N_A1_N_c_84_n N_A1_N_M1003_g N_A1_N_c_91_n
+ N_A1_N_c_92_n N_A1_N_M1005_g N_A1_N_c_86_n N_A1_N_c_87_n A1_N A1_N A1_N A1_N
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.spice
index 8ecf3ba..c7fb2af 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_0.spice
-* Created: Fri Aug 28 11:12:26 2020
+* Created: Wed Sep 2 10:22:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.lvs.report
new file mode 100644
index 0000000..601c8fe
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_1.sp ('sky130_fd_sc_lp__o2bb2ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.spice ('sky130_fd_sc_lp__o2bb2ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_1 sky130_fd_sc_lp__o2bb2ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pex.spice
index 50ba776..041dffd 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_1.pex.spice
-* Created: Fri Aug 28 11:12:34 2020
+* Created: Wed Sep 2 10:22:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pxi.spice
index 42fea7d..dd1d654 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_1.pxi.spice
-* Created: Fri Aug 28 11:12:34 2020
+* Created: Wed Sep 2 10:22:09 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_1%A1_N N_A1_N_M1003_g N_A1_N_M1005_g A1_N A1_N
+ N_A1_N_c_67_n N_A1_N_c_68_n PM_SKY130_FD_SC_LP__O2BB2AI_1%A1_N
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.spice
index 8c9b9b6..b700f1e 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_1.spice
-* Created: Fri Aug 28 11:12:34 2020
+* Created: Wed Sep 2 10:22:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.lvs.report
new file mode 100644
index 0000000..a394fcc
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_2.sp ('sky130_fd_sc_lp__o2bb2ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.spice ('sky130_fd_sc_lp__o2bb2ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_2 sky130_fd_sc_lp__o2bb2ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B1 B2 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pex.spice
index 9bb84ad..de99bff 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_2.pex.spice
-* Created: Fri Aug 28 11:12:46 2020
+* Created: Wed Sep 2 10:22:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pxi.spice
index 9af5072..5423a4a 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_2.pxi.spice
-* Created: Fri Aug 28 11:12:46 2020
+* Created: Wed Sep 2 10:22:17 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_2%A1_N N_A1_N_M1015_g N_A1_N_M1001_g
+ N_A1_N_M1017_g N_A1_N_M1007_g N_A1_N_c_113_p N_A1_N_c_101_n N_A1_N_c_102_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.spice
index 5f842d4..b381ab5 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_2.spice
-* Created: Fri Aug 28 11:12:46 2020
+* Created: Wed Sep 2 10:22:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.lvs.report
new file mode 100644
index 0000000..2c6939c
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_4.sp ('sky130_fd_sc_lp__o2bb2ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.spice ('sky130_fd_sc_lp__o2bb2ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_4 sky130_fd_sc_lp__o2bb2ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A1_N A2_N VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pex.spice
index 75abbe8..5e628b8 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_4.pex.spice
-* Created: Fri Aug 28 11:12:58 2020
+* Created: Wed Sep 2 10:22:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pxi.spice
index 500db7c..37c10f9 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_4.pxi.spice
-* Created: Fri Aug 28 11:12:58 2020
+* Created: Wed Sep 2 10:22:24 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_4%B1 N_B1_M1017_g N_B1_M1009_g N_B1_M1019_g
+ N_B1_M1012_g N_B1_M1034_g N_B1_M1036_g N_B1_M1039_g N_B1_M1038_g N_B1_c_166_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.spice
index 4af2990..a517e91 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_4.spice
-* Created: Fri Aug 28 11:12:58 2020
+* Created: Wed Sep 2 10:22:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.lvs.report
new file mode 100644
index 0000000..b1f0980
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_lp.sp ('sky130_fd_sc_lp__o2bb2ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.spice ('sky130_fd_sc_lp__o2bb2ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_lp sky130_fd_sc_lp__o2bb2ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pex.spice
index de566fc..4112e8b 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_lp.pex.spice
-* Created: Fri Aug 28 11:13:06 2020
+* Created: Wed Sep 2 10:22:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pxi.spice
index 95eccca..6c249ab 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_lp.pxi.spice
-* Created: Fri Aug 28 11:13:06 2020
+* Created: Wed Sep 2 10:22:31 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_LP%A1_N N_A1_N_M1001_g N_A1_N_M1006_g A1_N A1_N
+ N_A1_N_c_67_n PM_SKY130_FD_SC_LP__O2BB2AI_LP%A1_N
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.spice
index 4d0f6ca..be9023d 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_lp.spice
-* Created: Fri Aug 28 11:13:06 2020
+* Created: Wed Sep 2 10:22:31 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.lvs.report b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.lvs.report
new file mode 100644
index 0000000..b63b9ce
--- /dev/null
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o2bb2ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o2bb2ai_m.sp ('sky130_fd_sc_lp__o2bb2ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.spice ('sky130_fd_sc_lp__o2bb2ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o2bb2ai_m sky130_fd_sc_lp__o2bb2ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o2bb2ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o2bb2ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1_N A2_N B2 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pex.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pex.spice
index 6dded9b..17309c6 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pex.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_m.pex.spice
-* Created: Fri Aug 28 11:13:14 2020
+* Created: Wed Sep 2 10:22:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pxi.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pxi.spice
index 14caf07..4b0dbcc 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pxi.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_m.pxi.spice
-* Created: Fri Aug 28 11:13:14 2020
+* Created: Wed Sep 2 10:22:38 2020
*
x_PM_SKY130_FD_SC_LP__O2BB2AI_M%A1_N N_A1_N_M1008_g N_A1_N_M1006_g A1_N A1_N
+ A1_N A1_N A1_N N_A1_N_c_74_n N_A1_N_c_75_n N_A1_N_c_76_n
diff --git a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.spice b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.spice
index 7749821..0cc9263 100644
--- a/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.spice
+++ b/cells/o2bb2ai/sky130_fd_sc_lp__o2bb2ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o2bb2ai_m.spice
-* Created: Fri Aug 28 11:13:14 2020
+* Created: Wed Sep 2 10:22:38 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_0.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_0.lvs.report
new file mode 100644
index 0000000..98cedff
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_0.sp ('sky130_fd_sc_lp__o311a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_0.spice ('sky130_fd_sc_lp__o311a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:42 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_0 sky130_fd_sc_lp__o311a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_0.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_0.pex.spice
index 7ab0496..6e5cb0e 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_0.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_0.pex.spice
-* Created: Fri Aug 28 11:13:22 2020
+* Created: Wed Sep 2 10:22:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_0.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_0.pxi.spice
index e986a36..522e447 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_0.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_0.pxi.spice
-* Created: Fri Aug 28 11:13:22 2020
+* Created: Wed Sep 2 10:22:46 2020
*
x_PM_SKY130_FD_SC_LP__O311A_0%A_96_161# N_A_96_161#_M1010_d N_A_96_161#_M1007_d
+ N_A_96_161#_M1001_d N_A_96_161#_c_92_n N_A_96_161#_c_93_n N_A_96_161#_M1000_g
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_0.spice b/cells/o311a/sky130_fd_sc_lp__o311a_0.spice
index 04fa92c..033866d 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_0.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_0.spice
-* Created: Fri Aug 28 11:13:22 2020
+* Created: Wed Sep 2 10:22:46 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_1.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_1.lvs.report
new file mode 100644
index 0000000..ec5065f
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_1.sp ('sky130_fd_sc_lp__o311a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_1.spice ('sky130_fd_sc_lp__o311a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_1 sky130_fd_sc_lp__o311a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_1.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_1.pex.spice
index 05abe48..88c877a 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_1.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_1.pex.spice
-* Created: Fri Aug 28 11:13:30 2020
+* Created: Wed Sep 2 10:22:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_1.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_1.pxi.spice
index 94542ff..562c790 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_1.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_1.pxi.spice
-* Created: Fri Aug 28 11:13:30 2020
+* Created: Wed Sep 2 10:22:53 2020
*
x_PM_SKY130_FD_SC_LP__O311A_1%A_80_21# N_A_80_21#_M1008_d N_A_80_21#_M1000_d
+ N_A_80_21#_M1009_d N_A_80_21#_M1003_g N_A_80_21#_M1002_g N_A_80_21#_c_64_n
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_1.spice b/cells/o311a/sky130_fd_sc_lp__o311a_1.spice
index d1a298f..b5f870b 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_1.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_1.spice
-* Created: Fri Aug 28 11:13:30 2020
+* Created: Wed Sep 2 10:22:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_2.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_2.lvs.report
new file mode 100644
index 0000000..c4273fe
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_2.sp ('sky130_fd_sc_lp__o311a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_2.spice ('sky130_fd_sc_lp__o311a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:22:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_2 sky130_fd_sc_lp__o311a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_2.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_2.pex.spice
index 5768b2d..b6c9dea 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_2.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_2.pex.spice
-* Created: Fri Aug 28 11:13:39 2020
+* Created: Wed Sep 2 10:23:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_2.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_2.pxi.spice
index 867211b..621ea10 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_2.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_2.pxi.spice
-* Created: Fri Aug 28 11:13:39 2020
+* Created: Wed Sep 2 10:23:01 2020
*
x_PM_SKY130_FD_SC_LP__O311A_2%A_85_21# N_A_85_21#_M1007_d N_A_85_21#_M1005_d
+ N_A_85_21#_M1001_d N_A_85_21#_c_72_n N_A_85_21#_M1012_g N_A_85_21#_M1003_g
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_2.spice b/cells/o311a/sky130_fd_sc_lp__o311a_2.spice
index 1ae0d05..fc7045f 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_2.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_2.spice
-* Created: Fri Aug 28 11:13:39 2020
+* Created: Wed Sep 2 10:23:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_4.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_4.lvs.report
new file mode 100644
index 0000000..fcace85
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_4.sp ('sky130_fd_sc_lp__o311a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_4.spice ('sky130_fd_sc_lp__o311a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_4 sky130_fd_sc_lp__o311a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C1 B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_4.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_4.pex.spice
index 3eabf17..0b63d32 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_4.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_4.pex.spice
-* Created: Fri Aug 28 11:13:50 2020
+* Created: Wed Sep 2 10:23:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_4.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_4.pxi.spice
index 4721675..f26bae3 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_4.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_4.pxi.spice
-* Created: Fri Aug 28 11:13:50 2020
+* Created: Wed Sep 2 10:23:09 2020
*
x_PM_SKY130_FD_SC_LP__O311A_4%A_81_23# N_A_81_23#_M1012_d N_A_81_23#_M1007_s
+ N_A_81_23#_M1010_d N_A_81_23#_M1004_s N_A_81_23#_M1000_g N_A_81_23#_M1003_g
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_4.spice b/cells/o311a/sky130_fd_sc_lp__o311a_4.spice
index 6679bf4..45405b5 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_4.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_4.spice
-* Created: Fri Aug 28 11:13:50 2020
+* Created: Wed Sep 2 10:23:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_lp.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_lp.lvs.report
new file mode 100644
index 0000000..6d69bdc
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_lp.sp ('sky130_fd_sc_lp__o311a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_lp.spice ('sky130_fd_sc_lp__o311a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_lp sky130_fd_sc_lp__o311a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_lp.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_lp.pex.spice
index ba0306e..cdb5a60 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_lp.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_lp.pex.spice
-* Created: Fri Aug 28 11:14:03 2020
+* Created: Wed Sep 2 10:23:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_lp.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_lp.pxi.spice
index c7acaf2..dbbc91a 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_lp.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_lp.pxi.spice
-* Created: Fri Aug 28 11:14:03 2020
+* Created: Wed Sep 2 10:23:17 2020
*
x_PM_SKY130_FD_SC_LP__O311A_LP%A_84_115# N_A_84_115#_M1004_d N_A_84_115#_M1010_d
+ N_A_84_115#_M1005_d N_A_84_115#_c_73_n N_A_84_115#_M1001_g N_A_84_115#_M1009_g
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_lp.spice b/cells/o311a/sky130_fd_sc_lp__o311a_lp.spice
index 30845a6..13d387c 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_lp.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_lp.spice
-* Created: Fri Aug 28 11:14:03 2020
+* Created: Wed Sep 2 10:23:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_m.lvs.report b/cells/o311a/sky130_fd_sc_lp__o311a_m.lvs.report
new file mode 100644
index 0000000..5ef00c4
--- /dev/null
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311a_m.sp ('sky130_fd_sc_lp__o311a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311a/sky130_fd_sc_lp__o311a_m.spice ('sky130_fd_sc_lp__o311a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311a_m sky130_fd_sc_lp__o311a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o311a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_m.pex.spice b/cells/o311a/sky130_fd_sc_lp__o311a_m.pex.spice
index 47746ba..9fb452e 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_m.pex.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_m.pex.spice
-* Created: Fri Aug 28 11:14:11 2020
+* Created: Wed Sep 2 10:23:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_m.pxi.spice b/cells/o311a/sky130_fd_sc_lp__o311a_m.pxi.spice
index e8aacd5..2905bca 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_m.pxi.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_m.pxi.spice
-* Created: Fri Aug 28 11:14:11 2020
+* Created: Wed Sep 2 10:23:26 2020
*
x_PM_SKY130_FD_SC_LP__O311A_M%A1 N_A1_c_85_n N_A1_M1004_g N_A1_M1003_g
+ N_A1_c_86_n N_A1_c_87_n N_A1_c_88_n A1 A1 A1 N_A1_c_90_n N_A1_c_91_n
diff --git a/cells/o311a/sky130_fd_sc_lp__o311a_m.spice b/cells/o311a/sky130_fd_sc_lp__o311a_m.spice
index a3f36fb..9453ceb 100644
--- a/cells/o311a/sky130_fd_sc_lp__o311a_m.spice
+++ b/cells/o311a/sky130_fd_sc_lp__o311a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311a_m.spice
-* Created: Fri Aug 28 11:14:11 2020
+* Created: Wed Sep 2 10:23:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.lvs.report
new file mode 100644
index 0000000..bfe0c6b
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_0.sp ('sky130_fd_sc_lp__o311ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_0.spice ('sky130_fd_sc_lp__o311ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_0 sky130_fd_sc_lp__o311ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pex.spice
index 6f24c3d..26b11d8 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_0.pex.spice
-* Created: Fri Aug 28 11:14:19 2020
+* Created: Wed Sep 2 10:23:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pxi.spice
index 02421df..7c342a0 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_0.pxi.spice
-* Created: Fri Aug 28 11:14:19 2020
+* Created: Wed Sep 2 10:23:37 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_0%A1 N_A1_c_78_n N_A1_c_79_n N_A1_M1005_g
+ N_A1_c_85_n N_A1_M1001_g N_A1_c_80_n N_A1_c_81_n N_A1_c_86_n A1 A1 A1
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.spice
index 0afef72..0efd53b 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_0.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_0.spice
-* Created: Fri Aug 28 11:14:19 2020
+* Created: Wed Sep 2 10:23:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.lvs.report
new file mode 100644
index 0000000..cded51e
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_1.sp ('sky130_fd_sc_lp__o311ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_1.spice ('sky130_fd_sc_lp__o311ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_1 sky130_fd_sc_lp__o311ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pex.spice
index b5f96d0..0b9d153 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_1.pex.spice
-* Created: Fri Aug 28 11:14:26 2020
+* Created: Wed Sep 2 10:23:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pxi.spice
index d6b4b9b..a950ddd 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_1.pxi.spice
-* Created: Fri Aug 28 11:14:26 2020
+* Created: Wed Sep 2 10:23:44 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_1%A1 N_A1_M1000_g N_A1_M1009_g A1 A1 N_A1_c_57_n
+ PM_SKY130_FD_SC_LP__O311AI_1%A1
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.spice
index 8215d9a..f4cd501 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_1.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_1.spice
-* Created: Fri Aug 28 11:14:26 2020
+* Created: Wed Sep 2 10:23:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.lvs.report
new file mode 100644
index 0000000..8a10869
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_2.sp ('sky130_fd_sc_lp__o311ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_2.spice ('sky130_fd_sc_lp__o311ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_2 sky130_fd_sc_lp__o311ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pex.spice
index 9dea22c..f426c70 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_2.pex.spice
-* Created: Fri Aug 28 11:14:35 2020
+* Created: Wed Sep 2 10:23:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pxi.spice
index d4d20bb..9881693 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_2.pxi.spice
-* Created: Fri Aug 28 11:14:35 2020
+* Created: Wed Sep 2 10:23:52 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_2%A1 N_A1_c_87_n N_A1_M1018_g N_A1_M1004_g
+ N_A1_c_89_n N_A1_M1019_g N_A1_M1012_g A1 A1 N_A1_c_92_n
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.spice
index 221cbd9..edc6162 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_2.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_2.spice
-* Created: Fri Aug 28 11:14:35 2020
+* Created: Wed Sep 2 10:23:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.lvs.report
new file mode 100644
index 0000000..4c88b89
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_4.sp ('sky130_fd_sc_lp__o311ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_4.spice ('sky130_fd_sc_lp__o311ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:23:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_4 sky130_fd_sc_lp__o311ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pex.spice
index 467b2dd..786223a 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_4.pex.spice
-* Created: Fri Aug 28 11:14:44 2020
+* Created: Wed Sep 2 10:23:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pxi.spice
index 93372e3..29d4b2d 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_4.pxi.spice
-* Created: Fri Aug 28 11:14:44 2020
+* Created: Wed Sep 2 10:23:59 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_4%A1 N_A1_c_146_n N_A1_M1002_g N_A1_M1005_g
+ N_A1_c_148_n N_A1_M1016_g N_A1_M1013_g N_A1_c_150_n N_A1_M1018_g N_A1_M1027_g
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.spice
index 0e08077..2faa2d4 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_4.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_4.spice
-* Created: Fri Aug 28 11:14:44 2020
+* Created: Wed Sep 2 10:23:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.lvs.report
new file mode 100644
index 0000000..c199c36
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_lp.sp ('sky130_fd_sc_lp__o311ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.spice ('sky130_fd_sc_lp__o311ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_lp sky130_fd_sc_lp__o311ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pex.spice
index c55c3e3..1a2701d 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_lp.pex.spice
-* Created: Fri Aug 28 11:14:55 2020
+* Created: Wed Sep 2 10:24:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pxi.spice
index 6ef598f..4364916 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_lp.pxi.spice
-* Created: Fri Aug 28 11:14:55 2020
+* Created: Wed Sep 2 10:24:06 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_LP%A1 N_A1_M1008_g N_A1_M1009_g A1 N_A1_c_57_n
+ N_A1_c_58_n PM_SKY130_FD_SC_LP__O311AI_LP%A1
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.spice
index df58f02..eaeaad3 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_lp.spice
-* Created: Fri Aug 28 11:14:55 2020
+* Created: Wed Sep 2 10:24:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.lvs.report b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.lvs.report
new file mode 100644
index 0000000..0319e9a
--- /dev/null
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o311ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o311ai_m.sp ('sky130_fd_sc_lp__o311ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o311ai/sky130_fd_sc_lp__o311ai_m.spice ('sky130_fd_sc_lp__o311ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o311ai_m sky130_fd_sc_lp__o311ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o311ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o311ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1_1 (7 pins)
+ ------ ------
+ Total Inst: 4 4
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1_1
+ ------- ------- --------- ---------
+ Total Inst: 4 4 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 C1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pex.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pex.spice
index d6064b7..5732813 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pex.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_m.pex.spice
-* Created: Fri Aug 28 11:15:08 2020
+* Created: Wed Sep 2 10:24:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pxi.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pxi.spice
index b7dca4b..8ba822f 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pxi.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_m.pxi.spice
-* Created: Fri Aug 28 11:15:08 2020
+* Created: Wed Sep 2 10:24:14 2020
*
x_PM_SKY130_FD_SC_LP__O311AI_M%A1 N_A1_M1008_g N_A1_M1005_g N_A1_c_68_n
+ N_A1_c_69_n A1 A1 A1 N_A1_c_71_n N_A1_c_72_n PM_SKY130_FD_SC_LP__O311AI_M%A1
diff --git a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.spice b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.spice
index d48995e..4b07f45 100644
--- a/cells/o311ai/sky130_fd_sc_lp__o311ai_m.spice
+++ b/cells/o311ai/sky130_fd_sc_lp__o311ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o311ai_m.spice
-* Created: Fri Aug 28 11:15:08 2020
+* Created: Wed Sep 2 10:24:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_0.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_0.lvs.report
new file mode 100644
index 0000000..eea14a6
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_0.sp ('sky130_fd_sc_lp__o31a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_0.spice ('sky130_fd_sc_lp__o31a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_0 sky130_fd_sc_lp__o31a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_0.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_0.pex.spice
index 90f1adc..73883a1 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_0.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_0.pex.spice
-* Created: Fri Aug 28 11:15:16 2020
+* Created: Wed Sep 2 10:24:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_0.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_0.pxi.spice
index bc47a66..61efd92 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_0.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_0.pxi.spice
-* Created: Fri Aug 28 11:15:16 2020
+* Created: Wed Sep 2 10:24:22 2020
*
x_PM_SKY130_FD_SC_LP__O31A_0%A_90_309# N_A_90_309#_M1007_d N_A_90_309#_M1009_d
+ N_A_90_309#_M1001_g N_A_90_309#_M1008_g N_A_90_309#_c_81_n N_A_90_309#_c_82_n
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_0.spice b/cells/o31a/sky130_fd_sc_lp__o31a_0.spice
index 0dcb014..8ffba44 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_0.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_0.spice
-* Created: Fri Aug 28 11:15:16 2020
+* Created: Wed Sep 2 10:24:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_1.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_1.lvs.report
new file mode 100644
index 0000000..2aee4e7
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_1.sp ('sky130_fd_sc_lp__o31a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_1.spice ('sky130_fd_sc_lp__o31a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_1 sky130_fd_sc_lp__o31a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_1.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_1.pex.spice
index a91aeea..b51cece 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_1.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_1.pex.spice
-* Created: Fri Aug 28 11:15:23 2020
+* Created: Wed Sep 2 10:24:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_1.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_1.pxi.spice
index 37df369..9e35090 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_1.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_1.pxi.spice
-* Created: Fri Aug 28 11:15:23 2020
+* Created: Wed Sep 2 10:24:29 2020
*
x_PM_SKY130_FD_SC_LP__O31A_1%A_86_23# N_A_86_23#_M1008_d N_A_86_23#_M1001_d
+ N_A_86_23#_M1005_g N_A_86_23#_M1003_g N_A_86_23#_c_57_n N_A_86_23#_c_58_n
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_1.spice b/cells/o31a/sky130_fd_sc_lp__o31a_1.spice
index b7de3c7..1344070 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_1.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_1.spice
-* Created: Fri Aug 28 11:15:23 2020
+* Created: Wed Sep 2 10:24:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_2.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_2.lvs.report
new file mode 100644
index 0000000..4a6e2c8
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_2.sp ('sky130_fd_sc_lp__o31a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_2.spice ('sky130_fd_sc_lp__o31a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_2 sky130_fd_sc_lp__o31a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_2.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_2.pex.spice
index 2a0d164..cd2be0b 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_2.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_2.pex.spice
-* Created: Fri Aug 28 11:15:31 2020
+* Created: Wed Sep 2 10:24:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_2.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_2.pxi.spice
index f7d8761..d7b9a84 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_2.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_2.pxi.spice
-* Created: Fri Aug 28 11:15:31 2020
+* Created: Wed Sep 2 10:24:37 2020
*
x_PM_SKY130_FD_SC_LP__O31A_2%A_85_21# N_A_85_21#_M1003_d N_A_85_21#_M1005_d
+ N_A_85_21#_c_64_n N_A_85_21#_M1010_g N_A_85_21#_M1002_g N_A_85_21#_c_66_n
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_2.spice b/cells/o31a/sky130_fd_sc_lp__o31a_2.spice
index 579e6d0..556e13f 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_2.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_2.spice
-* Created: Fri Aug 28 11:15:31 2020
+* Created: Wed Sep 2 10:24:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_4.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_4.lvs.report
new file mode 100644
index 0000000..c9b2ccb
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_4.sp ('sky130_fd_sc_lp__o31a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_4.spice ('sky130_fd_sc_lp__o31a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_4 sky130_fd_sc_lp__o31a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 24 layout mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+ 24 source mos transistors were reduced to 10.
+ 14 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_4.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_4.pex.spice
index 83a8d00..ba168a8 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_4.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_4.pex.spice
-* Created: Fri Aug 28 11:15:40 2020
+* Created: Wed Sep 2 10:24:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_4.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_4.pxi.spice
index 956e91c..99ca740 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_4.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_4.pxi.spice
-* Created: Fri Aug 28 11:15:40 2020
+* Created: Wed Sep 2 10:24:44 2020
*
x_PM_SKY130_FD_SC_LP__O31A_4%A_101_23# N_A_101_23#_M1014_d N_A_101_23#_M1006_s
+ N_A_101_23#_M1015_s N_A_101_23#_M1001_g N_A_101_23#_M1000_g
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_4.spice b/cells/o31a/sky130_fd_sc_lp__o31a_4.spice
index 28854ce..688c8fc 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_4.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_4.spice
-* Created: Fri Aug 28 11:15:40 2020
+* Created: Wed Sep 2 10:24:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_lp.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_lp.lvs.report
new file mode 100644
index 0000000..628ab4b
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_lp.sp ('sky130_fd_sc_lp__o31a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_lp.spice ('sky130_fd_sc_lp__o31a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_lp sky130_fd_sc_lp__o31a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 12 11
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_lp.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_lp.pex.spice
index 2ce3462..bf0f045 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_lp.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_lp.pex.spice
-* Created: Fri Aug 28 11:15:48 2020
+* Created: Wed Sep 2 10:24:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_lp.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_lp.pxi.spice
index 61f5636..cfb8ecc 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_lp.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_lp.pxi.spice
-* Created: Fri Aug 28 11:15:48 2020
+* Created: Wed Sep 2 10:24:51 2020
*
x_PM_SKY130_FD_SC_LP__O31A_LP%B1 N_B1_M1010_g N_B1_M1009_g N_B1_c_78_n
+ N_B1_c_79_n B1 B1 N_B1_c_80_n N_B1_c_81_n PM_SKY130_FD_SC_LP__O31A_LP%B1
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_lp.spice b/cells/o31a/sky130_fd_sc_lp__o31a_lp.spice
index 3ccc8e0..c4f6f03 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_lp.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_lp.spice
-* Created: Fri Aug 28 11:15:48 2020
+* Created: Wed Sep 2 10:24:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_m.lvs.report b/cells/o31a/sky130_fd_sc_lp__o31a_m.lvs.report
new file mode 100644
index 0000000..ab5008d
--- /dev/null
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31a_m.sp ('sky130_fd_sc_lp__o31a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31a/sky130_fd_sc_lp__o31a_m.spice ('sky130_fd_sc_lp__o31a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:24:55 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31a_m sky130_fd_sc_lp__o31a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o31a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_m.pex.spice b/cells/o31a/sky130_fd_sc_lp__o31a_m.pex.spice
index 02122fb..0bd9284 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_m.pex.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_m.pex.spice
-* Created: Fri Aug 28 11:16:00 2020
+* Created: Wed Sep 2 10:24:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_m.pxi.spice b/cells/o31a/sky130_fd_sc_lp__o31a_m.pxi.spice
index 2eca944..3279404 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_m.pxi.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_m.pxi.spice
-* Created: Fri Aug 28 11:16:00 2020
+* Created: Wed Sep 2 10:24:58 2020
*
x_PM_SKY130_FD_SC_LP__O31A_M%A1 N_A1_M1000_g N_A1_M1008_g N_A1_c_71_n
+ N_A1_c_75_n A1 A1 N_A1_c_73_n PM_SKY130_FD_SC_LP__O31A_M%A1
diff --git a/cells/o31a/sky130_fd_sc_lp__o31a_m.spice b/cells/o31a/sky130_fd_sc_lp__o31a_m.spice
index 9907292..7f345c8 100644
--- a/cells/o31a/sky130_fd_sc_lp__o31a_m.spice
+++ b/cells/o31a/sky130_fd_sc_lp__o31a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31a_m.spice
-* Created: Fri Aug 28 11:16:00 2020
+* Created: Wed Sep 2 10:24:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.lvs.report
new file mode 100644
index 0000000..13a0170
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_0.sp ('sky130_fd_sc_lp__o31ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_0.spice ('sky130_fd_sc_lp__o31ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_0 sky130_fd_sc_lp__o31ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pex.spice
index 3987e1a..1fc3bc0 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_0.pex.spice
-* Created: Fri Aug 28 11:16:13 2020
+* Created: Wed Sep 2 10:25:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pxi.spice
index 0cc00ae..8778bda 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_0.pxi.spice
-* Created: Fri Aug 28 11:16:13 2020
+* Created: Wed Sep 2 10:25:06 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_0%A1 N_A1_c_64_n N_A1_c_65_n N_A1_M1006_g
+ N_A1_c_71_n N_A1_M1000_g N_A1_c_66_n N_A1_c_67_n N_A1_c_72_n A1 A1 A1 A1
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.spice
index 28daaf2..93bf03b 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_0.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_0.spice
-* Created: Fri Aug 28 11:16:13 2020
+* Created: Wed Sep 2 10:25:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.lvs.report
new file mode 100644
index 0000000..5b0c640
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_1.sp ('sky130_fd_sc_lp__o31ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_1.spice ('sky130_fd_sc_lp__o31ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_1 sky130_fd_sc_lp__o31ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pex.spice
index 584875c..3325210 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_1.pex.spice
-* Created: Fri Aug 28 11:16:21 2020
+* Created: Wed Sep 2 10:25:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pxi.spice
index 003b6ae..fc03368 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_1.pxi.spice
-* Created: Fri Aug 28 11:16:21 2020
+* Created: Wed Sep 2 10:25:13 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_1%A1 N_A1_M1004_g N_A1_M1007_g A1 A1 N_A1_c_50_n
+ PM_SKY130_FD_SC_LP__O31AI_1%A1
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.spice
index 1f7073b..caf697a 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_1.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_1.spice
-* Created: Fri Aug 28 11:16:21 2020
+* Created: Wed Sep 2 10:25:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.lvs.report
new file mode 100644
index 0000000..4d8e69a
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_2.sp ('sky130_fd_sc_lp__o31ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_2.spice ('sky130_fd_sc_lp__o31ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_2 sky130_fd_sc_lp__o31ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 16 layout mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+ 16 source mos transistors were reduced to 8.
+ 8 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pex.spice
index 921c096..d9de08f 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_2.pex.spice
-* Created: Fri Aug 28 11:16:28 2020
+* Created: Wed Sep 2 10:25:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pxi.spice
index c0d7e1b..2a29935 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_2.pxi.spice
-* Created: Fri Aug 28 11:16:28 2020
+* Created: Wed Sep 2 10:25:21 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_2%A1 N_A1_M1002_g N_A1_c_74_n N_A1_M1000_g
+ N_A1_M1009_g N_A1_c_76_n N_A1_M1010_g A1 A1 A1 N_A1_c_78_n
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.spice
index b397bad..548a513 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_2.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_2.spice
-* Created: Fri Aug 28 11:16:28 2020
+* Created: Wed Sep 2 10:25:21 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.lvs.report
new file mode 100644
index 0000000..f8903b7
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_4.sp ('sky130_fd_sc_lp__o31ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_4.spice ('sky130_fd_sc_lp__o31ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_4 sky130_fd_sc_lp__o31ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 32 layout mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+ 32 source mos transistors were reduced to 8.
+ 24 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pex.spice
index 4ff4a21..eeee891 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_4.pex.spice
-* Created: Fri Aug 28 11:16:36 2020
+* Created: Wed Sep 2 10:25:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pxi.spice
index 32f1a24..869be21 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_4.pxi.spice
-* Created: Fri Aug 28 11:16:36 2020
+* Created: Wed Sep 2 10:25:28 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_4%A2 N_A2_M1004_g N_A2_M1012_g N_A2_M1007_g
+ N_A2_M1020_g N_A2_M1011_g N_A2_M1030_g N_A2_M1024_g N_A2_M1031_g N_A2_c_125_n
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.spice
index 8287213..cdab1b7 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_4.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_4.spice
-* Created: Fri Aug 28 11:16:36 2020
+* Created: Wed Sep 2 10:25:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.lvs.report
new file mode 100644
index 0000000..b04ba29
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_lp.sp ('sky130_fd_sc_lp__o31ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.spice ('sky130_fd_sc_lp__o31ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:32 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_lp sky130_fd_sc_lp__o31ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pex.spice
index fb86348..a1a1fe4 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_lp.pex.spice
-* Created: Fri Aug 28 11:16:45 2020
+* Created: Wed Sep 2 10:25:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pxi.spice
index c292b04..0655b8d 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_lp.pxi.spice
-* Created: Fri Aug 28 11:16:45 2020
+* Created: Wed Sep 2 10:25:35 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_LP%A1 N_A1_c_56_n N_A1_M1003_g N_A1_c_57_n
+ N_A1_M1000_g N_A1_c_58_n A1 A1 N_A1_c_59_n N_A1_c_60_n N_A1_c_61_n
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.spice
index 8a24387..3da87ec 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_lp.spice
-* Created: Fri Aug 28 11:16:45 2020
+* Created: Wed Sep 2 10:25:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.lvs.report b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.lvs.report
new file mode 100644
index 0000000..33c5b43
--- /dev/null
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o31ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o31ai_m.sp ('sky130_fd_sc_lp__o31ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o31ai/sky130_fd_sc_lp__o31ai_m.spice ('sky130_fd_sc_lp__o31ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o31ai_m sky130_fd_sc_lp__o31ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o31ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o31ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_1 (6 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pex.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pex.spice
index 8d66896..78acd8b 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pex.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_m.pex.spice
-* Created: Fri Aug 28 11:16:53 2020
+* Created: Wed Sep 2 10:25:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pxi.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pxi.spice
index 452ca88..143b13b 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pxi.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_m.pxi.spice
-* Created: Fri Aug 28 11:16:53 2020
+* Created: Wed Sep 2 10:25:43 2020
*
x_PM_SKY130_FD_SC_LP__O31AI_M%A1 N_A1_c_64_n N_A1_M1007_g N_A1_c_65_n
+ N_A1_M1002_g N_A1_c_60_n N_A1_c_61_n N_A1_c_66_n N_A1_c_67_n A1 A1 A1 A1
diff --git a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.spice b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.spice
index 2c82571..c3cff91 100644
--- a/cells/o31ai/sky130_fd_sc_lp__o31ai_m.spice
+++ b/cells/o31ai/sky130_fd_sc_lp__o31ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o31ai_m.spice
-* Created: Fri Aug 28 11:16:53 2020
+* Created: Wed Sep 2 10:25:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_0.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_0.lvs.report
new file mode 100644
index 0000000..90800c3
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_0.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_0.sp ('sky130_fd_sc_lp__o32a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_0.spice ('sky130_fd_sc_lp__o32a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:47 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_0 sky130_fd_sc_lp__o32a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_0.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_0.pex.spice
index df84071..d4684e2 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_0.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_0.pex.spice
-* Created: Fri Aug 28 11:17:05 2020
+* Created: Wed Sep 2 10:25:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_0.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_0.pxi.spice
index 45a7282..e3f313e 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_0.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_0.pxi.spice
-* Created: Fri Aug 28 11:17:05 2020
+* Created: Wed Sep 2 10:25:51 2020
*
x_PM_SKY130_FD_SC_LP__O32A_0%A_97_309# N_A_97_309#_M1007_d N_A_97_309#_M1002_d
+ N_A_97_309#_M1000_g N_A_97_309#_M1011_g N_A_97_309#_c_91_n N_A_97_309#_c_92_n
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_0.spice b/cells/o32a/sky130_fd_sc_lp__o32a_0.spice
index dec9473..4fa983c 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_0.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_0.spice
-* Created: Fri Aug 28 11:17:05 2020
+* Created: Wed Sep 2 10:25:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_1.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_1.lvs.report
new file mode 100644
index 0000000..7be3ecd
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_1.sp ('sky130_fd_sc_lp__o32a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_1.spice ('sky130_fd_sc_lp__o32a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:25:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_1 sky130_fd_sc_lp__o32a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_1.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_1.pex.spice
index bf65f17..3399f49 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_1.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_1.pex.spice
-* Created: Fri Aug 28 11:17:17 2020
+* Created: Wed Sep 2 10:25:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_1.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_1.pxi.spice
index 2903367..ee2a696 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_1.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_1.pxi.spice
-* Created: Fri Aug 28 11:17:17 2020
+* Created: Wed Sep 2 10:25:58 2020
*
x_PM_SKY130_FD_SC_LP__O32A_1%A_88_269# N_A_88_269#_M1000_d N_A_88_269#_M1007_d
+ N_A_88_269#_M1009_g N_A_88_269#_M1004_g N_A_88_269#_c_66_n N_A_88_269#_c_76_p
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_1.spice b/cells/o32a/sky130_fd_sc_lp__o32a_1.spice
index 18b80fa..0ee90c6 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_1.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_1.spice
-* Created: Fri Aug 28 11:17:17 2020
+* Created: Wed Sep 2 10:25:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_2.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_2.lvs.report
new file mode 100644
index 0000000..39fa9de
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_2.sp ('sky130_fd_sc_lp__o32a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_2.spice ('sky130_fd_sc_lp__o32a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_2 sky130_fd_sc_lp__o32a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_2.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_2.pex.spice
index ea3ce17..a7975c9 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_2.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_2.pex.spice
-* Created: Fri Aug 28 11:17:25 2020
+* Created: Wed Sep 2 10:26:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_2.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_2.pxi.spice
index b07a01c..a245e88 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_2.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_2.pxi.spice
-* Created: Fri Aug 28 11:17:25 2020
+* Created: Wed Sep 2 10:26:05 2020
*
x_PM_SKY130_FD_SC_LP__O32A_2%A_85_21# N_A_85_21#_M1009_d N_A_85_21#_M1005_d
+ N_A_85_21#_M1011_g N_A_85_21#_M1006_g N_A_85_21#_M1013_g N_A_85_21#_M1012_g
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_2.spice b/cells/o32a/sky130_fd_sc_lp__o32a_2.spice
index ff080d6..9f180fb 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_2.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_2.spice
-* Created: Fri Aug 28 11:17:25 2020
+* Created: Wed Sep 2 10:26:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_4.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_4.lvs.report
new file mode 100644
index 0000000..754b8fc
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_4.sp ('sky130_fd_sc_lp__o32a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_4.spice ('sky130_fd_sc_lp__o32a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_4 sky130_fd_sc_lp__o32a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A2 A1 A3 B2 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_4.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_4.pex.spice
index f06ea26..a25ccd6 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_4.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_4.pex.spice
-* Created: Fri Aug 28 11:17:33 2020
+* Created: Wed Sep 2 10:26:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_4.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_4.pxi.spice
index 9dc6a97..a05b4e1 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_4.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_4.pxi.spice
-* Created: Fri Aug 28 11:17:33 2020
+* Created: Wed Sep 2 10:26:11 2020
*
x_PM_SKY130_FD_SC_LP__O32A_4%A2 N_A2_M1012_g N_A2_M1013_g N_A2_M1018_g
+ N_A2_M1015_g N_A2_c_147_n N_A2_c_138_n N_A2_c_139_n N_A2_c_140_n A2 A2 A2
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_4.spice b/cells/o32a/sky130_fd_sc_lp__o32a_4.spice
index c496e59..a1a848a 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_4.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_4.spice
-* Created: Fri Aug 28 11:17:33 2020
+* Created: Wed Sep 2 10:26:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_lp.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_lp.lvs.report
new file mode 100644
index 0000000..52fd675
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_lp.sp ('sky130_fd_sc_lp__o32a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_lp.spice ('sky130_fd_sc_lp__o32a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_lp sky130_fd_sc_lp__o32a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_lp.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_lp.pex.spice
index bed320b..1f92138 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_lp.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_lp.pex.spice
-* Created: Fri Aug 28 11:17:41 2020
+* Created: Wed Sep 2 10:26:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_lp.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_lp.pxi.spice
index 1facd29..7b1ea4b 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_lp.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_lp.pxi.spice
-* Created: Fri Aug 28 11:17:41 2020
+* Created: Wed Sep 2 10:26:19 2020
*
x_PM_SKY130_FD_SC_LP__O32A_LP%B1 N_B1_c_78_n N_B1_c_83_n N_B1_M1005_g
+ N_B1_c_79_n N_B1_M1000_g N_B1_c_80_n N_B1_c_81_n B1 B1
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_lp.spice b/cells/o32a/sky130_fd_sc_lp__o32a_lp.spice
index bc8c50c..0d20814 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_lp.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_lp.spice
-* Created: Fri Aug 28 11:17:41 2020
+* Created: Wed Sep 2 10:26:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_m.lvs.report b/cells/o32a/sky130_fd_sc_lp__o32a_m.lvs.report
new file mode 100644
index 0000000..a54a80a
--- /dev/null
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_m.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32a_m.sp ('sky130_fd_sc_lp__o32a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32a/sky130_fd_sc_lp__o32a_m.spice ('sky130_fd_sc_lp__o32a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32a_m sky130_fd_sc_lp__o32a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o32a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 B2 B1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_m.pex.spice b/cells/o32a/sky130_fd_sc_lp__o32a_m.pex.spice
index 9513255..9744ad1 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_m.pex.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_m.pex.spice
-* Created: Fri Aug 28 11:17:51 2020
+* Created: Wed Sep 2 10:26:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_m.pxi.spice b/cells/o32a/sky130_fd_sc_lp__o32a_m.pxi.spice
index 518192a..78b9df7 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_m.pxi.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_m.pxi.spice
-* Created: Fri Aug 28 11:17:51 2020
+* Created: Wed Sep 2 10:26:26 2020
*
x_PM_SKY130_FD_SC_LP__O32A_M%A1 N_A1_c_77_n N_A1_M1009_g N_A1_M1000_g
+ N_A1_c_79_n A1 A1 A1 N_A1_c_81_n N_A1_c_82_n PM_SKY130_FD_SC_LP__O32A_M%A1
diff --git a/cells/o32a/sky130_fd_sc_lp__o32a_m.spice b/cells/o32a/sky130_fd_sc_lp__o32a_m.spice
index 29cd748..003aa62 100644
--- a/cells/o32a/sky130_fd_sc_lp__o32a_m.spice
+++ b/cells/o32a/sky130_fd_sc_lp__o32a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32a_m.spice
-* Created: Fri Aug 28 11:17:51 2020
+* Created: Wed Sep 2 10:26:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.lvs.report
new file mode 100644
index 0000000..15f309f
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_0.sp ('sky130_fd_sc_lp__o32ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_0.spice ('sky130_fd_sc_lp__o32ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_0 sky130_fd_sc_lp__o32ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pex.spice
index a9c7a55..58d7297 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_0.pex.spice
-* Created: Fri Aug 28 11:18:00 2020
+* Created: Wed Sep 2 10:26:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pxi.spice
index e4aa518..a2731af 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_0.pxi.spice
-* Created: Fri Aug 28 11:18:00 2020
+* Created: Wed Sep 2 10:26:34 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_0%B1 N_B1_c_66_n N_B1_M1003_g N_B1_c_67_n
+ N_B1_M1006_g B1 B1 B1 B1 PM_SKY130_FD_SC_LP__O32AI_0%B1
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.spice
index eae385f..8a46e1a 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_0.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_0.spice
-* Created: Fri Aug 28 11:18:00 2020
+* Created: Wed Sep 2 10:26:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.lvs.report
new file mode 100644
index 0000000..40c735d
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_1.sp ('sky130_fd_sc_lp__o32ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_1.spice ('sky130_fd_sc_lp__o32ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_1 sky130_fd_sc_lp__o32ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pex.spice
index c9ec41e..479ac0a 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_1.pex.spice
-* Created: Fri Aug 28 11:18:12 2020
+* Created: Wed Sep 2 10:26:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pxi.spice
index bef05ea..12b8e46 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_1.pxi.spice
-* Created: Fri Aug 28 11:18:12 2020
+* Created: Wed Sep 2 10:26:42 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_1%B1 N_B1_c_51_n N_B1_M1009_g N_B1_M1004_g B1 B1 B1
+ N_B1_c_54_n N_B1_c_55_n PM_SKY130_FD_SC_LP__O32AI_1%B1
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.spice
index 915fbdf..95dbd74 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_1.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_1.spice
-* Created: Fri Aug 28 11:18:12 2020
+* Created: Wed Sep 2 10:26:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.lvs.report
new file mode 100644
index 0000000..16752a5
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_2.sp ('sky130_fd_sc_lp__o32ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_2.spice ('sky130_fd_sc_lp__o32ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_2 sky130_fd_sc_lp__o32ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pex.spice
index 9b92c59..8eb7f99 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_2.pex.spice
-* Created: Fri Aug 28 11:18:25 2020
+* Created: Wed Sep 2 10:26:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pxi.spice
index ff2e53a..f58e016 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_2.pxi.spice
-* Created: Fri Aug 28 11:18:25 2020
+* Created: Wed Sep 2 10:26:49 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_2%B2 N_B2_M1004_g N_B2_M1005_g N_B2_M1019_g
+ N_B2_M1015_g B2 B2 B2 N_B2_c_91_n PM_SKY130_FD_SC_LP__O32AI_2%B2
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.spice
index a01433b..4ae164a 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_2.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_2.spice
-* Created: Fri Aug 28 11:18:25 2020
+* Created: Wed Sep 2 10:26:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.lvs.report
new file mode 100644
index 0000000..37e6157
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_4.sp ('sky130_fd_sc_lp__o32ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_4.spice ('sky130_fd_sc_lp__o32ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:26:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_4 sky130_fd_sc_lp__o32ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B2 B1 A3 A2 A1 Y VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pex.spice
index 3cb58da..feca636 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_4.pex.spice
-* Created: Fri Aug 28 11:18:33 2020
+* Created: Wed Sep 2 10:26:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pxi.spice
index 1733762..d6c986b 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_4.pxi.spice
-* Created: Fri Aug 28 11:18:33 2020
+* Created: Wed Sep 2 10:26:57 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_4%B2 N_B2_M1003_g N_B2_M1006_g N_B2_M1018_g
+ N_B2_M1014_g N_B2_M1020_g N_B2_M1025_g N_B2_M1027_g N_B2_M1028_g B2 B2 B2 B2
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.spice
index 3cb1278..4d1dafb 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_4.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_4.spice
-* Created: Fri Aug 28 11:18:33 2020
+* Created: Wed Sep 2 10:26:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.lvs.report
new file mode 100644
index 0000000..d20e40d
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_lp.sp ('sky130_fd_sc_lp__o32ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.spice ('sky130_fd_sc_lp__o32ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_lp sky130_fd_sc_lp__o32ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pex.spice
index 5fe03ae..6fd1c55 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_lp.pex.spice
-* Created: Fri Aug 28 11:18:42 2020
+* Created: Wed Sep 2 10:27:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pxi.spice
index 079287f..98d7199 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_lp.pxi.spice
-* Created: Fri Aug 28 11:18:42 2020
+* Created: Wed Sep 2 10:27:04 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_LP%B1 N_B1_M1008_g N_B1_M1009_g B1 N_B1_c_58_n
+ N_B1_c_59_n PM_SKY130_FD_SC_LP__O32AI_LP%B1
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.spice
index 47ddb97..1904c62 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_lp.spice
-* Created: Fri Aug 28 11:18:42 2020
+* Created: Wed Sep 2 10:27:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.lvs.report b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.lvs.report
new file mode 100644
index 0000000..af8a66a
--- /dev/null
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o32ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o32ai_m.sp ('sky130_fd_sc_lp__o32ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o32ai/sky130_fd_sc_lp__o32ai_m.spice ('sky130_fd_sc_lp__o32ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o32ai_m sky130_fd_sc_lp__o32ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o32ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o32ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_3_2 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_3_2
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 B2 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pex.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pex.spice
index ccb5235..4555d22 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pex.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_m.pex.spice
-* Created: Fri Aug 28 11:18:51 2020
+* Created: Wed Sep 2 10:27:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pxi.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pxi.spice
index 14d9352..59c613f 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pxi.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_m.pxi.spice
-* Created: Fri Aug 28 11:18:51 2020
+* Created: Wed Sep 2 10:27:11 2020
*
x_PM_SKY130_FD_SC_LP__O32AI_M%B1 N_B1_c_72_n N_B1_c_73_n N_B1_c_74_n N_B1_c_80_n
+ N_B1_c_81_n N_B1_c_75_n N_B1_M1007_g N_B1_M1001_g N_B1_c_76_n B1 B1 B1 B1 B1
diff --git a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.spice b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.spice
index 0278492..4caf800 100644
--- a/cells/o32ai/sky130_fd_sc_lp__o32ai_m.spice
+++ b/cells/o32ai/sky130_fd_sc_lp__o32ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o32ai_m.spice
-* Created: Fri Aug 28 11:18:51 2020
+* Created: Wed Sep 2 10:27:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_0.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_0.lvs.report
new file mode 100644
index 0000000..0aa8bbd
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_0.sp ('sky130_fd_sc_lp__o41a_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_0.spice ('sky130_fd_sc_lp__o41a_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_0 sky130_fd_sc_lp__o41a_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_0.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_0.pex.spice
index 11032b5..f551ce5 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_0.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_0.pex.spice
-* Created: Fri Aug 28 11:19:00 2020
+* Created: Wed Sep 2 10:27:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_0.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_0.pxi.spice
index 12d3248..83142c2 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_0.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_0.pxi.spice
-* Created: Fri Aug 28 11:19:00 2020
+* Created: Wed Sep 2 10:27:18 2020
*
x_PM_SKY130_FD_SC_LP__O41A_0%A_80_21# N_A_80_21#_M1007_s N_A_80_21#_M1005_d
+ N_A_80_21#_M1003_g N_A_80_21#_c_90_n N_A_80_21#_M1010_g N_A_80_21#_c_92_n
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_0.spice b/cells/o41a/sky130_fd_sc_lp__o41a_0.spice
index d5c7fe5..9acaa95 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_0.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_0.spice
-* Created: Fri Aug 28 11:19:00 2020
+* Created: Wed Sep 2 10:27:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_1.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_1.lvs.report
new file mode 100644
index 0000000..d1bdcc1
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_1.sp ('sky130_fd_sc_lp__o41a_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_1.spice ('sky130_fd_sc_lp__o41a_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:22 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_1 sky130_fd_sc_lp__o41a_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_1.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_1.pex.spice
index 6bf7b34..1f0f7c8 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_1.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_1.pex.spice
-* Created: Fri Aug 28 11:19:13 2020
+* Created: Wed Sep 2 10:27:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_1.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_1.pxi.spice
index 0bd9c18..91fcb64 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_1.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_1.pxi.spice
-* Created: Fri Aug 28 11:19:13 2020
+* Created: Wed Sep 2 10:27:26 2020
*
x_PM_SKY130_FD_SC_LP__O41A_1%A_155_23# N_A_155_23#_M1002_s N_A_155_23#_M1010_d
+ N_A_155_23#_c_68_n N_A_155_23#_M1001_g N_A_155_23#_M1008_g N_A_155_23#_c_70_n
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_1.spice b/cells/o41a/sky130_fd_sc_lp__o41a_1.spice
index bb57414..e5f5a41 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_1.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_1.spice
-* Created: Fri Aug 28 11:19:13 2020
+* Created: Wed Sep 2 10:27:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_2.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_2.lvs.report
new file mode 100644
index 0000000..b18e140
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_2.sp ('sky130_fd_sc_lp__o41a_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_2.spice ('sky130_fd_sc_lp__o41a_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:29 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_2 sky130_fd_sc_lp__o41a_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_2.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_2.pex.spice
index bdfcf67..93be1a7 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_2.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_2.pex.spice
-* Created: Fri Aug 28 11:19:25 2020
+* Created: Wed Sep 2 10:27:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_2.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_2.pxi.spice
index 23b467f..16f7612 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_2.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_2.pxi.spice
-* Created: Fri Aug 28 11:19:25 2020
+* Created: Wed Sep 2 10:27:33 2020
*
x_PM_SKY130_FD_SC_LP__O41A_2%A_102_53# N_A_102_53#_M1004_s N_A_102_53#_M1007_d
+ N_A_102_53#_c_74_n N_A_102_53#_M1000_g N_A_102_53#_M1003_g N_A_102_53#_c_75_n
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_2.spice b/cells/o41a/sky130_fd_sc_lp__o41a_2.spice
index f24cebc..d36aea1 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_2.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_2.spice
-* Created: Fri Aug 28 11:19:25 2020
+* Created: Wed Sep 2 10:27:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_4.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_4.lvs.report
new file mode 100644
index 0000000..c086db6
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_4.sp ('sky130_fd_sc_lp__o41a_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_4.spice ('sky130_fd_sc_lp__o41a_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_4 sky130_fd_sc_lp__o41a_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 28 layout mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+ 28 source mos transistors were reduced to 12.
+ 16 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_4.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_4.pex.spice
index 54a9833..29d91d5 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_4.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_4.pex.spice
-* Created: Fri Aug 28 11:19:34 2020
+* Created: Wed Sep 2 10:27:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_4.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_4.pxi.spice
index 22ce992..126e93c 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_4.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_4.pxi.spice
-* Created: Fri Aug 28 11:19:34 2020
+* Created: Wed Sep 2 10:27:41 2020
*
x_PM_SKY130_FD_SC_LP__O41A_4%A_83_23# N_A_83_23#_M1013_s N_A_83_23#_M1004_d
+ N_A_83_23#_M1002_d N_A_83_23#_M1000_g N_A_83_23#_M1006_g N_A_83_23#_M1010_g
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_4.spice b/cells/o41a/sky130_fd_sc_lp__o41a_4.spice
index b0ccc3b..ce74ef6 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_4.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_4.spice
-* Created: Fri Aug 28 11:19:34 2020
+* Created: Wed Sep 2 10:27:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_lp.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_lp.lvs.report
new file mode 100644
index 0000000..efe8d00
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_lp.sp ('sky130_fd_sc_lp__o41a_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_lp.spice ('sky130_fd_sc_lp__o41a_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_lp sky130_fd_sc_lp__o41a_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 16 16
+
+ Instances: 7 7 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 2 2 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A1 A2 A3 A4 B1 VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_lp.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_lp.pex.spice
index 7617858..cb6e6e2 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_lp.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_lp.pex.spice
-* Created: Fri Aug 28 11:19:43 2020
+* Created: Wed Sep 2 10:27:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_lp.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_lp.pxi.spice
index 60ac8f6..1c93b98 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_lp.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_lp.pxi.spice
-* Created: Fri Aug 28 11:19:43 2020
+* Created: Wed Sep 2 10:27:48 2020
*
x_PM_SKY130_FD_SC_LP__O41A_LP%A1 N_A1_M1008_g N_A1_M1002_g N_A1_c_88_n
+ N_A1_c_93_n A1 N_A1_c_89_n N_A1_c_90_n PM_SKY130_FD_SC_LP__O41A_LP%A1
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_lp.spice b/cells/o41a/sky130_fd_sc_lp__o41a_lp.spice
index 24d1870..2bee34e 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_lp.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_lp.spice
-* Created: Fri Aug 28 11:19:43 2020
+* Created: Wed Sep 2 10:27:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_m.lvs.report b/cells/o41a/sky130_fd_sc_lp__o41a_m.lvs.report
new file mode 100644
index 0000000..00365dd
--- /dev/null
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41a_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41a_m.sp ('sky130_fd_sc_lp__o41a_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41a/sky130_fd_sc_lp__o41a_m.spice ('sky130_fd_sc_lp__o41a_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:51 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41a_m sky130_fd_sc_lp__o41a_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41a_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o41a_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 11 11
+
+ Instances: 1 1 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_m.pex.spice b/cells/o41a/sky130_fd_sc_lp__o41a_m.pex.spice
index b0f82ca..0cefef0 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_m.pex.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_m.pex.spice
-* Created: Fri Aug 28 11:19:52 2020
+* Created: Wed Sep 2 10:27:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_m.pxi.spice b/cells/o41a/sky130_fd_sc_lp__o41a_m.pxi.spice
index 051d564..af6c632 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_m.pxi.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_m.pxi.spice
-* Created: Fri Aug 28 11:19:52 2020
+* Created: Wed Sep 2 10:27:55 2020
*
x_PM_SKY130_FD_SC_LP__O41A_M%A_80_21# N_A_80_21#_M1009_s N_A_80_21#_M1007_d
+ N_A_80_21#_M1006_g N_A_80_21#_c_92_n N_A_80_21#_M1002_g N_A_80_21#_c_94_n
diff --git a/cells/o41a/sky130_fd_sc_lp__o41a_m.spice b/cells/o41a/sky130_fd_sc_lp__o41a_m.spice
index 951f7c6..c751a67 100644
--- a/cells/o41a/sky130_fd_sc_lp__o41a_m.spice
+++ b/cells/o41a/sky130_fd_sc_lp__o41a_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41a_m.spice
-* Created: Fri Aug 28 11:19:52 2020
+* Created: Wed Sep 2 10:27:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.lvs.report
new file mode 100644
index 0000000..ec413c3
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_0.sp ('sky130_fd_sc_lp__o41ai_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_0.spice ('sky130_fd_sc_lp__o41ai_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:27:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_0 sky130_fd_sc_lp__o41ai_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_0
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pex.spice
index 21bf30b..1ff8714 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_0.pex.spice
-* Created: Fri Aug 28 11:20:01 2020
+* Created: Wed Sep 2 10:28:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pxi.spice
index 0a54fbf..fb50b0d 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_0.pxi.spice
-* Created: Fri Aug 28 11:20:01 2020
+* Created: Wed Sep 2 10:28:03 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_0%B1 N_B1_c_78_n N_B1_M1000_g N_B1_M1006_g
+ N_B1_c_79_n N_B1_c_80_n N_B1_c_86_n B1 B1 B1 N_B1_c_82_n N_B1_c_83_n
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.spice
index 8330a06..68058fa 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_0.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_0.spice
-* Created: Fri Aug 28 11:20:01 2020
+* Created: Wed Sep 2 10:28:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.lvs.report
new file mode 100644
index 0000000..a068967
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_1.sp ('sky130_fd_sc_lp__o41ai_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_1.spice ('sky130_fd_sc_lp__o41ai_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_1 sky130_fd_sc_lp__o41ai_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_1
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pex.spice
index 8de0a55..42de51b 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_1.pex.spice
-* Created: Fri Aug 28 11:20:13 2020
+* Created: Wed Sep 2 10:28:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pxi.spice
index aba7e50..7945e99 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_1.pxi.spice
-* Created: Fri Aug 28 11:20:13 2020
+* Created: Wed Sep 2 10:28:11 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_1%B1 N_B1_M1004_g N_B1_M1005_g N_B1_c_62_n
+ N_B1_c_63_n B1 N_B1_c_64_n PM_SKY130_FD_SC_LP__O41AI_1%B1
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.spice
index 25c739b..05d599f 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_1.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_1.spice
-* Created: Fri Aug 28 11:20:13 2020
+* Created: Wed Sep 2 10:28:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.lvs.report
new file mode 100644
index 0000000..47b666c
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_2.sp ('sky130_fd_sc_lp__o41ai_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_2.spice ('sky130_fd_sc_lp__o41ai_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_2 sky130_fd_sc_lp__o41ai_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_2
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pex.spice
index 961027c..2841a91 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_2.pex.spice
-* Created: Fri Aug 28 11:20:26 2020
+* Created: Wed Sep 2 10:28:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pxi.spice
index 63fb7f0..9400e5d 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_2.pxi.spice
-* Created: Fri Aug 28 11:20:26 2020
+* Created: Wed Sep 2 10:28:20 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_2%B1 N_B1_M1009_g N_B1_M1018_g N_B1_c_96_n
+ N_B1_M1007_g N_B1_c_97_n N_B1_M1008_g B1 B1 N_B1_c_98_n
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.spice
index 5971753..56c19a4 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_2.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_2.spice
-* Created: Fri Aug 28 11:20:26 2020
+* Created: Wed Sep 2 10:28:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.lvs.report
new file mode 100644
index 0000000..d196f45
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_4.sp ('sky130_fd_sc_lp__o41ai_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_4.spice ('sky130_fd_sc_lp__o41ai_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_4 sky130_fd_sc_lp__o41ai_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_4
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pex.spice
index a1e1fe5..82997da 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_4.pex.spice
-* Created: Fri Aug 28 11:20:35 2020
+* Created: Wed Sep 2 10:28:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pxi.spice
index ab2fe7e..e6b0661 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_4.pxi.spice
-* Created: Fri Aug 28 11:20:35 2020
+* Created: Wed Sep 2 10:28:27 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_4%B1 N_B1_M1004_g N_B1_M1010_g N_B1_M1006_g
+ N_B1_M1014_g N_B1_M1018_g N_B1_M1026_g N_B1_M1033_g N_B1_M1029_g B1 B1 B1 B1
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.spice
index 3d4912f..bbea8b8 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_4.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_4.spice
-* Created: Fri Aug 28 11:20:35 2020
+* Created: Wed Sep 2 10:28:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.lvs.report
new file mode 100644
index 0000000..3b2442b
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_lp.sp ('sky130_fd_sc_lp__o41ai_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.spice ('sky130_fd_sc_lp__o41ai_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_lp sky130_fd_sc_lp__o41ai_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pex.spice
index fedc8d9..99d25a2 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_lp.pex.spice
-* Created: Fri Aug 28 11:20:43 2020
+* Created: Wed Sep 2 10:28:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pxi.spice
index e197c29..e903c42 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_lp.pxi.spice
-* Created: Fri Aug 28 11:20:43 2020
+* Created: Wed Sep 2 10:28:35 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_LP%B1 N_B1_M1002_g N_B1_M1007_g N_B1_c_67_n
+ N_B1_c_68_n B1 B1 N_B1_c_69_n N_B1_c_70_n PM_SKY130_FD_SC_LP__O41AI_LP%B1
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.spice
index c598d34..be8164b 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_lp.spice
-* Created: Fri Aug 28 11:20:43 2020
+* Created: Wed Sep 2 10:28:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.lvs.report b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.lvs.report
new file mode 100644
index 0000000..c6ab58a
--- /dev/null
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__o41ai_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__o41ai_m.sp ('sky130_fd_sc_lp__o41ai_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/o41ai/sky130_fd_sc_lp__o41ai_m.spice ('sky130_fd_sc_lp__o41ai_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__o41ai_m sky130_fd_sc_lp__o41ai_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__o41ai_m
+SOURCE CELL NAME: sky130_fd_sc_lp__o41ai_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 14 14
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ 1 1 SPMN_4_1 (7 pins)
+ ------ ------
+ Total Inst: 3 3
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ 1 1 0 0 SPMN_4_1
+ ------- ------- --------- ---------
+ Total Inst: 3 3 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B1 A4 A3 A2 A1 VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pex.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pex.spice
index 864a044..1471b83 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pex.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_m.pex.spice
-* Created: Fri Aug 28 11:20:53 2020
+* Created: Wed Sep 2 10:28:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pxi.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pxi.spice
index 4adf92d..4347eb0 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pxi.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_m.pxi.spice
-* Created: Fri Aug 28 11:20:53 2020
+* Created: Wed Sep 2 10:28:42 2020
*
x_PM_SKY130_FD_SC_LP__O41AI_M%B1 N_B1_c_67_n N_B1_M1000_g N_B1_M1006_g
+ N_B1_c_69_n B1 B1 B1 N_B1_c_71_n N_B1_c_72_n PM_SKY130_FD_SC_LP__O41AI_M%B1
diff --git a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.spice b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.spice
index a3a1298..e45089f 100644
--- a/cells/o41ai/sky130_fd_sc_lp__o41ai_m.spice
+++ b/cells/o41ai/sky130_fd_sc_lp__o41ai_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__o41ai_m.spice
-* Created: Fri Aug 28 11:20:53 2020
+* Created: Wed Sep 2 10:28:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_0.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_0.lvs.report
new file mode 100644
index 0000000..17062b5
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_0.sp ('sky130_fd_sc_lp__or2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_0.spice ('sky130_fd_sc_lp__or2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_0 sky130_fd_sc_lp__or2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_0.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_0.pex.spice
index 3032357..21800f4 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_0.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_0.pex.spice
-* Created: Fri Aug 28 11:21:02 2020
+* Created: Wed Sep 2 10:28:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_0.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_0.pxi.spice
index 74955a8..d12e7ff 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_0.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_0.pxi.spice
-* Created: Fri Aug 28 11:21:02 2020
+* Created: Wed Sep 2 10:28:50 2020
*
x_PM_SKY130_FD_SC_LP__OR2_0%B N_B_M1002_g N_B_M1000_g N_B_c_53_n N_B_c_54_n B B
+ B B N_B_c_56_n PM_SKY130_FD_SC_LP__OR2_0%B
diff --git a/cells/or2/sky130_fd_sc_lp__or2_0.spice b/cells/or2/sky130_fd_sc_lp__or2_0.spice
index 236c58e..8661b6e 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_0.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_0.spice
-* Created: Fri Aug 28 11:21:02 2020
+* Created: Wed Sep 2 10:28:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_1.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_1.lvs.report
new file mode 100644
index 0000000..1269441
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_1.sp ('sky130_fd_sc_lp__or2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_1.spice ('sky130_fd_sc_lp__or2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:28:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_1 sky130_fd_sc_lp__or2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_1.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_1.pex.spice
index 4215500..96eeaf6 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_1.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_1.pex.spice
-* Created: Fri Aug 28 11:21:14 2020
+* Created: Wed Sep 2 10:28:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_1.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_1.pxi.spice
index 9006eb5..79cc4ae 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_1.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_1.pxi.spice
-* Created: Fri Aug 28 11:21:14 2020
+* Created: Wed Sep 2 10:28:57 2020
*
x_PM_SKY130_FD_SC_LP__OR2_1%B N_B_c_43_n N_B_c_44_n N_B_c_45_n N_B_M1001_g
+ N_B_c_49_n N_B_M1003_g B N_B_c_47_n PM_SKY130_FD_SC_LP__OR2_1%B
diff --git a/cells/or2/sky130_fd_sc_lp__or2_1.spice b/cells/or2/sky130_fd_sc_lp__or2_1.spice
index 6d4ca07..39a55f8 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_1.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_1.spice
-* Created: Fri Aug 28 11:21:14 2020
+* Created: Wed Sep 2 10:28:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_2.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_2.lvs.report
new file mode 100644
index 0000000..886b4df
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_2.sp ('sky130_fd_sc_lp__or2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_2.spice ('sky130_fd_sc_lp__or2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_2 sky130_fd_sc_lp__or2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_2.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_2.pex.spice
index 37e3306..33d0911 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_2.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_2.pex.spice
-* Created: Fri Aug 28 11:21:28 2020
+* Created: Wed Sep 2 10:29:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_2.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_2.pxi.spice
index b972cf2..6ce6a5e 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_2.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_2.pxi.spice
-* Created: Fri Aug 28 11:21:28 2020
+* Created: Wed Sep 2 10:29:05 2020
*
x_PM_SKY130_FD_SC_LP__OR2_2%B N_B_c_56_n N_B_M1004_g N_B_c_63_n N_B_M1000_g
+ N_B_c_58_n N_B_c_59_n N_B_c_64_n B B N_B_c_61_n PM_SKY130_FD_SC_LP__OR2_2%B
diff --git a/cells/or2/sky130_fd_sc_lp__or2_2.spice b/cells/or2/sky130_fd_sc_lp__or2_2.spice
index fba07fa..fe73a7d 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_2.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_2.spice
-* Created: Fri Aug 28 11:21:28 2020
+* Created: Wed Sep 2 10:29:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_4.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_4.lvs.report
new file mode 100644
index 0000000..60a6cdb
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_4.sp ('sky130_fd_sc_lp__or2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_4.spice ('sky130_fd_sc_lp__or2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_4 sky130_fd_sc_lp__or2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_4.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_4.pex.spice
index 9bb95f6..658d074 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_4.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_4.pex.spice
-* Created: Fri Aug 28 11:21:36 2020
+* Created: Wed Sep 2 10:29:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_4.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_4.pxi.spice
index e18db3d..27aaec9 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_4.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_4.pxi.spice
-* Created: Fri Aug 28 11:21:36 2020
+* Created: Wed Sep 2 10:29:12 2020
*
x_PM_SKY130_FD_SC_LP__OR2_4%B N_B_M1003_g N_B_M1011_g N_B_c_68_n N_B_c_69_n
+ N_B_c_70_n B B N_B_c_72_n PM_SKY130_FD_SC_LP__OR2_4%B
diff --git a/cells/or2/sky130_fd_sc_lp__or2_4.spice b/cells/or2/sky130_fd_sc_lp__or2_4.spice
index e642c48..57f4fac 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_4.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_4.spice
-* Created: Fri Aug 28 11:21:36 2020
+* Created: Wed Sep 2 10:29:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_lp.lvs.report
new file mode 100644
index 0000000..67fd5e6
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_lp.sp ('sky130_fd_sc_lp__or2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_lp.spice ('sky130_fd_sc_lp__or2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_lp sky130_fd_sc_lp__or2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_lp.pex.spice
index 2ae53e1..2d81364 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp.pex.spice
-* Created: Fri Aug 28 11:21:53 2020
+* Created: Wed Sep 2 10:29:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_lp.pxi.spice
index b03c53f..e5d74ac 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp.pxi.spice
-* Created: Fri Aug 28 11:21:53 2020
+* Created: Wed Sep 2 10:29:27 2020
*
x_PM_SKY130_FD_SC_LP__OR2_LP%A N_A_M1004_g N_A_M1006_g N_A_M1001_g N_A_c_58_n
+ N_A_c_62_n A A A N_A_c_60_n PM_SKY130_FD_SC_LP__OR2_LP%A
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp.spice b/cells/or2/sky130_fd_sc_lp__or2_lp.spice
index ef1461c..b6ca8c3 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp.spice
-* Created: Fri Aug 28 11:21:53 2020
+* Created: Wed Sep 2 10:29:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp2.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_lp2.lvs.report
new file mode 100644
index 0000000..42f493a
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp2.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_lp2.sp ('sky130_fd_sc_lp__or2_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_lp2.spice ('sky130_fd_sc_lp__or2_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_lp2 sky130_fd_sc_lp__or2_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 10 9
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 1 1 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp2.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_lp2.pex.spice
index 1d6e309..a91988d 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp2.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp2.pex.spice
-* Created: Fri Aug 28 11:21:44 2020
+* Created: Wed Sep 2 10:29:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp2.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_lp2.pxi.spice
index 6cc4983..71e8f91 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp2.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp2.pxi.spice
-* Created: Fri Aug 28 11:21:44 2020
+* Created: Wed Sep 2 10:29:19 2020
*
x_PM_SKY130_FD_SC_LP__OR2_LP2%B N_B_c_49_n N_B_M1007_g N_B_c_55_n N_B_c_56_n
+ N_B_M1008_g N_B_c_58_n N_B_M1001_g N_B_c_59_n B B B B B N_B_c_53_n
diff --git a/cells/or2/sky130_fd_sc_lp__or2_lp2.spice b/cells/or2/sky130_fd_sc_lp__or2_lp2.spice
index ccbb952..9389429 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_lp2.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_lp2.spice
-* Created: Fri Aug 28 11:21:44 2020
+* Created: Wed Sep 2 10:29:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2/sky130_fd_sc_lp__or2_m.lvs.report b/cells/or2/sky130_fd_sc_lp__or2_m.lvs.report
new file mode 100644
index 0000000..1d75adf
--- /dev/null
+++ b/cells/or2/sky130_fd_sc_lp__or2_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2_m.sp ('sky130_fd_sc_lp__or2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2/sky130_fd_sc_lp__or2_m.spice ('sky130_fd_sc_lp__or2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2_m sky130_fd_sc_lp__or2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 3 3 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 7 6
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 5 5
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 5 5 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2/sky130_fd_sc_lp__or2_m.pex.spice b/cells/or2/sky130_fd_sc_lp__or2_m.pex.spice
index b5d0340..54fb28a 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_m.pex.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_m.pex.spice
-* Created: Fri Aug 28 11:22:01 2020
+* Created: Wed Sep 2 10:29:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2/sky130_fd_sc_lp__or2_m.pxi.spice b/cells/or2/sky130_fd_sc_lp__or2_m.pxi.spice
index cbd8630..75afbd2 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_m.pxi.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_m.pxi.spice
-* Created: Fri Aug 28 11:22:01 2020
+* Created: Wed Sep 2 10:29:34 2020
*
x_PM_SKY130_FD_SC_LP__OR2_M%B N_B_c_42_n N_B_c_43_n N_B_M1001_g N_B_c_49_n
+ N_B_M1004_g N_B_c_44_n N_B_c_45_n N_B_c_50_n B B N_B_c_47_n
diff --git a/cells/or2/sky130_fd_sc_lp__or2_m.spice b/cells/or2/sky130_fd_sc_lp__or2_m.spice
index ce461d7..1b5cde1 100644
--- a/cells/or2/sky130_fd_sc_lp__or2_m.spice
+++ b/cells/or2/sky130_fd_sc_lp__or2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2_m.spice
-* Created: Fri Aug 28 11:22:01 2020
+* Created: Wed Sep 2 10:29:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_1.lvs.report b/cells/or2b/sky130_fd_sc_lp__or2b_1.lvs.report
new file mode 100644
index 0000000..fb5f370
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2b_1.sp ('sky130_fd_sc_lp__or2b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2b/sky130_fd_sc_lp__or2b_1.spice ('sky130_fd_sc_lp__or2b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2b_1 sky130_fd_sc_lp__or2b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or2b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_1.pex.spice b/cells/or2b/sky130_fd_sc_lp__or2b_1.pex.spice
index 8db40a4..8868105 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_1.pex.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_1.pex.spice
-* Created: Fri Aug 28 11:22:10 2020
+* Created: Wed Sep 2 10:29:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_1.pxi.spice b/cells/or2b/sky130_fd_sc_lp__or2b_1.pxi.spice
index 8aa7deb..b109eed 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_1.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_1.pxi.spice
-* Created: Fri Aug 28 11:22:10 2020
+* Created: Wed Sep 2 10:29:42 2020
*
x_PM_SKY130_FD_SC_LP__OR2B_1%B_N N_B_N_M1006_g N_B_N_c_66_n N_B_N_c_67_n
+ N_B_N_c_68_n N_B_N_M1000_g N_B_N_c_69_n B_N B_N B_N N_B_N_c_72_n
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_1.spice b/cells/or2b/sky130_fd_sc_lp__or2b_1.spice
index f88e018..2d8a253 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_1.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_1.spice
-* Created: Fri Aug 28 11:22:10 2020
+* Created: Wed Sep 2 10:29:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_2.lvs.report b/cells/or2b/sky130_fd_sc_lp__or2b_2.lvs.report
new file mode 100644
index 0000000..2de7f73
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2b_2.sp ('sky130_fd_sc_lp__or2b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2b/sky130_fd_sc_lp__or2b_2.spice ('sky130_fd_sc_lp__or2b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2b_2 sky130_fd_sc_lp__or2b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or2b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_2.pex.spice b/cells/or2b/sky130_fd_sc_lp__or2b_2.pex.spice
index e99cde0..8eacab4 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_2.pex.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_2.pex.spice
-* Created: Fri Aug 28 11:22:21 2020
+* Created: Wed Sep 2 10:29:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_2.pxi.spice b/cells/or2b/sky130_fd_sc_lp__or2b_2.pxi.spice
index 5baf5d2..a90f21d 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_2.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_2.pxi.spice
-* Created: Fri Aug 28 11:22:21 2020
+* Created: Wed Sep 2 10:29:50 2020
*
x_PM_SKY130_FD_SC_LP__OR2B_2%B_N N_B_N_M1001_g N_B_N_M1005_g N_B_N_c_57_n
+ N_B_N_c_58_n B_N N_B_N_c_59_n N_B_N_c_60_n PM_SKY130_FD_SC_LP__OR2B_2%B_N
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_2.spice b/cells/or2b/sky130_fd_sc_lp__or2b_2.spice
index 120ef76..c3a9260 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_2.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_2.spice
-* Created: Fri Aug 28 11:22:21 2020
+* Created: Wed Sep 2 10:29:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_4.lvs.report b/cells/or2b/sky130_fd_sc_lp__or2b_4.lvs.report
new file mode 100644
index 0000000..65d6443
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2b_4.sp ('sky130_fd_sc_lp__or2b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2b/sky130_fd_sc_lp__or2b_4.spice ('sky130_fd_sc_lp__or2b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:29:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2b_4 sky130_fd_sc_lp__or2b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or2b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_4.pex.spice b/cells/or2b/sky130_fd_sc_lp__or2b_4.pex.spice
index 89fef7c..27cf8ac 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_4.pex.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_4.pex.spice
-* Created: Fri Aug 28 11:22:34 2020
+* Created: Wed Sep 2 10:29:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_4.pxi.spice b/cells/or2b/sky130_fd_sc_lp__or2b_4.pxi.spice
index aaea709..d597c9f 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_4.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_4.pxi.spice
-* Created: Fri Aug 28 11:22:34 2020
+* Created: Wed Sep 2 10:29:57 2020
*
x_PM_SKY130_FD_SC_LP__OR2B_4%B_N N_B_N_M1008_g N_B_N_c_86_n N_B_N_c_87_n
+ N_B_N_c_88_n N_B_N_M1005_g N_B_N_c_89_n B_N B_N B_N B_N B_N N_B_N_c_91_n
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_4.spice b/cells/or2b/sky130_fd_sc_lp__or2b_4.spice
index 0aa1013..9dc3938 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_4.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_4.spice
-* Created: Fri Aug 28 11:22:34 2020
+* Created: Wed Sep 2 10:29:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_lp.lvs.report b/cells/or2b/sky130_fd_sc_lp__or2b_lp.lvs.report
new file mode 100644
index 0000000..8d0afa6
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2b_lp.sp ('sky130_fd_sc_lp__or2b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2b/sky130_fd_sc_lp__or2b_lp.spice ('sky130_fd_sc_lp__or2b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2b_lp sky130_fd_sc_lp__or2b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or2b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 2 2 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_lp.pex.spice b/cells/or2b/sky130_fd_sc_lp__or2b_lp.pex.spice
index 822dec7..b0a3422 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_lp.pex.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_lp.pex.spice
-* Created: Fri Aug 28 11:22:42 2020
+* Created: Wed Sep 2 10:30:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_lp.pxi.spice b/cells/or2b/sky130_fd_sc_lp__or2b_lp.pxi.spice
index 0f542a1..7f2653b 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_lp.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_lp.pxi.spice
-* Created: Fri Aug 28 11:22:42 2020
+* Created: Wed Sep 2 10:30:04 2020
*
x_PM_SKY130_FD_SC_LP__OR2B_LP%B_N N_B_N_M1006_g N_B_N_M1011_g N_B_N_M1002_g
+ N_B_N_c_71_n N_B_N_c_72_n B_N B_N N_B_N_c_74_n PM_SKY130_FD_SC_LP__OR2B_LP%B_N
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_lp.spice b/cells/or2b/sky130_fd_sc_lp__or2b_lp.spice
index c3a57a8..43ead89 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_lp.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_lp.spice
-* Created: Fri Aug 28 11:22:42 2020
+* Created: Wed Sep 2 10:30:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_m.lvs.report b/cells/or2b/sky130_fd_sc_lp__or2b_m.lvs.report
new file mode 100644
index 0000000..aa6172b
--- /dev/null
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or2b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or2b_m.sp ('sky130_fd_sc_lp__or2b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or2b/sky130_fd_sc_lp__or2b_m.spice ('sky130_fd_sc_lp__or2b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or2b_m sky130_fd_sc_lp__or2b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or2b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or2b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 10 10
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B_N A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_m.pex.spice b/cells/or2b/sky130_fd_sc_lp__or2b_m.pex.spice
index ccf510b..31d77b0 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_m.pex.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_m.pex.spice
-* Created: Fri Aug 28 11:22:49 2020
+* Created: Wed Sep 2 10:30:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_m.pxi.spice b/cells/or2b/sky130_fd_sc_lp__or2b_m.pxi.spice
index e73ff73..2457f0f 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_m.pxi.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_m.pxi.spice
-* Created: Fri Aug 28 11:22:49 2020
+* Created: Wed Sep 2 10:30:12 2020
*
x_PM_SKY130_FD_SC_LP__OR2B_M%B_N N_B_N_M1005_g N_B_N_c_68_n N_B_N_c_69_n
+ N_B_N_c_70_n N_B_N_M1002_g N_B_N_c_71_n N_B_N_c_72_n N_B_N_c_77_n B_N B_N B_N
diff --git a/cells/or2b/sky130_fd_sc_lp__or2b_m.spice b/cells/or2b/sky130_fd_sc_lp__or2b_m.spice
index f21b7e9..9b5646e 100644
--- a/cells/or2b/sky130_fd_sc_lp__or2b_m.spice
+++ b/cells/or2b/sky130_fd_sc_lp__or2b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or2b_m.spice
-* Created: Fri Aug 28 11:22:49 2020
+* Created: Wed Sep 2 10:30:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_0.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_0.lvs.report
new file mode 100644
index 0000000..e4be74b
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_0.sp ('sky130_fd_sc_lp__or3_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_0.spice ('sky130_fd_sc_lp__or3_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_0 sky130_fd_sc_lp__or3_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_0
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_0.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_0.pex.spice
index 5961da1..94885b0 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_0.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_0.pex.spice
-* Created: Fri Aug 28 11:22:58 2020
+* Created: Wed Sep 2 10:30:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_0.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_0.pxi.spice
index 4ad2007..d4e61fe 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_0.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_0.pxi.spice
-* Created: Fri Aug 28 11:22:58 2020
+* Created: Wed Sep 2 10:30:20 2020
*
x_PM_SKY130_FD_SC_LP__OR3_0%C N_C_M1001_g N_C_M1000_g N_C_c_64_n N_C_c_69_n C C
+ C N_C_c_66_n PM_SKY130_FD_SC_LP__OR3_0%C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_0.spice b/cells/or3/sky130_fd_sc_lp__or3_0.spice
index adaf41e..dc132a8 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_0.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_0.spice
-* Created: Fri Aug 28 11:22:58 2020
+* Created: Wed Sep 2 10:30:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_1.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_1.lvs.report
new file mode 100644
index 0000000..0b17b9a
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_1.sp ('sky130_fd_sc_lp__or3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_1.spice ('sky130_fd_sc_lp__or3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_1 sky130_fd_sc_lp__or3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_1.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_1.pex.spice
index af80494..3be0bdc 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_1.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_1.pex.spice
-* Created: Fri Aug 28 11:23:06 2020
+* Created: Wed Sep 2 10:30:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_1.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_1.pxi.spice
index 0cc326b..24429e3 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_1.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_1.pxi.spice
-* Created: Fri Aug 28 11:23:06 2020
+* Created: Wed Sep 2 10:30:27 2020
*
x_PM_SKY130_FD_SC_LP__OR3_1%C N_C_c_56_n N_C_M1007_g N_C_M1003_g N_C_c_59_n C C
+ C N_C_c_61_n PM_SKY130_FD_SC_LP__OR3_1%C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_1.spice b/cells/or3/sky130_fd_sc_lp__or3_1.spice
index 0761293..7a4bc31 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_1.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_1.spice
-* Created: Fri Aug 28 11:23:06 2020
+* Created: Wed Sep 2 10:30:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_2.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_2.lvs.report
new file mode 100644
index 0000000..8f31ce8
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_2.sp ('sky130_fd_sc_lp__or3_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_2.spice ('sky130_fd_sc_lp__or3_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_2 sky130_fd_sc_lp__or3_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_2.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_2.pex.spice
index 436e84e..eac382d 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_2.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_2.pex.spice
-* Created: Fri Aug 28 11:23:15 2020
+* Created: Wed Sep 2 10:30:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_2.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_2.pxi.spice
index 38b65c3..24e75b5 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_2.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_2.pxi.spice
-* Created: Fri Aug 28 11:23:15 2020
+* Created: Wed Sep 2 10:30:34 2020
*
x_PM_SKY130_FD_SC_LP__OR3_2%C N_C_M1006_g N_C_M1009_g C C C N_C_c_64_n
+ PM_SKY130_FD_SC_LP__OR3_2%C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_2.spice b/cells/or3/sky130_fd_sc_lp__or3_2.spice
index 76538dc..d8f838e 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_2.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_2.spice
-* Created: Fri Aug 28 11:23:15 2020
+* Created: Wed Sep 2 10:30:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_4.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_4.lvs.report
new file mode 100644
index 0000000..98930ed
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_4.sp ('sky130_fd_sc_lp__or3_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_4.spice ('sky130_fd_sc_lp__or3_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_4 sky130_fd_sc_lp__or3_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_4.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_4.pex.spice
index b6cdd0c..6311ea5 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_4.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_4.pex.spice
-* Created: Fri Aug 28 11:23:26 2020
+* Created: Wed Sep 2 10:30:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_4.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_4.pxi.spice
index e433453..10c10d4 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_4.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_4.pxi.spice
-* Created: Fri Aug 28 11:23:26 2020
+* Created: Wed Sep 2 10:30:41 2020
*
x_PM_SKY130_FD_SC_LP__OR3_4%C N_C_M1001_g N_C_M1000_g C C N_C_c_82_n
+ PM_SKY130_FD_SC_LP__OR3_4%C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_4.spice b/cells/or3/sky130_fd_sc_lp__or3_4.spice
index d9ef7b1..6444feb 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_4.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_4.spice
-* Created: Fri Aug 28 11:23:26 2020
+* Created: Wed Sep 2 10:30:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_lp.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_lp.lvs.report
new file mode 100644
index 0000000..9d21f0d
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_lp.sp ('sky130_fd_sc_lp__or3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_lp.spice ('sky130_fd_sc_lp__or3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_lp sky130_fd_sc_lp__or3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 1 1 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_lp.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_lp.pex.spice
index eb7d623..c3df1f4 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_lp.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_lp.pex.spice
-* Created: Fri Aug 28 11:23:39 2020
+* Created: Wed Sep 2 10:30:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_lp.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_lp.pxi.spice
index d9660f5..a055163 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_lp.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_lp.pxi.spice
-* Created: Fri Aug 28 11:23:39 2020
+* Created: Wed Sep 2 10:30:49 2020
*
x_PM_SKY130_FD_SC_LP__OR3_LP%A_108_31# N_A_108_31#_M1010_d N_A_108_31#_M1004_d
+ N_A_108_31#_M1006_d N_A_108_31#_M1008_g N_A_108_31#_c_76_n N_A_108_31#_c_77_n
diff --git a/cells/or3/sky130_fd_sc_lp__or3_lp.spice b/cells/or3/sky130_fd_sc_lp__or3_lp.spice
index 974f4ef..0e3230d 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_lp.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_lp.spice
-* Created: Fri Aug 28 11:23:39 2020
+* Created: Wed Sep 2 10:30:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3/sky130_fd_sc_lp__or3_m.lvs.report b/cells/or3/sky130_fd_sc_lp__or3_m.lvs.report
new file mode 100644
index 0000000..ecc5e4d
--- /dev/null
+++ b/cells/or3/sky130_fd_sc_lp__or3_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3_m.sp ('sky130_fd_sc_lp__or3_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3/sky130_fd_sc_lp__or3_m.spice ('sky130_fd_sc_lp__or3_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:30:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3_m sky130_fd_sc_lp__or3_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or3_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 11 11
+
+ Instances: 4 4 MN (4 pins)
+ 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 9 8
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 9 9
+
+ Instances: 4 4 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 9 9 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3/sky130_fd_sc_lp__or3_m.pex.spice b/cells/or3/sky130_fd_sc_lp__or3_m.pex.spice
index 70548d6..804a127 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_m.pex.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_m.pex.spice
-* Created: Fri Aug 28 11:23:47 2020
+* Created: Wed Sep 2 10:30:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3/sky130_fd_sc_lp__or3_m.pxi.spice b/cells/or3/sky130_fd_sc_lp__or3_m.pxi.spice
index 4b656e8..9d2bec0 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_m.pxi.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_m.pxi.spice
-* Created: Fri Aug 28 11:23:47 2020
+* Created: Wed Sep 2 10:30:56 2020
*
x_PM_SKY130_FD_SC_LP__OR3_M%C N_C_M1002_g N_C_c_62_n N_C_c_63_n N_C_c_69_n
+ N_C_c_70_n N_C_M1005_g N_C_c_64_n C C C N_C_c_66_n N_C_c_67_n
diff --git a/cells/or3/sky130_fd_sc_lp__or3_m.spice b/cells/or3/sky130_fd_sc_lp__or3_m.spice
index 709a173..acfbfc1 100644
--- a/cells/or3/sky130_fd_sc_lp__or3_m.spice
+++ b/cells/or3/sky130_fd_sc_lp__or3_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3_m.spice
-* Created: Fri Aug 28 11:23:47 2020
+* Created: Wed Sep 2 10:30:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_1.lvs.report b/cells/or3b/sky130_fd_sc_lp__or3b_1.lvs.report
new file mode 100644
index 0000000..0a9d192
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3b_1.sp ('sky130_fd_sc_lp__or3b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3b/sky130_fd_sc_lp__or3b_1.spice ('sky130_fd_sc_lp__or3b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3b_1 sky130_fd_sc_lp__or3b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or3b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_1.pex.spice b/cells/or3b/sky130_fd_sc_lp__or3b_1.pex.spice
index 18b2e50..1bb0162 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_1.pex.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_1.pex.spice
-* Created: Fri Aug 28 11:23:55 2020
+* Created: Wed Sep 2 10:31:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_1.pxi.spice b/cells/or3b/sky130_fd_sc_lp__or3b_1.pxi.spice
index 02bfe24..7de64e0 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_1.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_1.pxi.spice
-* Created: Fri Aug 28 11:23:55 2020
+* Created: Wed Sep 2 10:31:04 2020
*
x_PM_SKY130_FD_SC_LP__OR3B_1%C_N N_C_N_c_68_n N_C_N_M1003_g N_C_N_M1006_g
+ N_C_N_c_70_n C_N C_N C_N C_N C_N N_C_N_c_72_n N_C_N_c_73_n
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_1.spice b/cells/or3b/sky130_fd_sc_lp__or3b_1.spice
index ae93b16..41e1df9 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_1.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_1.spice
-* Created: Fri Aug 28 11:23:55 2020
+* Created: Wed Sep 2 10:31:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_2.lvs.report b/cells/or3b/sky130_fd_sc_lp__or3b_2.lvs.report
new file mode 100644
index 0000000..fd728a9
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3b_2.sp ('sky130_fd_sc_lp__or3b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3b/sky130_fd_sc_lp__or3b_2.spice ('sky130_fd_sc_lp__or3b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3b_2 sky130_fd_sc_lp__or3b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or3b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_2.pex.spice b/cells/or3b/sky130_fd_sc_lp__or3b_2.pex.spice
index 1a339f0..b497c23 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_2.pex.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_2.pex.spice
-* Created: Fri Aug 28 11:24:04 2020
+* Created: Wed Sep 2 10:31:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_2.pxi.spice b/cells/or3b/sky130_fd_sc_lp__or3b_2.pxi.spice
index 1a3bc1e..de18569 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_2.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_2.pxi.spice
-* Created: Fri Aug 28 11:24:04 2020
+* Created: Wed Sep 2 10:31:12 2020
*
x_PM_SKY130_FD_SC_LP__OR3B_2%C_N N_C_N_M1004_g N_C_N_c_78_n N_C_N_M1002_g C_N
+ N_C_N_c_76_n N_C_N_c_77_n PM_SKY130_FD_SC_LP__OR3B_2%C_N
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_2.spice b/cells/or3b/sky130_fd_sc_lp__or3b_2.spice
index dc51a5e..3df51ef 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_2.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_2.spice
-* Created: Fri Aug 28 11:24:04 2020
+* Created: Wed Sep 2 10:31:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_4.lvs.report b/cells/or3b/sky130_fd_sc_lp__or3b_4.lvs.report
new file mode 100644
index 0000000..834d642
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3b_4.sp ('sky130_fd_sc_lp__or3b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3b/sky130_fd_sc_lp__or3b_4.spice ('sky130_fd_sc_lp__or3b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3b_4 sky130_fd_sc_lp__or3b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or3b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_4.pex.spice b/cells/or3b/sky130_fd_sc_lp__or3b_4.pex.spice
index aa71d78..92242ca 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_4.pex.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_4.pex.spice
-* Created: Fri Aug 28 11:24:12 2020
+* Created: Wed Sep 2 10:31:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_4.pxi.spice b/cells/or3b/sky130_fd_sc_lp__or3b_4.pxi.spice
index d2af3c8..aea37fd 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_4.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_4.pxi.spice
-* Created: Fri Aug 28 11:24:12 2020
+* Created: Wed Sep 2 10:31:19 2020
*
x_PM_SKY130_FD_SC_LP__OR3B_4%C_N N_C_N_M1015_g N_C_N_M1014_g C_N C_N C_N C_N C_N
+ N_C_N_c_87_n N_C_N_c_88_n PM_SKY130_FD_SC_LP__OR3B_4%C_N
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_4.spice b/cells/or3b/sky130_fd_sc_lp__or3b_4.spice
index 03ce2a7..36d6162 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_4.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_4.spice
-* Created: Fri Aug 28 11:24:12 2020
+* Created: Wed Sep 2 10:31:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_lp.lvs.report b/cells/or3b/sky130_fd_sc_lp__or3b_lp.lvs.report
new file mode 100644
index 0000000..5253ebb
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3b_lp.sp ('sky130_fd_sc_lp__or3b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3b/sky130_fd_sc_lp__or3b_lp.spice ('sky130_fd_sc_lp__or3b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3b_lp sky130_fd_sc_lp__or3b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or3b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 17 17
+
+ Instances: 10 10 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 2 2 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_lp.pex.spice b/cells/or3b/sky130_fd_sc_lp__or3b_lp.pex.spice
index b7c9836..548d763 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_lp.pex.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_lp.pex.spice
-* Created: Fri Aug 28 11:24:20 2020
+* Created: Wed Sep 2 10:31:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_lp.pxi.spice b/cells/or3b/sky130_fd_sc_lp__or3b_lp.pxi.spice
index 30af486..a183103 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_lp.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_lp.pxi.spice
-* Created: Fri Aug 28 11:24:20 2020
+* Created: Wed Sep 2 10:31:27 2020
*
x_PM_SKY130_FD_SC_LP__OR3B_LP%C_N N_C_N_c_98_n N_C_N_M1002_g N_C_N_c_99_n
+ N_C_N_M1001_g N_C_N_c_100_n N_C_N_c_101_n N_C_N_M1014_g N_C_N_c_102_n
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_lp.spice b/cells/or3b/sky130_fd_sc_lp__or3b_lp.spice
index 45997dc..2035404 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_lp.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_lp.spice
-* Created: Fri Aug 28 11:24:20 2020
+* Created: Wed Sep 2 10:31:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_m.lvs.report b/cells/or3b/sky130_fd_sc_lp__or3b_m.lvs.report
new file mode 100644
index 0000000..4b06002
--- /dev/null
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or3b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or3b_m.sp ('sky130_fd_sc_lp__or3b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or3b/sky130_fd_sc_lp__or3b_m.spice ('sky130_fd_sc_lp__or3b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or3b_m sky130_fd_sc_lp__or3b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or3b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or3b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 12 12
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP3 (5 pins)
+ ------ ------
+ Total Inst: 8 8
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP3
+ ------- ------- --------- ---------
+ Total Inst: 8 8 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_m.pex.spice b/cells/or3b/sky130_fd_sc_lp__or3b_m.pex.spice
index 1ad97f6..fe987b7 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_m.pex.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_m.pex.spice
-* Created: Fri Aug 28 11:24:32 2020
+* Created: Wed Sep 2 10:31:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_m.pxi.spice b/cells/or3b/sky130_fd_sc_lp__or3b_m.pxi.spice
index 2e4d77c..e3571ba 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_m.pxi.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_m.pxi.spice
-* Created: Fri Aug 28 11:24:32 2020
+* Created: Wed Sep 2 10:31:34 2020
*
x_PM_SKY130_FD_SC_LP__OR3B_M%C_N N_C_N_c_80_n N_C_N_M1000_g N_C_N_M1005_g
+ N_C_N_c_82_n N_C_N_c_83_n N_C_N_c_88_n C_N C_N C_N C_N C_N N_C_N_c_85_n
diff --git a/cells/or3b/sky130_fd_sc_lp__or3b_m.spice b/cells/or3b/sky130_fd_sc_lp__or3b_m.spice
index 50acc49..72f56c7 100644
--- a/cells/or3b/sky130_fd_sc_lp__or3b_m.spice
+++ b/cells/or3b/sky130_fd_sc_lp__or3b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or3b_m.spice
-* Created: Fri Aug 28 11:24:32 2020
+* Created: Wed Sep 2 10:31:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_0.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_0.lvs.report
new file mode 100644
index 0000000..f1f2d4a
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_0.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_0.sp ('sky130_fd_sc_lp__or4_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_0.spice ('sky130_fd_sc_lp__or4_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_0 sky130_fd_sc_lp__or4_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_0
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_0.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_0.pex.spice
index 7302b17..090814d 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_0.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_0.pex.spice
-* Created: Fri Aug 28 11:24:45 2020
+* Created: Wed Sep 2 10:31:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_0.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_0.pxi.spice
index b2a5e3a..86fe149 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_0.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_0.pxi.spice
-* Created: Fri Aug 28 11:24:45 2020
+* Created: Wed Sep 2 10:31:42 2020
*
x_PM_SKY130_FD_SC_LP__OR4_0%D N_D_M1000_g N_D_c_70_n N_D_M1005_g D D D D
+ PM_SKY130_FD_SC_LP__OR4_0%D
diff --git a/cells/or4/sky130_fd_sc_lp__or4_0.spice b/cells/or4/sky130_fd_sc_lp__or4_0.spice
index 48b7350..f0f61ec 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_0.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_0.spice
-* Created: Fri Aug 28 11:24:45 2020
+* Created: Wed Sep 2 10:31:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_1.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_1.lvs.report
new file mode 100644
index 0000000..049a0e8
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_1.sp ('sky130_fd_sc_lp__or4_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_1.spice ('sky130_fd_sc_lp__or4_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_1 sky130_fd_sc_lp__or4_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_1.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_1.pex.spice
index 67f0546..0835ef5 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_1.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_1.pex.spice
-* Created: Fri Aug 28 11:24:53 2020
+* Created: Wed Sep 2 10:31:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_1.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_1.pxi.spice
index 7bbc9eb..e111b78 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_1.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_1.pxi.spice
-* Created: Fri Aug 28 11:24:53 2020
+* Created: Wed Sep 2 10:31:49 2020
*
x_PM_SKY130_FD_SC_LP__OR4_1%D N_D_M1003_g N_D_M1006_g D D D N_D_c_67_n
+ PM_SKY130_FD_SC_LP__OR4_1%D
diff --git a/cells/or4/sky130_fd_sc_lp__or4_1.spice b/cells/or4/sky130_fd_sc_lp__or4_1.spice
index 0b00638..69d4e18 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_1.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_1.spice
-* Created: Fri Aug 28 11:24:53 2020
+* Created: Wed Sep 2 10:31:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_2.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_2.lvs.report
new file mode 100644
index 0000000..54c689d
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_2.sp ('sky130_fd_sc_lp__or4_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_2.spice ('sky130_fd_sc_lp__or4_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:31:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_2 sky130_fd_sc_lp__or4_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_2.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_2.pex.spice
index 21d3345..3eeb261 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_2.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_2.pex.spice
-* Created: Fri Aug 28 11:25:01 2020
+* Created: Wed Sep 2 10:31:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_2.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_2.pxi.spice
index 74353f1..881697b 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_2.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_2.pxi.spice
-* Created: Fri Aug 28 11:25:01 2020
+* Created: Wed Sep 2 10:31:56 2020
*
x_PM_SKY130_FD_SC_LP__OR4_2%D N_D_c_79_n N_D_c_80_n N_D_c_81_n N_D_c_82_n
+ N_D_M1010_g N_D_M1008_g D D D N_D_c_86_n PM_SKY130_FD_SC_LP__OR4_2%D
diff --git a/cells/or4/sky130_fd_sc_lp__or4_2.spice b/cells/or4/sky130_fd_sc_lp__or4_2.spice
index e64c4b2..96f7f1b 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_2.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_2.spice
-* Created: Fri Aug 28 11:25:01 2020
+* Created: Wed Sep 2 10:31:56 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_4.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_4.lvs.report
new file mode 100644
index 0000000..219a19e
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_4.sp ('sky130_fd_sc_lp__or4_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_4.spice ('sky130_fd_sc_lp__or4_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:00 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_4 sky130_fd_sc_lp__or4_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_4.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_4.pex.spice
index e242032..33e4636 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_4.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_4.pex.spice
-* Created: Fri Aug 28 11:25:10 2020
+* Created: Wed Sep 2 10:32:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_4.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_4.pxi.spice
index b81fc7d..44b0d47 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_4.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_4.pxi.spice
-* Created: Fri Aug 28 11:25:10 2020
+* Created: Wed Sep 2 10:32:04 2020
*
x_PM_SKY130_FD_SC_LP__OR4_4%D N_D_c_87_n N_D_M1004_g N_D_M1000_g N_D_c_89_n
+ N_D_c_90_n D D PM_SKY130_FD_SC_LP__OR4_4%D
diff --git a/cells/or4/sky130_fd_sc_lp__or4_4.spice b/cells/or4/sky130_fd_sc_lp__or4_4.spice
index e5b35e6..af327cb 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_4.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_4.spice
-* Created: Fri Aug 28 11:25:10 2020
+* Created: Wed Sep 2 10:32:04 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_lp.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_lp.lvs.report
new file mode 100644
index 0000000..0729250
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_lp.sp ('sky130_fd_sc_lp__or4_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_lp.spice ('sky130_fd_sc_lp__or4_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_lp sky130_fd_sc_lp__or4_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 18 18
+
+ Instances: 10 10 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 16 15
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 1 1 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_lp.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_lp.pex.spice
index c0b58ad..0c6646a 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_lp.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_lp.pex.spice
-* Created: Fri Aug 28 11:25:18 2020
+* Created: Wed Sep 2 10:32:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_lp.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_lp.pxi.spice
index 9e1073e..27f3895 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_lp.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_lp.pxi.spice
-* Created: Fri Aug 28 11:25:18 2020
+* Created: Wed Sep 2 10:32:11 2020
*
x_PM_SKY130_FD_SC_LP__OR4_LP%D N_D_c_88_n N_D_M1004_g N_D_c_89_n N_D_M1001_g
+ N_D_c_91_n N_D_c_92_n N_D_M1014_g N_D_c_93_n N_D_c_94_n D N_D_c_95_n
diff --git a/cells/or4/sky130_fd_sc_lp__or4_lp.spice b/cells/or4/sky130_fd_sc_lp__or4_lp.spice
index 5324779..cb59d16 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_lp.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_lp.spice
-* Created: Fri Aug 28 11:25:18 2020
+* Created: Wed Sep 2 10:32:11 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4/sky130_fd_sc_lp__or4_m.lvs.report b/cells/or4/sky130_fd_sc_lp__or4_m.lvs.report
new file mode 100644
index 0000000..240796c
--- /dev/null
+++ b/cells/or4/sky130_fd_sc_lp__or4_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4_m.sp ('sky130_fd_sc_lp__or4_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4/sky130_fd_sc_lp__or4_m.spice ('sky130_fd_sc_lp__or4_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4_m sky130_fd_sc_lp__or4_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or4_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 13 13
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 10 10
+
+ Instances: 5 5 MN (4 pins)
+ 1 1 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 7 7
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 10 10 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 1 1 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 7 7 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4/sky130_fd_sc_lp__or4_m.pex.spice b/cells/or4/sky130_fd_sc_lp__or4_m.pex.spice
index 172b678..b2d308f 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_m.pex.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_m.pex.spice
-* Created: Fri Aug 28 11:25:26 2020
+* Created: Wed Sep 2 10:32:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4/sky130_fd_sc_lp__or4_m.pxi.spice b/cells/or4/sky130_fd_sc_lp__or4_m.pxi.spice
index fc815b4..8c07c55 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_m.pxi.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_m.pxi.spice
-* Created: Fri Aug 28 11:25:26 2020
+* Created: Wed Sep 2 10:32:19 2020
*
x_PM_SKY130_FD_SC_LP__OR4_M%D N_D_c_72_n N_D_M1006_g N_D_M1003_g N_D_c_68_n
+ N_D_c_69_n D D D D D N_D_c_71_n PM_SKY130_FD_SC_LP__OR4_M%D
diff --git a/cells/or4/sky130_fd_sc_lp__or4_m.spice b/cells/or4/sky130_fd_sc_lp__or4_m.spice
index eb2406d..c525075 100644
--- a/cells/or4/sky130_fd_sc_lp__or4_m.spice
+++ b/cells/or4/sky130_fd_sc_lp__or4_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4_m.spice
-* Created: Fri Aug 28 11:25:26 2020
+* Created: Wed Sep 2 10:32:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_1.lvs.report b/cells/or4b/sky130_fd_sc_lp__or4b_1.lvs.report
new file mode 100644
index 0000000..0f3330b
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4b_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4b_1.sp ('sky130_fd_sc_lp__or4b_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4b/sky130_fd_sc_lp__or4b_1.spice ('sky130_fd_sc_lp__or4b_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4b_1 sky130_fd_sc_lp__or4b_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4b_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or4b_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_1.pex.spice b/cells/or4b/sky130_fd_sc_lp__or4b_1.pex.spice
index d2d32d8..efc5dd9 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_1.pex.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_1.pex.spice
-* Created: Fri Aug 28 11:25:38 2020
+* Created: Wed Sep 2 10:32:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_1.pxi.spice b/cells/or4b/sky130_fd_sc_lp__or4b_1.pxi.spice
index 37a19d7..91acded 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_1.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_1.pxi.spice
-* Created: Fri Aug 28 11:25:38 2020
+* Created: Wed Sep 2 10:32:27 2020
*
x_PM_SKY130_FD_SC_LP__OR4B_1%D_N N_D_N_M1006_g N_D_N_M1005_g D_N D_N
+ N_D_N_c_72_n PM_SKY130_FD_SC_LP__OR4B_1%D_N
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_1.spice b/cells/or4b/sky130_fd_sc_lp__or4b_1.spice
index e500bd2..aa148b7 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_1.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_1.spice
-* Created: Fri Aug 28 11:25:38 2020
+* Created: Wed Sep 2 10:32:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_2.lvs.report b/cells/or4b/sky130_fd_sc_lp__or4b_2.lvs.report
new file mode 100644
index 0000000..9dd3598
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4b_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4b_2.sp ('sky130_fd_sc_lp__or4b_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4b/sky130_fd_sc_lp__or4b_2.spice ('sky130_fd_sc_lp__or4b_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4b_2 sky130_fd_sc_lp__or4b_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4b_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or4b_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_2.pex.spice b/cells/or4b/sky130_fd_sc_lp__or4b_2.pex.spice
index 20262e1..94adb15 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_2.pex.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_2.pex.spice
-* Created: Fri Aug 28 11:25:51 2020
+* Created: Wed Sep 2 10:32:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_2.pxi.spice b/cells/or4b/sky130_fd_sc_lp__or4b_2.pxi.spice
index 3bb61ca..afdc11c 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_2.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_2.pxi.spice
-* Created: Fri Aug 28 11:25:51 2020
+* Created: Wed Sep 2 10:32:34 2020
*
x_PM_SKY130_FD_SC_LP__OR4B_2%D_N N_D_N_M1012_g N_D_N_M1008_g D_N N_D_N_c_82_n
+ N_D_N_c_83_n PM_SKY130_FD_SC_LP__OR4B_2%D_N
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_2.spice b/cells/or4b/sky130_fd_sc_lp__or4b_2.spice
index d734df1..647533c 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_2.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_2.spice
-* Created: Fri Aug 28 11:25:51 2020
+* Created: Wed Sep 2 10:32:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_4.lvs.report b/cells/or4b/sky130_fd_sc_lp__or4b_4.lvs.report
new file mode 100644
index 0000000..43e841a
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4b_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4b_4.sp ('sky130_fd_sc_lp__or4b_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4b/sky130_fd_sc_lp__or4b_4.spice ('sky130_fd_sc_lp__or4b_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4b_4 sky130_fd_sc_lp__or4b_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4b_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or4b_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 9 9 MN (4 pins)
+ 9 9 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C D_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_4.pex.spice b/cells/or4b/sky130_fd_sc_lp__or4b_4.pex.spice
index d8b7edd..c34122f 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_4.pex.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_4.pex.spice
-* Created: Fri Aug 28 11:25:59 2020
+* Created: Wed Sep 2 10:32:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_4.pxi.spice b/cells/or4b/sky130_fd_sc_lp__or4b_4.pxi.spice
index 28db13e..65bb626 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_4.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_4.pxi.spice
-* Created: Fri Aug 28 11:25:59 2020
+* Created: Wed Sep 2 10:32:42 2020
*
x_PM_SKY130_FD_SC_LP__OR4B_4%A_83_21# N_A_83_21#_M1006_d N_A_83_21#_M1003_d
+ N_A_83_21#_M1010_d N_A_83_21#_M1000_g N_A_83_21#_M1001_g N_A_83_21#_M1007_g
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_4.spice b/cells/or4b/sky130_fd_sc_lp__or4b_4.spice
index 25e3c43..95bb00a 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_4.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_4.spice
-* Created: Fri Aug 28 11:25:59 2020
+* Created: Wed Sep 2 10:32:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_lp.lvs.report b/cells/or4b/sky130_fd_sc_lp__or4b_lp.lvs.report
new file mode 100644
index 0000000..b477500
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4b_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4b_lp.sp ('sky130_fd_sc_lp__or4b_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4b/sky130_fd_sc_lp__or4b_lp.spice ('sky130_fd_sc_lp__or4b_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4b_lp sky130_fd_sc_lp__or4b_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4b_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or4b_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 20 20
+
+ Instances: 12 12 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 19 18
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 2 2 MP (4 pins)
+ 6 6 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 2 2 0 0 MP(PHIGHVT)
+ 6 6 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_lp.pex.spice b/cells/or4b/sky130_fd_sc_lp__or4b_lp.pex.spice
index 89fea17..12d2b16 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_lp.pex.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_lp.pex.spice
-* Created: Fri Aug 28 11:26:07 2020
+* Created: Wed Sep 2 10:32:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_lp.pxi.spice b/cells/or4b/sky130_fd_sc_lp__or4b_lp.pxi.spice
index d2ee1d5..679e6f3 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_lp.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_lp.pxi.spice
-* Created: Fri Aug 28 11:26:07 2020
+* Created: Wed Sep 2 10:32:49 2020
*
x_PM_SKY130_FD_SC_LP__OR4B_LP%D_N N_D_N_M1016_g N_D_N_M1006_g N_D_N_M1011_g
+ N_D_N_c_102_n N_D_N_c_106_n D_N D_N N_D_N_c_104_n
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_lp.spice b/cells/or4b/sky130_fd_sc_lp__or4b_lp.spice
index 7692f16..7c52862 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_lp.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_lp.spice
-* Created: Fri Aug 28 11:26:07 2020
+* Created: Wed Sep 2 10:32:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_m.lvs.report b/cells/or4b/sky130_fd_sc_lp__or4b_m.lvs.report
new file mode 100644
index 0000000..98743ff
--- /dev/null
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4b_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4b_m.sp ('sky130_fd_sc_lp__or4b_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4b/sky130_fd_sc_lp__or4b_m.spice ('sky130_fd_sc_lp__or4b_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:32:53 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4b_m sky130_fd_sc_lp__or4b_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4b_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or4b_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 14 14
+
+ Instances: 6 6 MN (4 pins)
+ 6 6 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 13 12
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 11 11
+
+ Instances: 6 6 MN (4 pins)
+ 2 2 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 9 9
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 11 11 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 9 9 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D_N C B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_m.pex.spice b/cells/or4b/sky130_fd_sc_lp__or4b_m.pex.spice
index a74956d..26b8fe3 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_m.pex.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_m.pex.spice
-* Created: Fri Aug 28 11:26:15 2020
+* Created: Wed Sep 2 10:32:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_m.pxi.spice b/cells/or4b/sky130_fd_sc_lp__or4b_m.pxi.spice
index 8b48611..baf27a6 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_m.pxi.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_m.pxi.spice
-* Created: Fri Aug 28 11:26:15 2020
+* Created: Wed Sep 2 10:32:57 2020
*
x_PM_SKY130_FD_SC_LP__OR4B_M%D_N N_D_N_c_80_n N_D_N_M1003_g N_D_N_M1004_g
+ N_D_N_c_82_n D_N D_N N_D_N_c_78_n N_D_N_c_79_n PM_SKY130_FD_SC_LP__OR4B_M%D_N
diff --git a/cells/or4b/sky130_fd_sc_lp__or4b_m.spice b/cells/or4b/sky130_fd_sc_lp__or4b_m.spice
index 3999e52..32beba2 100644
--- a/cells/or4b/sky130_fd_sc_lp__or4b_m.spice
+++ b/cells/or4b/sky130_fd_sc_lp__or4b_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4b_m.spice
-* Created: Fri Aug 28 11:26:15 2020
+* Created: Wed Sep 2 10:32:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.lvs.report b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.lvs.report
new file mode 100644
index 0000000..9d67f76
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4bb_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4bb_1.sp ('sky130_fd_sc_lp__or4bb_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4bb/sky130_fd_sc_lp__or4bb_1.spice ('sky130_fd_sc_lp__or4bb_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4bb_1 sky130_fd_sc_lp__or4bb_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4bb_1
+SOURCE CELL NAME: sky130_fd_sc_lp__or4bb_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N D_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pex.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pex.spice
index 654bb52..e9edda0 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_1.pex.spice
-* Created: Fri Aug 28 11:26:23 2020
+* Created: Wed Sep 2 10:33:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pxi.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pxi.spice
index d2b9d31..c180a4f 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_1.pxi.spice
-* Created: Fri Aug 28 11:26:23 2020
+* Created: Wed Sep 2 10:33:05 2020
*
x_PM_SKY130_FD_SC_LP__OR4BB_1%C_N N_C_N_M1011_g N_C_N_M1008_g N_C_N_c_91_n
+ N_C_N_c_92_n N_C_N_c_93_n C_N C_N N_C_N_c_95_n PM_SKY130_FD_SC_LP__OR4BB_1%C_N
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.spice
index f64cb1c..a7a98fe 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_1.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_1.spice
-* Created: Fri Aug 28 11:26:23 2020
+* Created: Wed Sep 2 10:33:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.lvs.report b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.lvs.report
new file mode 100644
index 0000000..e7606cc
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4bb_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4bb_2.sp ('sky130_fd_sc_lp__or4bb_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4bb/sky130_fd_sc_lp__or4bb_2.spice ('sky130_fd_sc_lp__or4bb_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4bb_2 sky130_fd_sc_lp__or4bb_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4bb_2
+SOURCE CELL NAME: sky130_fd_sc_lp__or4bb_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 17 16
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B D_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pex.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pex.spice
index 04a4f3b..8d8d1a5 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_2.pex.spice
-* Created: Fri Aug 28 11:26:32 2020
+* Created: Wed Sep 2 10:33:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pxi.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pxi.spice
index 8fc053b..b6dc79c 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_2.pxi.spice
-* Created: Fri Aug 28 11:26:32 2020
+* Created: Wed Sep 2 10:33:12 2020
*
x_PM_SKY130_FD_SC_LP__OR4BB_2%C_N N_C_N_M1003_g N_C_N_c_105_n N_C_N_c_106_n
+ N_C_N_c_112_n N_C_N_c_113_n N_C_N_M1007_g N_C_N_c_107_n C_N C_N C_N
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.spice
index b606734..e92183c 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_2.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_2.spice
-* Created: Fri Aug 28 11:26:32 2020
+* Created: Wed Sep 2 10:33:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.lvs.report b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.lvs.report
new file mode 100644
index 0000000..0c076ac
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.lvs.report
@@ -0,0 +1,471 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4bb_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4bb_4.sp ('sky130_fd_sc_lp__or4bb_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4bb/sky130_fd_sc_lp__or4bb_4.spice ('sky130_fd_sc_lp__or4bb_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:16 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4bb_4 sky130_fd_sc_lp__or4bb_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4bb_4
+SOURCE CELL NAME: sky130_fd_sc_lp__or4bb_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N A B D_N VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pex.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pex.spice
index 5bd6781..afead53 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_4.pex.spice
-* Created: Fri Aug 28 11:26:44 2020
+* Created: Wed Sep 2 10:33:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pxi.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pxi.spice
index 9f74624..f261fca 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_4.pxi.spice
-* Created: Fri Aug 28 11:26:44 2020
+* Created: Wed Sep 2 10:33:19 2020
*
x_PM_SKY130_FD_SC_LP__OR4BB_4%C_N N_C_N_c_104_n N_C_N_M1011_g N_C_N_M1014_g
+ N_C_N_c_106_n N_C_N_c_107_n C_N C_N PM_SKY130_FD_SC_LP__OR4BB_4%C_N
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.spice
index 22bf5f6..7419666 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_4.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_4.spice
-* Created: Fri Aug 28 11:26:44 2020
+* Created: Wed Sep 2 10:33:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.lvs.report b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.lvs.report
new file mode 100644
index 0000000..3df9071
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4bb_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4bb_lp.sp ('sky130_fd_sc_lp__or4bb_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.spice ('sky130_fd_sc_lp__or4bb_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4bb_lp sky130_fd_sc_lp__or4bb_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4bb_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__or4bb_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 22 22
+
+ Instances: 14 14 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 22 21
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 3 3 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N B A D_N X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pex.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pex.spice
index 9014da2..1633c66 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_lp.pex.spice
-* Created: Fri Aug 28 11:26:57 2020
+* Created: Wed Sep 2 10:33:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pxi.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pxi.spice
index cfa0f1e..f37aaa8 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_lp.pxi.spice
-* Created: Fri Aug 28 11:26:57 2020
+* Created: Wed Sep 2 10:33:26 2020
*
x_PM_SKY130_FD_SC_LP__OR4BB_LP%A_86_21# N_A_86_21#_M1013_d N_A_86_21#_M1004_d
+ N_A_86_21#_M1019_d N_A_86_21#_M1012_g N_A_86_21#_c_157_n N_A_86_21#_c_158_n
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.spice
index 7f0a478..23903a5 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_lp.spice
-* Created: Fri Aug 28 11:26:57 2020
+* Created: Wed Sep 2 10:33:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.lvs.report b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.lvs.report
new file mode 100644
index 0000000..d76efc5
--- /dev/null
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__or4bb_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__or4bb_m.sp ('sky130_fd_sc_lp__or4bb_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/or4bb/sky130_fd_sc_lp__or4bb_m.spice ('sky130_fd_sc_lp__or4bb_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__or4bb_m sky130_fd_sc_lp__or4bb_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__or4bb_m
+SOURCE CELL NAME: sky130_fd_sc_lp__or4bb_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 15 15
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 15 14
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 12 12
+
+ Instances: 7 7 MN (4 pins)
+ 3 3 MP (4 pins)
+ 1 1 SMP4 (6 pins)
+ ------ ------
+ Total Inst: 11 11
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 12 12 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMP4
+ ------- ------- --------- ---------
+ Total Inst: 11 11 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C_N D_N B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pex.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pex.spice
index d22e5d7..e45f11a 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pex.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_m.pex.spice
-* Created: Fri Aug 28 11:27:05 2020
+* Created: Wed Sep 2 10:33:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pxi.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pxi.spice
index 0d47055..3695dfe 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pxi.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_m.pxi.spice
-* Created: Fri Aug 28 11:27:05 2020
+* Created: Wed Sep 2 10:33:34 2020
*
x_PM_SKY130_FD_SC_LP__OR4BB_M%C_N N_C_N_M1011_g N_C_N_M1010_g N_C_N_c_99_n
+ N_C_N_c_100_n N_C_N_c_101_n C_N C_N N_C_N_c_103_n
diff --git a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.spice b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.spice
index 5be2ce4..562e0b9 100644
--- a/cells/or4bb/sky130_fd_sc_lp__or4bb_m.spice
+++ b/cells/or4bb/sky130_fd_sc_lp__or4bb_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__or4bb_m.spice
-* Created: Fri Aug 28 11:27:05 2020
+* Created: Wed Sep 2 10:33:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.lvs.report b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.lvs.report
new file mode 100644
index 0000000..ed040f8
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfbbn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfbbn_1.sp ('sky130_fd_sc_lp__sdfbbn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.spice ('sky130_fd_sc_lp__sdfbbn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfbbn_1 sky130_fd_sc_lp__sdfbbn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfbbn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfbbn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 36 36
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pex.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pex.spice
index e8a3238..667fabd 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_1.pex.spice
-* Created: Fri Aug 28 11:27:13 2020
+* Created: Wed Sep 2 10:33:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pxi.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pxi.spice
index 7bc849d..c4aac4a 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_1.pxi.spice
-* Created: Fri Aug 28 11:27:13 2020
+* Created: Wed Sep 2 10:33:42 2020
*
x_PM_SKY130_FD_SC_LP__SDFBBN_1%SCD N_SCD_c_349_n N_SCD_M1024_g N_SCD_M1032_g
+ N_SCD_c_355_n SCD N_SCD_c_351_n N_SCD_c_352_n PM_SKY130_FD_SC_LP__SDFBBN_1%SCD
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.spice
index 6538090..1ee064f 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_1.spice
-* Created: Fri Aug 28 11:27:13 2020
+* Created: Wed Sep 2 10:33:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.lvs.report b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.lvs.report
new file mode 100644
index 0000000..fd2f8af
--- /dev/null
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfbbn_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfbbn_2.sp ('sky130_fd_sc_lp__sdfbbn_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.spice ('sky130_fd_sc_lp__sdfbbn_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfbbn_2 sky130_fd_sc_lp__sdfbbn_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfbbn_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfbbn_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 36 36
+
+ Instances: 26 26 MN (4 pins)
+ 26 26 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK_N SET_B RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pex.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pex.spice
index 7e8efc5..9282c69 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pex.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_2.pex.spice
-* Created: Fri Aug 28 11:27:21 2020
+* Created: Wed Sep 2 10:33:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pxi.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pxi.spice
index 2531dfb..088ac1a 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pxi.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_2.pxi.spice
-* Created: Fri Aug 28 11:27:21 2020
+* Created: Wed Sep 2 10:33:50 2020
*
x_PM_SKY130_FD_SC_LP__SDFBBN_2%SCD N_SCD_c_350_n N_SCD_M1013_g N_SCD_c_355_n
+ N_SCD_M1048_g N_SCD_c_357_n N_SCD_c_358_n SCD N_SCD_c_352_n N_SCD_c_353_n
diff --git a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.spice b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.spice
index f04e6d3..871d9c0 100644
--- a/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.spice
+++ b/cells/sdfbbn/sky130_fd_sc_lp__sdfbbn_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbn_2.spice
-* Created: Fri Aug 28 11:27:21 2020
+* Created: Wed Sep 2 10:33:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.lvs.report b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.lvs.report
new file mode 100644
index 0000000..50c7f8f
--- /dev/null
+++ b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.lvs.report
@@ -0,0 +1,1225 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfbbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfbbp_1.sp ('sky130_fd_sc_lp__sdfbbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.spice ('sky130_fd_sc_lp__sdfbbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:33:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports.
+ Error: Connectivity errors.
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ INCORRECT sky130_fd_sc_lp__sdfbbp_1 sky130_fd_sc_lp__sdfbbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # # #####################
+ # # # #
+ # # INCORRECT #
+ # # # #
+ # # #####################
+
+
+ Error: Different numbers of ports (see below).
+ Error: Connectivity errors.
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfbbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfbbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 10 *
+
+ Nets: 36 36
+
+ Instances: 24 24 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 10 *
+
+ Nets: 22 22
+
+ Instances: 8 8 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 7 7 SMP2 (4 pins)
+ 2 2 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INCORRECT OBJECTS
+**************************************************************************************************************
+
+
+LEGEND:
+-------
+
+ ne = Naming Error (same layout name found in source
+ circuit, but object was matched otherwise).
+
+
+**************************************************************************************************************
+ INCORRECT NETS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 1 Net VNB VNB
+ --- 9 Connections On This Net --- --- 15 Connections On This Net ---
+ -------------------------- --------------------------
+
+ M23(15.255,0.265):b ** missing connection **
+ M22(14.745,0.685):b ** missing connection **
+ M21(13.755,0.235):b ** missing connection **
+ M20(13.245,0.655):b ** missing connection **
+ M7(6.010,0.235):b ** missing connection **
+ M6(4.750,0.505):b ** missing connection **
+ M5(3.625,0.530):b ** missing connection **
+ M4(2.360,0.595):b ** missing connection **
+
+
+
+ ** missing connection ** (SMN2):output
+ M1003:d
+
+
+ ** missing connection ** (SMN2):output
+ M1033:s
+
+
+ ** missing connection ** (SMN2):output
+ M1008:s
+
+
+ ** missing connection ** (SMN2):output
+ M1009:d
+
+
+ ** missing connection ** (SPMN_2_1):output
+ M1011:s
+
+
+ ** missing connection ** (SMN2):output
+ M1010:d
+
+
+ ** missing connection ** (SPMN_2_1):output
+ M1026:s
+
+
+ ** missing connection ** M1039:d
+ ** missing connection ** M1036:s
+ ** missing connection ** M1034:s
+ ** missing connection ** M1030:s
+ ** missing connection ** M1022:d
+ ** missing connection ** M1015:s
+ ** missing connection ** M1002:d
+
+
+--------------------------------------------------------------------------------------------------------------
+
+ 2 Net VPB VPB
+ --- 11 Connections On This Net --- --- 17 Connections On This Net ---
+ -------------------------- --------------------------
+
+ M47(15.255,1.835):b ** missing connection **
+ M46(14.745,1.835):b ** missing connection **
+ M45(13.755,1.785):b ** missing connection **
+ M44(13.245,1.785):b ** missing connection **
+ M31(5.930,2.285):b ** missing connection **
+ M30(4.840,2.285):b ** missing connection **
+ M29(3.850,2.370):b ** missing connection **
+ M28(2.860,2.405):b ** missing connection **
+ M34(7.340,1.865):b ** missing connection **
+ M41(11.315,2.255):b ** missing connection **
+
+
+
+ ** missing connection ** (SMP2):output
+ M1032:s
+
+
+ ** missing connection ** (SMP2):output
+ M1037:d
+
+
+ ** missing connection ** (SMP2):output
+ M1017:d
+
+
+ ** missing connection ** (SMP2):output
+ M1031:s
+
+
+ ** missing connection ** (SMP2):output
+ M1046:d
+
+
+ ** missing connection ** (SMP2):output
+ M1014:d
+
+
+ ** missing connection ** (SMP2):output
+ M1016:d
+
+
+ ** missing connection ** M1045:s
+ ** missing connection ** M1044:s
+ ** missing connection ** M1042:d
+ ** missing connection ** M1038:s
+ ** missing connection ** M1025:d
+ ** missing connection ** M1006:s
+ ** missing connection ** M1000:d
+ ** missing connection ** M1020:s
+ ** missing connection ** M1040:s
+
+
+--------------------------------------------------------------------------------------------------------------
+
+ 3 Net VPWR ** no similar net **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 4 Net VGND ** no similar net **
+
+--------------------------------------------------------------------------------------------------------------
+
+ 5 ** no similar net ** w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 6 ** no similar net ** w_0_0#
+
+
+**************************************************************************************************************
+ INCORRECT PORTS
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 7 VPWR on net: VPWR ** missing port **
+ 8 VGND on net: VGND ** missing port **
+
+
+**************************************************************************************************************
+ INCORRECT INSTANCES
+
+DISC# LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ 9 M8(6.440,0.235) MN(NSHORT) M1023 MN(NSHORT)
+ g: 8 g: a_893_101#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 10 M9(6.800,0.235) MN(NSHORT) M1010 MN(NSHORT)
+ g: 9 g: a_1297_290#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 11 M12(8.250,0.235) MN(NSHORT) M1007 MN(NSHORT)
+ g: 12 g: a_1650_21#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 12 M11(7.740,0.235) MN(NSHORT) M1001 MN(NSHORT)
+ g: 11 g: a_1216_457#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 13 M10(7.310,0.235) MN(NSHORT) M1026 MN(NSHORT)
+ g: SET_B g: SET_B
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 14 M19(12.275,0.285) MN(NSHORT) M1047 MN(NSHORT)
+ g: 12 g: a_1650_21#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 15 M18(11.675,0.285) MN(NSHORT) M1028 MN(NSHORT)
+ g: 15 g: a_1861_431#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 16 M17(11.245,0.285) MN(NSHORT) M1011 MN(NSHORT)
+ g: SET_B g: SET_B
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 17 M32(6.360,2.285) MP(PHIGHVT) M1043 MP(PHIGHVT)
+ g: 13 g: a_755_106#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 18 M33(6.750,2.285) MP(PHIGHVT) M1016 MP(PHIGHVT)
+ g: 9 g: a_1297_290#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 19 M2(1.300,0.595) MN(NSHORT) M1019 MN(NSHORT)
+ g: D g: D
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 20 M3(1.660,0.595) MN(NSHORT) M1003 MN(NSHORT)
+ g: 5 g: a_332_93#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 21 M0(0.480,0.595) MN(NSHORT) M1033 MN(NSHORT)
+ g: SCD g: SCD
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 22 M1(0.870,0.595) MN(NSHORT) M1013 MN(NSHORT)
+ g: SCE g: SCE
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 23 M15(10.180,0.505) MN(NSHORT) M1027 MN(NSHORT)
+ g: 13 g: a_755_106#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 24 M16(10.570,0.505) MN(NSHORT) M1009 MN(NSHORT)
+ g: 14 g: a_2064_453#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 25 M13(9.250,0.285) MN(NSHORT) M1008 MN(NSHORT)
+ g: 9 g: a_1297_290#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 26 M14(9.670,0.285) MN(NSHORT) M1018 MN(NSHORT)
+ g: 8 g: a_893_101#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 27 M25(0.970,2.405) MP(PHIGHVT) M1032 MP(PHIGHVT)
+ g: SCE g: SCE
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 28 M26(1.360,2.405) MP(PHIGHVT) M1005 MP(PHIGHVT)
+ g: D g: D
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 29 M27(1.790,2.405) MP(PHIGHVT) M1041 MP(PHIGHVT)
+ g: 5 g: a_332_93#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 30 M24(0.420,2.405) MP(PHIGHVT) M1037 MP(PHIGHVT)
+ g: SCD g: SCD
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 31 M35(7.770,1.865) MP(PHIGHVT) M1024 MP(PHIGHVT)
+ g: 11 g: a_1216_457#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 32 M36(8.250,1.865) MP(PHIGHVT) M1046 MP(PHIGHVT)
+ g: 12 g: a_1650_21#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 33 M39(9.665,2.575) MP(PHIGHVT) M1029 MP(PHIGHVT)
+ g: 8 g: a_893_101#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 34 M40(10.320,2.575) MP(PHIGHVT) M1017 MP(PHIGHVT)
+ g: 14 g: a_2064_453#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 35 M37(8.680,1.865) MP(PHIGHVT) M1031 MP(PHIGHVT)
+ g: 9 g: a_1297_290#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 36 M38(9.155,2.155) MP(PHIGHVT) M1035 MP(PHIGHVT)
+ g: 13 g: a_755_106#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 37 M42(11.825,2.255) MP(PHIGHVT) M1021 MP(PHIGHVT)
+ g: 15 g: a_1861_431#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ 38 M43(12.245,2.255) MP(PHIGHVT) M1014 MP(PHIGHVT)
+ g: 12 g: a_1650_21#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 2 0
+
+ Nets: 20 20 2 2
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 7 7 0 0 SMP2
+ 2 2 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Layout Names That Are Missing In The Source:
+
+ Ports: VPWR VGND
+ Nets: VPWR VGND
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK SET_B RESET_B Q_N Q
+
+
+**************************************************************************************************************
+ DETAILED INSTANCE CONNECTIONS
+
+ LAYOUT NAME SOURCE NAME
+**************************************************************************************************************
+
+ (This section contains detailed information about connections of
+ matched instances that are involved in net discrepancies).
+
+--------------------------------------------------------------------------------------------------------------
+
+ M41(11.315,2.255) MP(PHIGHVT) M1020 MP(PHIGHVT)
+ g: SET_B g: SET_B
+ d: 14 d: a_2064_453#
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M34(7.340,1.865) MP(PHIGHVT) M1040 MP(PHIGHVT)
+ g: SET_B g: SET_B
+ d: 9 d: a_1297_290#
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M4(2.360,0.595) MN(NSHORT) M1034 MN(NSHORT)
+ g: SCE g: SCE
+ d: 5 d: a_332_93#
+ s: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** s: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M5(3.625,0.530) MN(NSHORT) M1015 MN(NSHORT)
+ g: CLK g: CLK
+ d: 13 d: a_755_106#
+ s: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** s: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M6(4.750,0.505) MN(NSHORT) M1022 MN(NSHORT)
+ g: 13 g: a_755_106#
+ s: 8 s: a_893_101#
+ d: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** d: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M7(6.010,0.235) MN(NSHORT) M1004 MN(NSHORT)
+ g: 13 g: a_755_106#
+ s: 21 s: a_204_119#
+ d: 11 d: a_1216_457#
+ b: VNB ** VNB **
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M20(13.245,0.655) MN(NSHORT) M1002 MN(NSHORT)
+ g: RESET_B g: RESET_B
+ s: 12 s: a_1650_21#
+ d: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** d: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M21(13.755,0.235) MN(NSHORT) M1036 MN(NSHORT)
+ g: 14 g: a_2064_453#
+ d: Q_N d: Q_N
+ s: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** s: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M22(14.745,0.685) MN(NSHORT) M1039 MN(NSHORT)
+ g: 14 g: a_2064_453#
+ s: 17 s: a_2892_137#
+ d: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** d: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M23(15.255,0.265) MN(NSHORT) M1030 MN(NSHORT)
+ g: 17 g: a_2892_137#
+ d: Q d: Q
+ s: VGND ** no similar net **
+ b: VNB ** VNB **
+ ** VNB ** s: VNB
+ ** no similar net ** b: w_0_0#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M28(2.860,2.405) MP(PHIGHVT) M1038 MP(PHIGHVT)
+ g: SCE g: SCE
+ d: 5 d: a_332_93#
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M29(3.850,2.370) MP(PHIGHVT) M1006 MP(PHIGHVT)
+ g: CLK g: CLK
+ d: 13 d: a_755_106#
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M30(4.840,2.285) MP(PHIGHVT) M1042 MP(PHIGHVT)
+ g: 13 g: a_755_106#
+ s: 8 s: a_893_101#
+ d: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** d: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M31(5.930,2.285) MP(PHIGHVT) M1012 MP(PHIGHVT)
+ g: 8 g: a_893_101#
+ s: 21 s: a_204_119#
+ d: 11 d: a_1216_457#
+ b: VPB ** VPB **
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M44(13.245,1.785) MP(PHIGHVT) M1000 MP(PHIGHVT)
+ g: RESET_B g: RESET_B
+ s: 12 s: a_1650_21#
+ d: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** d: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M45(13.755,1.785) MP(PHIGHVT) M1045 MP(PHIGHVT)
+ g: 14 g: a_2064_453#
+ d: Q_N d: Q_N
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M46(14.745,1.835) MP(PHIGHVT) M1025 MP(PHIGHVT)
+ g: 14 g: a_2064_453#
+ s: 17 s: a_2892_137#
+ d: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** d: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ M47(15.255,1.835) MP(PHIGHVT) M1044 MP(PHIGHVT)
+ g: 17 g: a_2892_137#
+ d: Q d: Q
+ s: VPWR ** no similar net **
+ b: VPB ** VPB **
+ ** VPB ** s: VPB
+ ** no similar net ** b: w_n38_331#
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMN2) (SMN2)
+ output: 11 output: a_1216_457#
+ input: 8 input: a_893_101#
+ input: 9 input: a_1297_290#
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M8(6.440,0.235) MN(NSHORT) M1023 MN(NSHORT)
+ M9(6.800,0.235) MN(NSHORT) M1010 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SPMN_2_1) (SPMN_2_1)
+ output: 9 output: a_1297_290#
+ input: 12 input: a_1650_21#
+ input: 11 input: a_1216_457#
+ input: SET_B input: SET_B
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M12(8.250,0.235) MN(NSHORT) M1007 MN(NSHORT)
+ M11(7.740,0.235) MN(NSHORT) M1001 MN(NSHORT)
+ M10(7.310,0.235) MN(NSHORT) M1026 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SPMN_2_1) (SPMN_2_1)
+ output: 14 output: a_2064_453#
+ input: 12 input: a_1650_21#
+ input: 15 input: a_1861_431#
+ input: SET_B input: SET_B
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M19(12.275,0.285) MN(NSHORT) M1047 MN(NSHORT)
+ M18(11.675,0.285) MN(NSHORT) M1028 MN(NSHORT)
+ M17(11.245,0.285) MN(NSHORT) M1011 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 11 output: a_1216_457#
+ input: 13 input: a_755_106#
+ input: 9 input: a_1297_290#
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M32(6.360,2.285) MP(PHIGHVT) M1043 MP(PHIGHVT)
+ M33(6.750,2.285) MP(PHIGHVT) M1016 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMN2) (SMN2)
+ output: 21 output: a_204_119#
+ input: D input: D
+ input: 5 input: a_332_93#
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M2(1.300,0.595) MN(NSHORT) M1019 MN(NSHORT)
+ M3(1.660,0.595) MN(NSHORT) M1003 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMN2) (SMN2)
+ output: 21 output: a_204_119#
+ input: SCD input: SCD
+ input: SCE input: SCE
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M0(0.480,0.595) MN(NSHORT) M1033 MN(NSHORT)
+ M1(0.870,0.595) MN(NSHORT) M1013 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMN2) (SMN2)
+ output: 15 output: a_1861_431#
+ input: 13 input: a_755_106#
+ input: 14 input: a_2064_453#
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M15(10.180,0.505) MN(NSHORT) M1027 MN(NSHORT)
+ M16(10.570,0.505) MN(NSHORT) M1009 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMN2) (SMN2)
+ output: 15 output: a_1861_431#
+ input: 9 input: a_1297_290#
+ input: 8 input: a_893_101#
+ output: VGND ** no similar net **
+ ** VNB ** output: VNB
+
+ Transistors:
+ M13(9.250,0.285) MN(NSHORT) M1008 MN(NSHORT)
+ M14(9.670,0.285) MN(NSHORT) M1018 MN(NSHORT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 21 output: a_204_119#
+ input: SCE input: SCE
+ input: D input: D
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M25(0.970,2.405) MP(PHIGHVT) M1032 MP(PHIGHVT)
+ M26(1.360,2.405) MP(PHIGHVT) M1005 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 21 output: a_204_119#
+ input: 5 input: a_332_93#
+ input: SCD input: SCD
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M27(1.790,2.405) MP(PHIGHVT) M1041 MP(PHIGHVT)
+ M24(0.420,2.405) MP(PHIGHVT) M1037 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 9 output: a_1297_290#
+ input: 11 input: a_1216_457#
+ input: 12 input: a_1650_21#
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M35(7.770,1.865) MP(PHIGHVT) M1024 MP(PHIGHVT)
+ M36(8.250,1.865) MP(PHIGHVT) M1046 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 15 output: a_1861_431#
+ input: 8 input: a_893_101#
+ input: 14 input: a_2064_453#
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M39(9.665,2.575) MP(PHIGHVT) M1029 MP(PHIGHVT)
+ M40(10.320,2.575) MP(PHIGHVT) M1017 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 15 output: a_1861_431#
+ input: 9 input: a_1297_290#
+ input: 13 input: a_755_106#
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M37(8.680,1.865) MP(PHIGHVT) M1031 MP(PHIGHVT)
+ M38(9.155,2.155) MP(PHIGHVT) M1035 MP(PHIGHVT)
+
+--------------------------------------------------------------------------------------------------------------
+
+ (SMP2) (SMP2)
+ output: 14 output: a_2064_453#
+ input: 15 input: a_1861_431#
+ input: 12 input: a_1650_21#
+ output: VPWR ** no similar net **
+ ** VPB ** output: VPB
+
+ Transistors:
+ M42(11.825,2.255) MP(PHIGHVT) M1021 MP(PHIGHVT)
+ M43(12.245,2.255) MP(PHIGHVT) M1014 MP(PHIGHVT)
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pex.spice b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pex.spice
index 7f2e414..86cbc01 100644
--- a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pex.spice
+++ b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbp_1.pex.spice
-* Created: Fri Aug 28 11:27:30 2020
+* Created: Wed Sep 2 10:33:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pxi.spice b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pxi.spice
index 1bf0885..03814e5 100644
--- a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pxi.spice
+++ b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbp_1.pxi.spice
-* Created: Fri Aug 28 11:27:30 2020
+* Created: Wed Sep 2 10:33:58 2020
*
x_PM_SKY130_FD_SC_LP__SDFBBP_1%SCD N_SCD_M1037_g N_SCD_M1033_g N_SCD_c_350_n
+ N_SCD_c_354_n N_SCD_c_355_n N_SCD_c_356_n SCD N_SCD_c_351_n N_SCD_c_352_n
diff --git a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.spice b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.spice
index b09ac66..3ab746d 100644
--- a/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.spice
+++ b/cells/sdfbbp/sky130_fd_sc_lp__sdfbbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfbbp_1.spice
-* Created: Fri Aug 28 11:27:30 2020
+* Created: Wed Sep 2 10:33:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.lvs.report b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.lvs.report
new file mode 100644
index 0000000..f38bd9a
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrbp_1.sp ('sky130_fd_sc_lp__sdfrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.spice ('sky130_fd_sc_lp__sdfrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrbp_1 sky130_fd_sc_lp__sdfrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 31 31
+
+ Instances: 23 23 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pex.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pex.spice
index f2ee0d0..2c2d904 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_1.pex.spice
-* Created: Fri Aug 28 11:27:38 2020
+* Created: Wed Sep 2 10:34:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pxi.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pxi.spice
index acbbf2d..895eb20 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_1.pxi.spice
-* Created: Fri Aug 28 11:27:38 2020
+* Created: Wed Sep 2 10:34:05 2020
*
x_PM_SKY130_FD_SC_LP__SDFRBP_1%SCE N_SCE_M1042_g N_SCE_c_293_n N_SCE_c_294_n
+ N_SCE_c_304_n N_SCE_c_305_n N_SCE_M1000_g N_SCE_c_306_n N_SCE_c_307_n
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.spice
index 5a77b83..ebfa8c3 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_1.spice
-* Created: Fri Aug 28 11:27:38 2020
+* Created: Wed Sep 2 10:34:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.lvs.report b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.lvs.report
new file mode 100644
index 0000000..3f49856
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrbp_2.sp ('sky130_fd_sc_lp__sdfrbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.spice ('sky130_fd_sc_lp__sdfrbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:09 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrbp_2 sky130_fd_sc_lp__sdfrbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 31 31
+
+ Instances: 25 25 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 49 48
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 9 9 MN (4 pins)
+ 13 13 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 9 9 0 0 MN(NSHORT)
+ 13 13 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 12 layout mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+ 12 source mos transistors were reduced to 6.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK RESET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pex.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pex.spice
index e0e111c..27de1c5 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_2.pex.spice
-* Created: Fri Aug 28 11:27:50 2020
+* Created: Wed Sep 2 10:34:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pxi.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pxi.spice
index 249ec19..ce30d2a 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_2.pxi.spice
-* Created: Fri Aug 28 11:27:50 2020
+* Created: Wed Sep 2 10:34:13 2020
*
x_PM_SKY130_FD_SC_LP__SDFRBP_2%SCE N_SCE_M1014_g N_SCE_c_287_n N_SCE_c_288_n
+ N_SCE_M1021_g N_SCE_c_289_n N_SCE_c_290_n N_SCE_M1004_g N_SCE_M1024_g
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.spice
index 7308618..e4bc887 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_2.spice
-* Created: Fri Aug 28 11:27:50 2020
+* Created: Wed Sep 2 10:34:13 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.lvs.report b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.lvs.report
new file mode 100644
index 0000000..c0b0d6b
--- /dev/null
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrbp_lp.sp ('sky130_fd_sc_lp__sdfrbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.spice ('sky130_fd_sc_lp__sdfrbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrbp_lp sky130_fd_sc_lp__sdfrbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 49 49
+
+ Instances: 28 28 MN (4 pins)
+ 32 32 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 61 60
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 2 2 MN (4 pins)
+ 2 2 MP (4 pins)
+ 9 9 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 15 15 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 2 2 0 0 MP(PHIGHVT)
+ 9 9 0 0 SMN2
+ 1 1 0 0 SMN3
+ 15 15 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pex.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pex.spice
index 47e7098..0bbd46c 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pex.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_lp.pex.spice
-* Created: Fri Aug 28 11:28:03 2020
+* Created: Wed Sep 2 10:34:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pxi.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pxi.spice
index 416168a..59435e3 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pxi.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_lp.pxi.spice
-* Created: Fri Aug 28 11:28:03 2020
+* Created: Wed Sep 2 10:34:20 2020
*
x_PM_SKY130_FD_SC_LP__SDFRBP_LP%SCE N_SCE_M1040_g N_SCE_M1024_g N_SCE_M1017_g
+ N_SCE_M1016_g N_SCE_c_382_n N_SCE_c_383_n N_SCE_M1008_g N_SCE_M1013_g
diff --git a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.spice b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.spice
index d29723c..94ea253 100644
--- a/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.spice
+++ b/cells/sdfrbp/sky130_fd_sc_lp__sdfrbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrbp_lp.spice
-* Created: Fri Aug 28 11:28:03 2020
+* Created: Wed Sep 2 10:34:20 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.lvs.report b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.lvs.report
new file mode 100644
index 0000000..99ca774
--- /dev/null
+++ b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtn_1.sp ('sky130_fd_sc_lp__sdfrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.spice ('sky130_fd_sc_lp__sdfrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:24 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtn_1 sky130_fd_sc_lp__sdfrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD SCE D RESET_B CLK_N VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pex.spice b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pex.spice
index d35bb23..8ccbbcc 100644
--- a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pex.spice
+++ b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtn_1.pex.spice
-* Created: Fri Aug 28 11:28:11 2020
+* Created: Wed Sep 2 10:34:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pxi.spice b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pxi.spice
index b261215..68bce0c 100644
--- a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pxi.spice
+++ b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtn_1.pxi.spice
-* Created: Fri Aug 28 11:28:11 2020
+* Created: Wed Sep 2 10:34:28 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTN_1%A_113_63# N_A_113_63#_M1039_d N_A_113_63#_M1021_d
+ N_A_113_63#_c_267_n N_A_113_63#_M1032_g N_A_113_63#_M1015_g
diff --git a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.spice b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.spice
index a9ec769..9899e81 100644
--- a/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.spice
+++ b/cells/sdfrtn/sky130_fd_sc_lp__sdfrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtn_1.spice
-* Created: Fri Aug 28 11:28:11 2020
+* Created: Wed Sep 2 10:34:28 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.lvs.report b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.lvs.report
new file mode 100644
index 0000000..b824cc2
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtp_1.sp ('sky130_fd_sc_lp__sdfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.spice ('sky130_fd_sc_lp__sdfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtp_1 sky130_fd_sc_lp__sdfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pex.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pex.spice
index d00be0b..bfd26a6 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_1.pex.spice
-* Created: Fri Aug 28 11:28:19 2020
+* Created: Wed Sep 2 10:34:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pxi.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pxi.spice
index 51d9510..602fdce 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_1.pxi.spice
-* Created: Fri Aug 28 11:28:19 2020
+* Created: Wed Sep 2 10:34:35 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTP_1%A_35_74# N_A_35_74#_M1026_s N_A_35_74#_M1021_s
+ N_A_35_74#_c_268_n N_A_35_74#_M1006_g N_A_35_74#_M1015_g N_A_35_74#_c_269_n
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.spice
index d884827..cbe8608 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_1.spice
-* Created: Fri Aug 28 11:28:19 2020
+* Created: Wed Sep 2 10:34:35 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.lvs.report b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.lvs.report
new file mode 100644
index 0000000..18cc5fe
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtp_2.sp ('sky130_fd_sc_lp__sdfrtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.spice ('sky130_fd_sc_lp__sdfrtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:39 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtp_2 sky130_fd_sc_lp__sdfrtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pex.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pex.spice
index 16d8595..1b7ced9 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_2.pex.spice
-* Created: Fri Aug 28 11:28:28 2020
+* Created: Wed Sep 2 10:34:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pxi.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pxi.spice
index 3b6ffe2..3fe2d83 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_2.pxi.spice
-* Created: Fri Aug 28 11:28:28 2020
+* Created: Wed Sep 2 10:34:43 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTP_2%A_35_74# N_A_35_74#_M1023_s N_A_35_74#_M1022_s
+ N_A_35_74#_c_283_n N_A_35_74#_M1003_g N_A_35_74#_M1018_g N_A_35_74#_c_284_n
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.spice
index d44ae79..c68b56d 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_2.spice
-* Created: Fri Aug 28 11:28:28 2020
+* Created: Wed Sep 2 10:34:43 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.lvs.report b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.lvs.report
new file mode 100644
index 0000000..08bcfe1
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.lvs.report
@@ -0,0 +1,477 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtp_4.sp ('sky130_fd_sc_lp__sdfrtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.spice ('sky130_fd_sc_lp__sdfrtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtp_4 sky130_fd_sc_lp__sdfrtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 23 23 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pex.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pex.spice
index efd892b..4f78d5e 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_4.pex.spice
-* Created: Fri Aug 28 11:28:36 2020
+* Created: Wed Sep 2 10:34:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pxi.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pxi.spice
index ea874ff..9e4e26a 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_4.pxi.spice
-* Created: Fri Aug 28 11:28:36 2020
+* Created: Wed Sep 2 10:34:51 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTP_4%A_27_74# N_A_27_74#_M1000_s N_A_27_74#_M1002_s
+ N_A_27_74#_M1021_g N_A_27_74#_M1020_g N_A_27_74#_c_323_p N_A_27_74#_c_309_n
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.spice
index 1f969da..22e3d56 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_4.spice
-* Created: Fri Aug 28 11:28:36 2020
+* Created: Wed Sep 2 10:34:51 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.lvs.report b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.lvs.report
new file mode 100644
index 0000000..35aa83f
--- /dev/null
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtp_lp2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtp_lp2.sp ('sky130_fd_sc_lp__sdfrtp_lp2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.spice ('sky130_fd_sc_lp__sdfrtp_lp2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:34:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtp_lp2 sky130_fd_sc_lp__sdfrtp_lp2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtp_lp2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtp_lp2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 36 36
+
+ Instances: 26 26 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 2 2 MN (4 pins)
+ 12 12 MP (4 pins)
+ 8 8 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 8 8 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK RESET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pex.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pex.spice
index d4c26cf..ce62c0e 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pex.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_lp2.pex.spice
-* Created: Fri Aug 28 11:28:45 2020
+* Created: Wed Sep 2 10:34:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pxi.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pxi.spice
index 6f18c32..b9be8b8 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pxi.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_lp2.pxi.spice
-* Created: Fri Aug 28 11:28:45 2020
+* Created: Wed Sep 2 10:34:59 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTP_LP2%A_81_194# N_A_81_194#_M1013_d
+ N_A_81_194#_M1023_d N_A_81_194#_M1000_g N_A_81_194#_M1030_g
diff --git a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.spice b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.spice
index 02e1d53..1c19deb 100644
--- a/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.spice
+++ b/cells/sdfrtp/sky130_fd_sc_lp__sdfrtp_lp2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_lp2.spice
-* Created: Fri Aug 28 11:28:45 2020
+* Created: Wed Sep 2 10:34:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.lvs.report b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.lvs.report
new file mode 100644
index 0000000..441a519
--- /dev/null
+++ b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfrtp_ov2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfrtp_ov2.sp ('sky130_fd_sc_lp__sdfrtp_ov2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.spice ('sky130_fd_sc_lp__sdfrtp_ov2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfrtp_ov2 sky130_fd_sc_lp__sdfrtp_ov2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfrtp_ov2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfrtp_ov2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 4 4 SMP2 (4 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 1 1 0 0 SMN3
+ 4 4 0 0 SMP2
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pex.spice b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pex.spice
index 93b5e74..75ec17a 100644
--- a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pex.spice
+++ b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_ov2.pex.spice
-* Created: Fri Aug 28 11:28:57 2020
+* Created: Wed Sep 2 10:35:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pxi.spice b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pxi.spice
index 3b650a8..ce09278 100644
--- a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pxi.spice
+++ b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_ov2.pxi.spice
-* Created: Fri Aug 28 11:28:57 2020
+* Created: Wed Sep 2 10:35:06 2020
*
x_PM_SKY130_FD_SC_LP__SDFRTP_OV2%A_35_74# N_A_35_74#_M1024_s N_A_35_74#_M1012_s
+ N_A_35_74#_c_270_n N_A_35_74#_M1005_g N_A_35_74#_M1015_g N_A_35_74#_c_271_n
diff --git a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.spice b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.spice
index 2b50c00..2749b0d 100644
--- a/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.spice
+++ b/cells/sdfrtp_ov2/sky130_fd_sc_lp__sdfrtp_ov2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfrtp_ov2.spice
-* Created: Fri Aug 28 11:28:57 2020
+* Created: Wed Sep 2 10:35:06 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.lvs.report b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.lvs.report
new file mode 100644
index 0000000..702c13e
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfsbp_1.sp ('sky130_fd_sc_lp__sdfsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.spice ('sky130_fd_sc_lp__sdfsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfsbp_1 sky130_fd_sc_lp__sdfsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfsbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 32 32
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pex.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pex.spice
index ca20672..521c3cb 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_1.pex.spice
-* Created: Fri Aug 28 11:29:09 2020
+* Created: Wed Sep 2 10:35:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pxi.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pxi.spice
index 14a95b3..e536dce 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_1.pxi.spice
-* Created: Fri Aug 28 11:29:09 2020
+* Created: Wed Sep 2 10:35:14 2020
*
x_PM_SKY130_FD_SC_LP__SDFSBP_1%SCE N_SCE_c_285_n N_SCE_c_286_n N_SCE_c_287_n
+ N_SCE_M1022_g N_SCE_c_288_n N_SCE_M1013_g N_SCE_M1034_g N_SCE_M1006_g
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.spice
index ca92081..85f57c0 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_1.spice
-* Created: Fri Aug 28 11:29:09 2020
+* Created: Wed Sep 2 10:35:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.lvs.report b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.lvs.report
new file mode 100644
index 0000000..faaadc7
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfsbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfsbp_2.sp ('sky130_fd_sc_lp__sdfsbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.spice ('sky130_fd_sc_lp__sdfsbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:17 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfsbp_2 sky130_fd_sc_lp__sdfsbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfsbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfsbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 32 32
+
+ Instances: 23 23 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 8 8 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pex.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pex.spice
index ceeae30..d0ade55 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_2.pex.spice
-* Created: Fri Aug 28 11:29:17 2020
+* Created: Wed Sep 2 10:35:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pxi.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pxi.spice
index 7235370..78875a4 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_2.pxi.spice
-* Created: Fri Aug 28 11:29:17 2020
+* Created: Wed Sep 2 10:35:22 2020
*
x_PM_SKY130_FD_SC_LP__SDFSBP_2%SCE N_SCE_c_294_n N_SCE_M1029_g N_SCE_M1004_g
+ N_SCE_M1005_g N_SCE_M1011_g N_SCE_c_297_n N_SCE_c_304_n N_SCE_c_298_n
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.spice
index 9393fac..12cc93c 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_2.spice
-* Created: Fri Aug 28 11:29:17 2020
+* Created: Wed Sep 2 10:35:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.lvs.report b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.lvs.report
new file mode 100644
index 0000000..a4afdf5
--- /dev/null
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfsbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfsbp_lp.sp ('sky130_fd_sc_lp__sdfsbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.spice ('sky130_fd_sc_lp__sdfsbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfsbp_lp sky130_fd_sc_lp__sdfsbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfsbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfsbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 39 39
+
+ Instances: 28 28 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 50 49
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 1 1 MN (4 pins)
+ 11 11 MP (4 pins)
+ 12 12 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 30 30
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 12 12 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 30 30 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pex.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pex.spice
index b550985..8e63eeb 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pex.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_lp.pex.spice
-* Created: Fri Aug 28 11:29:25 2020
+* Created: Wed Sep 2 10:35:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pxi.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pxi.spice
index ea32017..e1b9fc3 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pxi.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_lp.pxi.spice
-* Created: Fri Aug 28 11:29:25 2020
+* Created: Wed Sep 2 10:35:29 2020
*
x_PM_SKY130_FD_SC_LP__SDFSBP_LP%SCE N_SCE_M1010_g N_SCE_M1023_g N_SCE_c_333_n
+ N_SCE_M1007_g N_SCE_M1032_g N_SCE_M1046_g N_SCE_c_335_n N_SCE_c_336_n
diff --git a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.spice b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.spice
index 3dfa7d9..667df41 100644
--- a/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.spice
+++ b/cells/sdfsbp/sky130_fd_sc_lp__sdfsbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfsbp_lp.spice
-* Created: Fri Aug 28 11:29:25 2020
+* Created: Wed Sep 2 10:35:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.lvs.report b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.lvs.report
new file mode 100644
index 0000000..7365399
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfstp_1.sp ('sky130_fd_sc_lp__sdfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.spice ('sky130_fd_sc_lp__sdfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfstp_1 sky130_fd_sc_lp__sdfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfstp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pex.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pex.spice
index 824f7c9..74cea93 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_1.pex.spice
-* Created: Fri Aug 28 11:29:34 2020
+* Created: Wed Sep 2 10:35:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pxi.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pxi.spice
index 18fbd93..e13dc31 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_1.pxi.spice
-* Created: Fri Aug 28 11:29:34 2020
+* Created: Wed Sep 2 10:35:37 2020
*
x_PM_SKY130_FD_SC_LP__SDFSTP_1%SCD N_SCD_M1013_g N_SCD_M1014_g N_SCD_c_268_n
+ N_SCD_c_269_n N_SCD_c_274_n SCD SCD N_SCD_c_271_n
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.spice
index 303eedb..596f4e1 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_1.spice
-* Created: Fri Aug 28 11:29:34 2020
+* Created: Wed Sep 2 10:35:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.lvs.report b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.lvs.report
new file mode 100644
index 0000000..7a30250
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfstp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfstp_2.sp ('sky130_fd_sc_lp__sdfstp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.spice ('sky130_fd_sc_lp__sdfstp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfstp_2 sky130_fd_sc_lp__sdfstp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfstp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfstp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 21 21 MN (4 pins)
+ 21 21 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 43 42
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pex.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pex.spice
index 9c684c8..4be3d30 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_2.pex.spice
-* Created: Fri Aug 28 11:29:42 2020
+* Created: Wed Sep 2 10:35:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pxi.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pxi.spice
index aa6e44d..bb527e8 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_2.pxi.spice
-* Created: Fri Aug 28 11:29:42 2020
+* Created: Wed Sep 2 10:35:44 2020
*
x_PM_SKY130_FD_SC_LP__SDFSTP_2%SCD N_SCD_M1037_g N_SCD_c_266_n N_SCD_M1022_g
+ N_SCD_c_267_n N_SCD_c_268_n SCD SCD N_SCD_c_270_n
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.spice
index 3f3b87c..714341e 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_2.spice
-* Created: Fri Aug 28 11:29:42 2020
+* Created: Wed Sep 2 10:35:44 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.lvs.report b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.lvs.report
new file mode 100644
index 0000000..7087fa4
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.lvs.report
@@ -0,0 +1,475 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfstp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfstp_4.sp ('sky130_fd_sc_lp__sdfstp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.spice ('sky130_fd_sc_lp__sdfstp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfstp_4 sky130_fd_sc_lp__sdfstp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfstp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfstp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 31 31
+
+ Instances: 23 23 MN (4 pins)
+ 23 23 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 7 7 MN (4 pins)
+ 10 10 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pex.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pex.spice
index 210171b..2734e99 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_4.pex.spice
-* Created: Fri Aug 28 11:29:51 2020
+* Created: Wed Sep 2 10:35:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pxi.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pxi.spice
index 1e4904b..318a8b5 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_4.pxi.spice
-* Created: Fri Aug 28 11:29:51 2020
+* Created: Wed Sep 2 10:35:53 2020
*
x_PM_SKY130_FD_SC_LP__SDFSTP_4%SCD N_SCD_M1038_g N_SCD_c_286_n N_SCD_M1014_g
+ N_SCD_c_287_n N_SCD_c_288_n SCD SCD N_SCD_c_289_n N_SCD_c_290_n
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.spice
index e307a80..cdd09f7 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_4.spice
-* Created: Fri Aug 28 11:29:51 2020
+* Created: Wed Sep 2 10:35:53 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.lvs.report b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.lvs.report
new file mode 100644
index 0000000..bc8645e
--- /dev/null
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfstp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfstp_lp.sp ('sky130_fd_sc_lp__sdfstp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.spice ('sky130_fd_sc_lp__sdfstp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:35:56 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfstp_lp sky130_fd_sc_lp__sdfstp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfstp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfstp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 37 37
+
+ Instances: 26 26 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 47 46
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 1 1 MN (4 pins)
+ 10 10 MP (4 pins)
+ 11 11 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 11 11 0 0 SMN2
+ 1 1 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK SET_B VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pex.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pex.spice
index 9a43ef6..8b01ca3 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pex.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_lp.pex.spice
-* Created: Fri Aug 28 11:30:03 2020
+* Created: Wed Sep 2 10:36:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pxi.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pxi.spice
index 0080102..de0f97f 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pxi.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_lp.pxi.spice
-* Created: Fri Aug 28 11:30:03 2020
+* Created: Wed Sep 2 10:36:01 2020
*
x_PM_SKY130_FD_SC_LP__SDFSTP_LP%SCE N_SCE_M1006_g N_SCE_M1017_g N_SCE_M1004_g
+ N_SCE_M1044_g N_SCE_M1018_g N_SCE_c_320_n N_SCE_c_321_n N_SCE_c_322_n
diff --git a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.spice b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.spice
index a21bcf0..b3ec717 100644
--- a/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.spice
+++ b/cells/sdfstp/sky130_fd_sc_lp__sdfstp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfstp_lp.spice
-* Created: Fri Aug 28 11:30:03 2020
+* Created: Wed Sep 2 10:36:01 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.lvs.report b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.lvs.report
new file mode 100644
index 0000000..d0ff27a
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxbp_1.sp ('sky130_fd_sc_lp__sdfxbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.spice ('sky130_fd_sc_lp__sdfxbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxbp_1 sky130_fd_sc_lp__sdfxbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 27 27
+
+ Instances: 18 18 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pex.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pex.spice
index 967baf5..7df2060 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_1.pex.spice
-* Created: Fri Aug 28 11:30:15 2020
+* Created: Wed Sep 2 10:36:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pxi.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pxi.spice
index b805190..76957d1 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_1.pxi.spice
-* Created: Fri Aug 28 11:30:15 2020
+* Created: Wed Sep 2 10:36:09 2020
*
x_PM_SKY130_FD_SC_LP__SDFXBP_1%SCD N_SCD_M1017_g N_SCD_M1012_g N_SCD_c_273_n
+ N_SCD_c_277_n SCD SCD SCD N_SCD_c_275_n PM_SKY130_FD_SC_LP__SDFXBP_1%SCD
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.spice
index 812baab..9a1935a 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_1.spice
-* Created: Fri Aug 28 11:30:15 2020
+* Created: Wed Sep 2 10:36:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.lvs.report b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.lvs.report
new file mode 100644
index 0000000..a7b980a
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxbp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxbp_2.sp ('sky130_fd_sc_lp__sdfxbp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.spice ('sky130_fd_sc_lp__sdfxbp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:12 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxbp_2 sky130_fd_sc_lp__sdfxbp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxbp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxbp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 27 27
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 10 10 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 4.
+ 4 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pex.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pex.spice
index c298084..9192594 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_2.pex.spice
-* Created: Fri Aug 28 11:30:24 2020
+* Created: Wed Sep 2 10:36:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pxi.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pxi.spice
index a6174df..055f7b5 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_2.pxi.spice
-* Created: Fri Aug 28 11:30:24 2020
+* Created: Wed Sep 2 10:36:16 2020
*
x_PM_SKY130_FD_SC_LP__SDFXBP_2%SCD N_SCD_M1035_g N_SCD_M1023_g N_SCD_c_278_n
+ N_SCD_c_279_n N_SCD_c_280_n SCD SCD SCD N_SCD_c_282_n
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.spice
index 7b8bf0f..d52963f 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_2.spice
-* Created: Fri Aug 28 11:30:24 2020
+* Created: Wed Sep 2 10:36:16 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.lvs.report b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.lvs.report
new file mode 100644
index 0000000..59acc0f
--- /dev/null
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxbp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxbp_lp.sp ('sky130_fd_sc_lp__sdfxbp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.spice ('sky130_fd_sc_lp__sdfxbp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxbp_lp sky130_fd_sc_lp__sdfxbp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxbp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxbp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 35 35
+
+ Instances: 26 26 MN (4 pins)
+ 18 18 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 19 19
+
+ Instances: 2 2 MN (4 pins)
+ 10 10 MP (4 pins)
+ 12 12 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 28 28
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 19 19 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 12 12 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 28 28 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pex.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pex.spice
index 8f43b7d..dd7c39c 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pex.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_lp.pex.spice
-* Created: Fri Aug 28 11:30:31 2020
+* Created: Wed Sep 2 10:36:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pxi.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pxi.spice
index 7324d1e..a35c378 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pxi.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_lp.pxi.spice
-* Created: Fri Aug 28 11:30:31 2020
+* Created: Wed Sep 2 10:36:24 2020
*
x_PM_SKY130_FD_SC_LP__SDFXBP_LP%A_27_409# N_A_27_409#_M1037_s
+ N_A_27_409#_M1017_s N_A_27_409#_c_267_n N_A_27_409#_M1036_g
diff --git a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.spice b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.spice
index 65b2fc8..82ac742 100644
--- a/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.spice
+++ b/cells/sdfxbp/sky130_fd_sc_lp__sdfxbp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxbp_lp.spice
-* Created: Fri Aug 28 11:30:31 2020
+* Created: Wed Sep 2 10:36:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.lvs.report b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.lvs.report
new file mode 100644
index 0000000..61f07a3
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxtp_1.sp ('sky130_fd_sc_lp__sdfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.spice ('sky130_fd_sc_lp__sdfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxtp_1 sky130_fd_sc_lp__sdfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 16 16 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 33 32
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pex.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pex.spice
index 882f581..82c3a0f 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_1.pex.spice
-* Created: Fri Aug 28 11:30:40 2020
+* Created: Wed Sep 2 10:36:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pxi.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pxi.spice
index da1ac2a..94256de 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_1.pxi.spice
-* Created: Fri Aug 28 11:30:40 2020
+* Created: Wed Sep 2 10:36:32 2020
*
x_PM_SKY130_FD_SC_LP__SDFXTP_1%A_78_123# N_A_78_123#_M1017_s N_A_78_123#_M1020_s
+ N_A_78_123#_c_219_n N_A_78_123#_M1010_g N_A_78_123#_M1011_g
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.spice
index 6c5f011..d178462 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_1.spice
-* Created: Fri Aug 28 11:30:40 2020
+* Created: Wed Sep 2 10:36:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.lvs.report b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.lvs.report
new file mode 100644
index 0000000..25a3d47
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxtp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxtp_2.sp ('sky130_fd_sc_lp__sdfxtp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.spice ('sky130_fd_sc_lp__sdfxtp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:35 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxtp_2 sky130_fd_sc_lp__sdfxtp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxtp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxtp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 17 17 MN (4 pins)
+ 17 17 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 35 34
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pex.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pex.spice
index 984cf23..b3440c1 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_2.pex.spice
-* Created: Fri Aug 28 11:30:48 2020
+* Created: Wed Sep 2 10:36:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pxi.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pxi.spice
index 9c321b1..561aaea 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_2.pxi.spice
-* Created: Fri Aug 28 11:30:48 2020
+* Created: Wed Sep 2 10:36:39 2020
*
x_PM_SKY130_FD_SC_LP__SDFXTP_2%A_55_119# N_A_55_119#_M1008_s N_A_55_119#_M1029_s
+ N_A_55_119#_M1007_g N_A_55_119#_M1005_g N_A_55_119#_c_229_n
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.spice
index 550c92f..430abea 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_2.spice
-* Created: Fri Aug 28 11:30:48 2020
+* Created: Wed Sep 2 10:36:39 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.lvs.report b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.lvs.report
new file mode 100644
index 0000000..bc702e1
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxtp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxtp_4.sp ('sky130_fd_sc_lp__sdfxtp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.spice ('sky130_fd_sc_lp__sdfxtp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxtp_4 sky130_fd_sc_lp__sdfxtp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxtp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxtp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 25 25
+
+ Instances: 19 19 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 8 8 MN (4 pins)
+ 8 8 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pex.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pex.spice
index 97a4bb4..c308c83 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_4.pex.spice
-* Created: Fri Aug 28 11:30:57 2020
+* Created: Wed Sep 2 10:36:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pxi.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pxi.spice
index 8f66888..390b1a6 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_4.pxi.spice
-* Created: Fri Aug 28 11:30:57 2020
+* Created: Wed Sep 2 10:36:47 2020
*
x_PM_SKY130_FD_SC_LP__SDFXTP_4%A_91_123# N_A_91_123#_M1035_s N_A_91_123#_M1027_s
+ N_A_91_123#_M1037_g N_A_91_123#_M1007_g N_A_91_123#_c_245_n
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.spice
index 16871a0..7f8a09e 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_4.spice
-* Created: Fri Aug 28 11:30:57 2020
+* Created: Wed Sep 2 10:36:47 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.lvs.report b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.lvs.report
new file mode 100644
index 0000000..be1208b
--- /dev/null
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdfxtp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdfxtp_lp.sp ('sky130_fd_sc_lp__sdfxtp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.spice ('sky130_fd_sc_lp__sdfxtp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:50 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdfxtp_lp sky130_fd_sc_lp__sdfxtp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdfxtp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdfxtp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 31 31
+
+ Instances: 22 22 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 39 38
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 17 17
+
+ Instances: 2 2 MN (4 pins)
+ 8 8 MP (4 pins)
+ 10 10 SMN2 (4 pins)
+ 4 4 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 24 24
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 17 17 0 0
+
+ Instances: 2 2 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 10 10 0 0 SMN2
+ 4 4 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 24 24 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SCE SCD CLK VPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pex.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pex.spice
index 59c2b5d..e463d1f 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pex.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_lp.pex.spice
-* Created: Fri Aug 28 11:31:09 2020
+* Created: Wed Sep 2 10:36:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pxi.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pxi.spice
index 7e030b2..f9a0d7e 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pxi.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_lp.pxi.spice
-* Created: Fri Aug 28 11:31:09 2020
+* Created: Wed Sep 2 10:36:55 2020
*
x_PM_SKY130_FD_SC_LP__SDFXTP_LP%A_27_409# N_A_27_409#_M1032_s
+ N_A_27_409#_M1005_s N_A_27_409#_M1011_g N_A_27_409#_M1025_g
diff --git a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.spice b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.spice
index e4789c3..648384c 100644
--- a/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.spice
+++ b/cells/sdfxtp/sky130_fd_sc_lp__sdfxtp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdfxtp_lp.spice
-* Created: Fri Aug 28 11:31:09 2020
+* Created: Wed Sep 2 10:36:55 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.lvs.report b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.lvs.report
new file mode 100644
index 0000000..00e09bc
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdlclkp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdlclkp_1.sp ('sky130_fd_sc_lp__sdlclkp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.spice ('sky130_fd_sc_lp__sdlclkp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:36:59 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdlclkp_1 sky130_fd_sc_lp__sdlclkp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdlclkp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sdlclkp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pex.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pex.spice
index 57955f6..80fda24 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_1.pex.spice
-* Created: Fri Aug 28 11:31:22 2020
+* Created: Wed Sep 2 10:37:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pxi.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pxi.spice
index ed643cb..b05d919 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_1.pxi.spice
-* Created: Fri Aug 28 11:31:22 2020
+* Created: Wed Sep 2 10:37:03 2020
*
x_PM_SKY130_FD_SC_LP__SDLCLKP_1%SCE N_SCE_M1020_g N_SCE_M1011_g N_SCE_c_161_n
+ N_SCE_c_162_n N_SCE_c_163_n SCE SCE SCE SCE SCE N_SCE_c_165_n
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.spice
index 93626c7..fa0b949 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_1.spice
-* Created: Fri Aug 28 11:31:22 2020
+* Created: Wed Sep 2 10:37:03 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.lvs.report b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.lvs.report
new file mode 100644
index 0000000..cfea10d
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdlclkp_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdlclkp_2.sp ('sky130_fd_sc_lp__sdlclkp_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.spice ('sky130_fd_sc_lp__sdlclkp_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:07 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdlclkp_2 sky130_fd_sc_lp__sdlclkp_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdlclkp_2
+SOURCE CELL NAME: sky130_fd_sc_lp__sdlclkp_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 12 12 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 25 24
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 2.
+ 2 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pex.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pex.spice
index 108ca51..a822520 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_2.pex.spice
-* Created: Fri Aug 28 11:31:30 2020
+* Created: Wed Sep 2 10:37:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pxi.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pxi.spice
index 942607d..efd0e28 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_2.pxi.spice
-* Created: Fri Aug 28 11:31:30 2020
+* Created: Wed Sep 2 10:37:10 2020
*
x_PM_SKY130_FD_SC_LP__SDLCLKP_2%SCE N_SCE_c_168_n N_SCE_M1005_g N_SCE_M1021_g
+ N_SCE_c_170_n SCE SCE SCE SCE N_SCE_c_172_n N_SCE_c_173_n
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.spice
index de664fd..2318d6d 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_2.spice
-* Created: Fri Aug 28 11:31:30 2020
+* Created: Wed Sep 2 10:37:10 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.lvs.report b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.lvs.report
new file mode 100644
index 0000000..4ee633d
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdlclkp_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdlclkp_4.sp ('sky130_fd_sc_lp__sdlclkp_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.spice ('sky130_fd_sc_lp__sdlclkp_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:14 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdlclkp_4 sky130_fd_sc_lp__sdlclkp_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdlclkp_4
+SOURCE CELL NAME: sky130_fd_sc_lp__sdlclkp_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 18 18
+
+ Instances: 14 14 MN (4 pins)
+ 14 14 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 7 7 MN (4 pins)
+ 7 7 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 7 7 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 8 layout mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+ 8 source mos transistors were reduced to 2.
+ 6 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE GATE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pex.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pex.spice
index 65a51ca..5ce4a22 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_4.pex.spice
-* Created: Fri Aug 28 11:31:38 2020
+* Created: Wed Sep 2 10:37:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pxi.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pxi.spice
index e332a53..6b274e7 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_4.pxi.spice
-* Created: Fri Aug 28 11:31:38 2020
+* Created: Wed Sep 2 10:37:18 2020
*
x_PM_SKY130_FD_SC_LP__SDLCLKP_4%SCE N_SCE_M1022_g N_SCE_M1014_g N_SCE_c_181_n
+ N_SCE_c_182_n SCE SCE SCE SCE SCE N_SCE_c_184_n
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.spice
index 89956a9..9161fc9 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_4.spice
-* Created: Fri Aug 28 11:31:38 2020
+* Created: Wed Sep 2 10:37:18 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.lvs.report b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.lvs.report
new file mode 100644
index 0000000..91ba25f
--- /dev/null
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sdlclkp_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sdlclkp_lp.sp ('sky130_fd_sc_lp__sdlclkp_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.spice ('sky130_fd_sc_lp__sdlclkp_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:21 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sdlclkp_lp sky130_fd_sc_lp__sdlclkp_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sdlclkp_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__sdlclkp_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 24 24
+
+ Instances: 17 17 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 29 28
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 14 14
+
+ Instances: 1 1 MN (4 pins)
+ 7 7 MP (4 pins)
+ 8 8 SMN2 (4 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 18 18
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 14 14 0 0
+
+ Instances: 1 1 0 0 MN(NSHORT)
+ 7 7 0 0 MP(PHIGHVT)
+ 8 8 0 0 SMN2
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 18 18 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB GATE SCE CLK VPWR GCLK VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pex.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pex.spice
index b333f4e..37d0fec 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pex.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_lp.pex.spice
-* Created: Fri Aug 28 11:31:46 2020
+* Created: Wed Sep 2 10:37:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pxi.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pxi.spice
index 505db5a..d1b31dd 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pxi.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_lp.pxi.spice
-* Created: Fri Aug 28 11:31:46 2020
+* Created: Wed Sep 2 10:37:26 2020
*
x_PM_SKY130_FD_SC_LP__SDLCLKP_LP%GATE N_GATE_c_165_n N_GATE_M1011_g
+ N_GATE_M1018_g N_GATE_c_166_n N_GATE_M1027_g GATE N_GATE_c_167_n
diff --git a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.spice b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.spice
index ceda122..c499ba9 100644
--- a/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.spice
+++ b/cells/sdlclkp/sky130_fd_sc_lp__sdlclkp_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sdlclkp_lp.spice
-* Created: Fri Aug 28 11:31:46 2020
+* Created: Wed Sep 2 10:37:26 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.lvs.report b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.lvs.report
new file mode 100644
index 0000000..1333644
--- /dev/null
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_pargate_plv_14.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_pargate_plv_14.sp ('sky130_fd_sc_lp__sleep_pargate_plv_14')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.spice ('sky130_fd_sc_lp__sleep_pargate_plv_14')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:30 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_pargate_plv_14 sky130_fd_sc_lp__sleep_pargate_plv_14
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_14
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_14
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VIRTPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pex.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pex.spice
index 751bb8e..dc2ee08 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pex.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_14.pex.spice
-* Created: Fri Aug 28 11:31:55 2020
+* Created: Wed Sep 2 10:37:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pxi.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pxi.spice
index 1bb79d2..3d7d181 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pxi.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_14.pxi.spice
-* Created: Fri Aug 28 11:31:55 2020
+* Created: Wed Sep 2 10:37:33 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_14%SLEEP N_SLEEP_c_32_n N_SLEEP_M1000_g
+ N_SLEEP_c_33_n N_SLEEP_M1001_g N_SLEEP_c_34_n SLEEP SLEEP SLEEP SLEEP SLEEP
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.spice
index 0f54d38..f6abb9e 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_14.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_14.spice
-* Created: Fri Aug 28 11:31:55 2020
+* Created: Wed Sep 2 10:37:33 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.lvs.report b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.lvs.report
new file mode 100644
index 0000000..d67d02c
--- /dev/null
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_pargate_plv_21.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_pargate_plv_21.sp ('sky130_fd_sc_lp__sleep_pargate_plv_21')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.spice ('sky130_fd_sc_lp__sleep_pargate_plv_21')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_pargate_plv_21 sky130_fd_sc_lp__sleep_pargate_plv_21
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_21
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_21
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 3 layout mos transistors were reduced to 1.
+ 2 mos transistors were deleted by parallel reduction.
+ 3 source mos transistors were reduced to 1.
+ 2 mos transistors were deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VPWR VIRTPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pex.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pex.spice
index 839bc08..db38587 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pex.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_21.pex.spice
-* Created: Fri Aug 28 11:32:03 2020
+* Created: Wed Sep 2 10:37:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pxi.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pxi.spice
index 05b5c90..e18c319 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pxi.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_21.pxi.spice
-* Created: Fri Aug 28 11:32:03 2020
+* Created: Wed Sep 2 10:37:41 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_21%SLEEP N_SLEEP_c_38_n N_SLEEP_M1000_g
+ N_SLEEP_c_39_n N_SLEEP_M1001_g N_SLEEP_c_40_n N_SLEEP_M1002_g N_SLEEP_c_41_n
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.spice
index d5df853..1869f3a 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_21.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_21.spice
-* Created: Fri Aug 28 11:32:03 2020
+* Created: Wed Sep 2 10:37:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.lvs.report b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.lvs.report
new file mode 100644
index 0000000..b954edf
--- /dev/null
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_pargate_plv_28.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_pargate_plv_28.sp ('sky130_fd_sc_lp__sleep_pargate_plv_28')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.spice ('sky130_fd_sc_lp__sleep_pargate_plv_28')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:45 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_pargate_plv_28 sky130_fd_sc_lp__sleep_pargate_plv_28
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_28
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_28
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 1.
+ 3 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 1.
+ 3 mos transistors were deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VIRTPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pex.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pex.spice
index cd5d89f..21f6a86 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pex.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_28.pex.spice
-* Created: Fri Aug 28 11:32:16 2020
+* Created: Wed Sep 2 10:37:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pxi.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pxi.spice
index fdbe22f..3fc194b 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pxi.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_28.pxi.spice
-* Created: Fri Aug 28 11:32:16 2020
+* Created: Wed Sep 2 10:37:49 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_28%SLEEP N_SLEEP_c_42_n N_SLEEP_M1000_g
+ N_SLEEP_c_43_n N_SLEEP_M1001_g N_SLEEP_c_44_n N_SLEEP_M1002_g N_SLEEP_c_45_n
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.spice
index e849a28..67f6053 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_28.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_28.spice
-* Created: Fri Aug 28 11:32:16 2020
+* Created: Wed Sep 2 10:37:49 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.lvs.report b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.lvs.report
new file mode 100644
index 0000000..74a7196
--- /dev/null
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.lvs.report
@@ -0,0 +1,463 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_pargate_plv_7.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_pargate_plv_7.sp ('sky130_fd_sc_lp__sleep_pargate_plv_7')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.spice ('sky130_fd_sc_lp__sleep_pargate_plv_7')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:37:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_pargate_plv_7 sky130_fd_sc_lp__sleep_pargate_plv_7
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_7
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_pargate_plv_7
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 1 1 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 2 1
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VPWR VIRTPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pex.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pex.spice
index cdb41ed..00f9779 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pex.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_7.pex.spice
-* Created: Fri Aug 28 11:32:28 2020
+* Created: Wed Sep 2 10:37:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pxi.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pxi.spice
index 9b4cb9d..2d3b606 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pxi.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_7.pxi.spice
-* Created: Fri Aug 28 11:32:28 2020
+* Created: Wed Sep 2 10:37:57 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_PARGATE_PLV_7%SLEEP N_SLEEP_c_31_n N_SLEEP_M1000_g
+ SLEEP SLEEP SLEEP SLEEP SLEEP N_SLEEP_c_33_n
diff --git a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.spice b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.spice
index d40f204..4c1439a 100644
--- a/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.spice
+++ b/cells/sleep_pargate_plv/sky130_fd_sc_lp__sleep_pargate_plv_7.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_pargate_plv_7.spice
-* Created: Fri Aug 28 11:32:28 2020
+* Created: Wed Sep 2 10:37:57 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.lvs.report b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.lvs.report
new file mode 100644
index 0000000..8a80e75
--- /dev/null
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_sergate_plv_14.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_sergate_plv_14.sp ('sky130_fd_sc_lp__sleep_sergate_plv_14')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.spice ('sky130_fd_sc_lp__sleep_sergate_plv_14')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:01 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_sergate_plv_14 sky130_fd_sc_lp__sleep_sergate_plv_14
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_14
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_14
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 2 2 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 3 2
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 2 layout mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+ 2 source mos transistors were reduced to 1.
+ 1 mos transistor was deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VIRTPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pex.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pex.spice
index 783b595..8edefa8 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pex.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_14.pex.spice
-* Created: Fri Aug 28 11:32:37 2020
+* Created: Wed Sep 2 10:38:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pxi.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pxi.spice
index a6cdfcf..dfdef47 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pxi.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_14.pxi.spice
-* Created: Fri Aug 28 11:32:37 2020
+* Created: Wed Sep 2 10:38:05 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14%SLEEP N_SLEEP_c_32_n N_SLEEP_c_33_n
+ N_SLEEP_c_34_n N_SLEEP_M1000_g N_SLEEP_c_35_n N_SLEEP_M1001_g SLEEP SLEEP
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.spice
index 0e6b9b8..936972a 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_14.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_14.spice
-* Created: Fri Aug 28 11:32:37 2020
+* Created: Wed Sep 2 10:38:05 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.lvs.report b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.lvs.report
new file mode 100644
index 0000000..c6c432c
--- /dev/null
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_sergate_plv_21.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_sergate_plv_21.sp ('sky130_fd_sc_lp__sleep_sergate_plv_21')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.spice ('sky130_fd_sc_lp__sleep_sergate_plv_21')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:08 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_sergate_plv_21 sky130_fd_sc_lp__sleep_sergate_plv_21
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_21
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_21
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 3 3 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 4 3
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 3 layout mos transistors were reduced to 1.
+ 2 mos transistors were deleted by parallel reduction.
+ 3 source mos transistors were reduced to 1.
+ 2 mos transistors were deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VPWR VIRTPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pex.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pex.spice
index a1b5e18..019747f 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pex.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_21.pex.spice
-* Created: Fri Aug 28 11:32:44 2020
+* Created: Wed Sep 2 10:38:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pxi.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pxi.spice
index 4c48a42..0c7e0df 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pxi.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_21.pxi.spice
-* Created: Fri Aug 28 11:32:44 2020
+* Created: Wed Sep 2 10:38:12 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_21%SLEEP N_SLEEP_c_42_n N_SLEEP_c_43_n
+ N_SLEEP_M1002_g N_SLEEP_c_44_n N_SLEEP_c_45_n N_SLEEP_M1000_g N_SLEEP_c_46_n
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.spice
index 7f3cca2..925e1ff 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_21.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_21.spice
-* Created: Fri Aug 28 11:32:44 2020
+* Created: Wed Sep 2 10:38:12 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.lvs.report b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.lvs.report
new file mode 100644
index 0000000..7761e74
--- /dev/null
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sleep_sergate_plv_28.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sleep_sergate_plv_28.sp ('sky130_fd_sc_lp__sleep_sergate_plv_28')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.spice ('sky130_fd_sc_lp__sleep_sergate_plv_28')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:15 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sleep_sergate_plv_28 sky130_fd_sc_lp__sleep_sergate_plv_28
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_28
+SOURCE CELL NAME: sky130_fd_sc_lp__sleep_sergate_plv_28
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 5 4 *
+
+ Instances: 4 4 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 5 4
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 4 4
+
+ Nets: 4 4
+
+ Instances: 1 1 MP (4 pins)
+ ------ ------
+ Total Inst: 1 1
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 4 4 0 0
+
+ Nets: 4 4 0 0
+
+ Instances: 1 1 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 1 1 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 4 layout mos transistors were reduced to 1.
+ 3 mos transistors were deleted by parallel reduction.
+ 4 source mos transistors were reduced to 1.
+ 3 mos transistors were deleted by parallel reduction.
+
+ 1 layout net had all its pins removed and was deleted.
+
+
+o Initial Correspondence Points:
+
+ Ports: VPB SLEEP VIRTPWR VPWR
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pex.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pex.spice
index 313b668..dc8f56e 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pex.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_28.pex.spice
-* Created: Fri Aug 28 11:32:53 2020
+* Created: Wed Sep 2 10:38:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pxi.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pxi.spice
index 00a81eb..aaf20cf 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pxi.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_28.pxi.spice
-* Created: Fri Aug 28 11:32:53 2020
+* Created: Wed Sep 2 10:38:19 2020
*
x_PM_SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_28%SLEEP N_SLEEP_c_39_n N_SLEEP_c_45_n
+ N_SLEEP_c_40_n N_SLEEP_c_41_n N_SLEEP_M1000_g N_SLEEP_c_48_n N_SLEEP_c_49_n
diff --git a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.spice b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.spice
index 642f1e3..9f533ad 100644
--- a/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.spice
+++ b/cells/sleep_sergate_plv/sky130_fd_sc_lp__sleep_sergate_plv_28.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sleep_sergate_plv_28.spice
-* Created: Fri Aug 28 11:32:53 2020
+* Created: Wed Sep 2 10:38:19 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.lvs.report b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.lvs.report
new file mode 100644
index 0000000..9c73695
--- /dev/null
+++ b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srdlrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srdlrtp_1.sp ('sky130_fd_sc_lp__srdlrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.spice ('sky130_fd_sc_lp__srdlrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:23 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srdlrtp_1 sky130_fd_sc_lp__srdlrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srdlrtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srdlrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 16 16 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 37 36
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 18 18
+
+ Instances: 4 4 MN (4 pins)
+ 10 10 MP (4 pins)
+ 3 3 SMN2 (4 pins)
+ 2 2 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ ------ ------
+ Total Inst: 23 23
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 18 18 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 10 10 0 0 MP(PHIGHVT)
+ 3 3 0 0 SMN2
+ 2 2 0 0 SMN3
+ 3 3 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ ------- ------- --------- ---------
+ Total Inst: 23 23 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D RESET_B GATE SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pex.spice b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pex.spice
index e6344cd..3e5fe37 100644
--- a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pex.spice
+++ b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlrtp_1.pex.spice
-* Created: Fri Aug 28 11:33:01 2020
+* Created: Wed Sep 2 10:38:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pxi.spice b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pxi.spice
index 0c8b171..e902512 100644
--- a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pxi.spice
+++ b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlrtp_1.pxi.spice
-* Created: Fri Aug 28 11:33:01 2020
+* Created: Wed Sep 2 10:38:27 2020
*
x_PM_SKY130_FD_SC_LP__SRDLRTP_1%D N_D_M1005_g N_D_M1032_g D N_D_c_213_n
+ PM_SKY130_FD_SC_LP__SRDLRTP_1%D
diff --git a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.spice b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.spice
index 83b4981..9620e69 100644
--- a/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.spice
+++ b/cells/srdlrtp/sky130_fd_sc_lp__srdlrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlrtp_1.spice
-* Created: Fri Aug 28 11:33:01 2020
+* Created: Wed Sep 2 10:38:27 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.lvs.report b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.lvs.report
new file mode 100644
index 0000000..004d0c0
--- /dev/null
+++ b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srdlstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srdlstp_1.sp ('sky130_fd_sc_lp__srdlstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.spice ('sky130_fd_sc_lp__srdlstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:31 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srdlstp_1 sky130_fd_sc_lp__srdlstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srdlstp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srdlstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 30 30
+
+ Instances: 20 20 MN (4 pins)
+ 15 15 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 36 35
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 10 10
+
+ Nets: 18 18
+
+ Instances: 4 4 MN (4 pins)
+ 9 9 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 3 3 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 10 10 0 0
+
+ Nets: 18 18 0 0
+
+ Instances: 4 4 0 0 MN(NSHORT)
+ 9 9 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 1 1 0 0 SMN3
+ 3 3 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D SET_B GATE SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pex.spice b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pex.spice
index 86b6a71..747b39d 100644
--- a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pex.spice
+++ b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlstp_1.pex.spice
-* Created: Fri Aug 28 11:33:10 2020
+* Created: Wed Sep 2 10:38:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pxi.spice b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pxi.spice
index cf373fa..be2ee2f 100644
--- a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pxi.spice
+++ b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlstp_1.pxi.spice
-* Created: Fri Aug 28 11:33:10 2020
+* Created: Wed Sep 2 10:38:34 2020
*
x_PM_SKY130_FD_SC_LP__SRDLSTP_1%D N_D_c_231_n N_D_M1024_g N_D_M1028_g
+ N_D_c_234_n D D N_D_c_235_n N_D_c_236_n PM_SKY130_FD_SC_LP__SRDLSTP_1%D
diff --git a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.spice b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.spice
index 3e226fb..601c205 100644
--- a/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.spice
+++ b/cells/srdlstp/sky130_fd_sc_lp__srdlstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlstp_1.spice
-* Created: Fri Aug 28 11:33:10 2020
+* Created: Wed Sep 2 10:38:34 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.lvs.report b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.lvs.report
new file mode 100644
index 0000000..77d338b
--- /dev/null
+++ b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srdlxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srdlxtp_1.sp ('sky130_fd_sc_lp__srdlxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.spice ('sky130_fd_sc_lp__srdlxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:38 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srdlxtp_1 sky130_fd_sc_lp__srdlxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srdlxtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srdlxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 24 24
+
+ Instances: 15 15 MN (4 pins)
+ 12 12 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 9 9
+
+ Nets: 16 16
+
+ Instances: 5 5 MN (4 pins)
+ 8 8 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 2 2 SMN3 (5 pins)
+ 2 2 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 19 19
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 9 9 0 0
+
+ Nets: 16 16 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 8 8 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 2 2 0 0 SMN3
+ 2 2 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 19 19 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB D GATE SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pex.spice b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pex.spice
index 7f6f103..9a4b8b4 100644
--- a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pex.spice
+++ b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlxtp_1.pex.spice
-* Created: Fri Aug 28 11:33:22 2020
+* Created: Wed Sep 2 10:38:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pxi.spice b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pxi.spice
index 6c800b5..dafa56e 100644
--- a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pxi.spice
+++ b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlxtp_1.pxi.spice
-* Created: Fri Aug 28 11:33:22 2020
+* Created: Wed Sep 2 10:38:42 2020
*
x_PM_SKY130_FD_SC_LP__SRDLXTP_1%A_84_153# N_A_84_153#_M1023_s
+ N_A_84_153#_M1026_d N_A_84_153#_M1013_g N_A_84_153#_M1004_g
diff --git a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.spice b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.spice
index bae0927..36c38f9 100644
--- a/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.spice
+++ b/cells/srdlxtp/sky130_fd_sc_lp__srdlxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srdlxtp_1.spice
-* Created: Fri Aug 28 11:33:22 2020
+* Created: Wed Sep 2 10:38:42 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.lvs.report b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.lvs.report
new file mode 100644
index 0000000..833d061
--- /dev/null
+++ b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sregrbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sregrbp_1.sp ('sky130_fd_sc_lp__sregrbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.spice ('sky130_fd_sc_lp__sregrbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sregrbp_1 sky130_fd_sc_lp__sregrbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sregrbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sregrbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 33 33
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 21 21
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 21 21 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK ASYNC VPWR Q Q_N VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pex.spice b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pex.spice
index 8a281cb..20028e8 100644
--- a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pex.spice
+++ b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregrbp_1.pex.spice
-* Created: Fri Aug 28 11:33:35 2020
+* Created: Wed Sep 2 10:38:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pxi.spice b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pxi.spice
index 56dfca9..6c4e9ab 100644
--- a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pxi.spice
+++ b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregrbp_1.pxi.spice
-* Created: Fri Aug 28 11:33:35 2020
+* Created: Wed Sep 2 10:38:50 2020
*
x_PM_SKY130_FD_SC_LP__SREGRBP_1%SCE N_SCE_M1022_g N_SCE_M1041_g N_SCE_c_296_n
+ N_SCE_M1000_g N_SCE_M1024_g N_SCE_c_298_n N_SCE_c_299_n N_SCE_c_300_n SCE SCE
diff --git a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.spice b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.spice
index 0b70c0a..2284f7b 100644
--- a/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.spice
+++ b/cells/sregrbp/sky130_fd_sc_lp__sregrbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregrbp_1.spice
-* Created: Fri Aug 28 11:33:35 2020
+* Created: Wed Sep 2 10:38:50 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.lvs.report b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.lvs.report
new file mode 100644
index 0000000..7634ef9
--- /dev/null
+++ b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__sregsbp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__sregsbp_1.sp ('sky130_fd_sc_lp__sregsbp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.spice ('sky130_fd_sc_lp__sregsbp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:38:54 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__sregsbp_1 sky130_fd_sc_lp__sregsbp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__sregsbp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__sregsbp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 33 33
+
+ Instances: 22 22 MN (4 pins)
+ 22 22 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 45 44
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 21 21
+
+ Instances: 8 8 MN (4 pins)
+ 12 12 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 32 32
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 21 21 0 0
+
+ Instances: 8 8 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 32 32 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD CLK ASYNC VPWR Q_N Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pex.spice b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pex.spice
index ee03181..a984161 100644
--- a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pex.spice
+++ b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregsbp_1.pex.spice
-* Created: Fri Aug 28 11:33:43 2020
+* Created: Wed Sep 2 10:38:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pxi.spice b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pxi.spice
index 2135a40..3bc36de 100644
--- a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pxi.spice
+++ b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregsbp_1.pxi.spice
-* Created: Fri Aug 28 11:33:43 2020
+* Created: Wed Sep 2 10:38:58 2020
*
x_PM_SKY130_FD_SC_LP__SREGSBP_1%SCE N_SCE_M1022_g N_SCE_M1041_g N_SCE_c_295_n
+ N_SCE_M1000_g N_SCE_M1024_g N_SCE_c_297_n N_SCE_c_298_n N_SCE_c_299_n SCE SCE
diff --git a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.spice b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.spice
index f4acc81..e211d18 100644
--- a/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.spice
+++ b/cells/sregsbp/sky130_fd_sc_lp__sregsbp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__sregsbp_1.spice
-* Created: Fri Aug 28 11:33:43 2020
+* Created: Wed Sep 2 10:38:58 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.lvs.report b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.lvs.report
new file mode 100644
index 0000000..4c1f472
--- /dev/null
+++ b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.lvs.report
@@ -0,0 +1,476 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srsdfrtn_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srsdfrtn_1.sp ('sky130_fd_sc_lp__srsdfrtn_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.spice ('sky130_fd_sc_lp__srsdfrtn_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:02 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srsdfrtn_1 sky130_fd_sc_lp__srsdfrtn_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srsdfrtn_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srsdfrtn_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 43 43
+
+ Instances: 29 29 MN (4 pins)
+ 25 25 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 55 54
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 5 5 MN (4 pins)
+ 12 12 MP (4 pins)
+ 4 4 SMN2 (4 pins)
+ 2 2 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ 1 1 SMP3 (5 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 31 31
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 5 5 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 4 4 0 0 SMN2
+ 2 2 0 0 SMN3
+ 5 5 0 0 SMP2
+ 1 1 0 0 SMP3
+ 1 1 0 0 SPMN_2_1_1_1
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 31 31 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK_N SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pex.spice b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pex.spice
index d9ee630..64894be 100644
--- a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pex.spice
+++ b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtn_1.pex.spice
-* Created: Fri Aug 28 11:33:51 2020
+* Created: Wed Sep 2 10:39:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pxi.spice b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pxi.spice
index 99f2a78..3adff66 100644
--- a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pxi.spice
+++ b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtn_1.pxi.spice
-* Created: Fri Aug 28 11:33:51 2020
+* Created: Wed Sep 2 10:39:07 2020
*
x_PM_SKY130_FD_SC_LP__SRSDFRTN_1%SCE N_SCE_M1001_g N_SCE_M1016_g N_SCE_c_363_n
+ N_SCE_c_364_n N_SCE_M1025_g N_SCE_c_365_n N_SCE_M1023_g N_SCE_c_366_n
@@ -47,8 +47,8 @@
+ N_A_666_89#_c_1076_n PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_666_89#
x_PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1343_51# N_A_1343_51#_M1032_d
+ N_A_1343_51#_M1044_s N_A_1343_51#_M1029_d N_A_1343_51#_M1015_d
-+ N_A_1343_51#_M1035_g N_A_1343_51#_c_1263_n N_A_1343_51#_M1010_g
-+ N_A_1343_51#_M1012_g N_A_1343_51#_c_1266_n N_A_1343_51#_c_1267_n
++ N_A_1343_51#_M1012_g N_A_1343_51#_c_1263_n N_A_1343_51#_M1010_g
++ N_A_1343_51#_M1035_g N_A_1343_51#_c_1266_n N_A_1343_51#_c_1267_n
+ N_A_1343_51#_c_1268_n N_A_1343_51#_c_1269_n N_A_1343_51#_c_1270_n
+ N_A_1343_51#_c_1271_n N_A_1343_51#_c_1272_n N_A_1343_51#_c_1315_n
+ N_A_1343_51#_c_1273_n N_A_1343_51#_c_1274_n N_A_1343_51#_c_1275_n
@@ -153,9 +153,9 @@
+ N_noxref_32_c_3023_n N_noxref_32_c_3024_n
+ PM_SKY130_FD_SC_LP__SRSDFRTN_1%noxref_32
x_PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1009_107# N_A_1009_107#_M1041_s
-+ N_A_1009_107#_M1035_s N_A_1009_107#_c_3056_n
++ N_A_1009_107#_M1012_s N_A_1009_107#_c_3056_n
+ PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1009_107#
-x_PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1453_77# N_A_1453_77#_M1012_d
+x_PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1453_77# N_A_1453_77#_M1035_d
+ N_A_1453_77#_M1007_d N_A_1453_77#_c_3075_n N_A_1453_77#_c_3076_n
+ N_A_1453_77#_c_3077_n PM_SKY130_FD_SC_LP__SRSDFRTN_1%A_1453_77#
cc_1 VNB N_SCE_M1001_g 0.0375416f $X=-0.19 $Y=-0.245 $X2=0.485 $Y2=0.485
@@ -218,7 +218,7 @@
cc_58 VNB N_A_666_89#_c_1076_n 0.00463183f $X=-0.19 $Y=-0.245 $X2=0 $Y2=0
cc_59 VNB N_A_1343_51#_c_1263_n 0.0126036f $X=-0.19 $Y=-0.245 $X2=1.45 $Y2=1.015
cc_60 VNB N_A_1343_51#_M1010_g 0.0369257f $X=-0.19 $Y=-0.245 $X2=0.75 $Y2=1.165
-cc_61 VNB N_A_1343_51#_M1012_g 0.0313245f $X=-0.19 $Y=-0.245 $X2=0.635 $Y2=1.21
+cc_61 VNB N_A_1343_51#_M1035_g 0.0313245f $X=-0.19 $Y=-0.245 $X2=0.635 $Y2=1.21
cc_62 VNB N_A_1343_51#_c_1266_n 0.0197839f $X=-0.19 $Y=-0.245 $X2=0 $Y2=0
cc_63 VNB N_A_1343_51#_c_1267_n 0.0094458f $X=-0.19 $Y=-0.245 $X2=0 $Y2=0
cc_64 VNB N_A_1343_51#_c_1268_n 9.88085e-19 $X=-0.19 $Y=-0.245 $X2=0.75 $Y2=1.26
@@ -804,9 +804,9 @@
+ $Y2=0
cc_523 N_RESET_B_c_608_n N_A_1343_51#_M1010_g 0.00848994f $X=7.07 $Y=1.695 $X2=0
+ $Y2=0
-cc_524 N_RESET_B_c_595_n N_A_1343_51#_M1012_g 0.00378728f $X=6.9 $Y=0.34 $X2=0
+cc_524 N_RESET_B_c_595_n N_A_1343_51#_M1035_g 0.00378728f $X=6.9 $Y=0.34 $X2=0
+ $Y2=0
-cc_525 N_RESET_B_c_597_n N_A_1343_51#_M1012_g 0.00616162f $X=6.985 $Y=1.61 $X2=0
+cc_525 N_RESET_B_c_597_n N_A_1343_51#_M1035_g 0.00616162f $X=6.985 $Y=1.61 $X2=0
+ $Y2=0
cc_526 N_RESET_B_c_595_n N_A_1343_51#_c_1266_n 0.0146065f $X=6.9 $Y=0.34 $X2=0
+ $Y2=0
@@ -1037,7 +1037,7 @@
+ $Y2=0
cc_645 N_RESET_B_c_596_n N_noxref_32_c_3024_n 0.00123572f $X=4.77 $Y=0.34 $X2=0
+ $Y2=0
-cc_646 N_RESET_B_c_595_n N_A_1009_107#_M1035_s 0.0027844f $X=6.9 $Y=0.34 $X2=0
+cc_646 N_RESET_B_c_595_n N_A_1009_107#_M1012_s 0.0027844f $X=6.9 $Y=0.34 $X2=0
+ $Y2=0
cc_647 N_RESET_B_c_586_n N_A_1009_107#_c_3056_n 0.00420455f $X=4.86 $Y=1.145
+ $X2=0 $Y2=0
@@ -2004,7 +2004,7 @@
+ $Y2=0
cc_1132 N_A_1343_51#_c_1366_p N_VGND_c_2837_n 0.00323373f $X=12.425 $Y=0.7 $X2=0
+ $Y2=0
-cc_1133 N_A_1343_51#_M1012_g N_VGND_c_2841_n 0.00540915f $X=7.19 $Y=0.595 $X2=0
+cc_1133 N_A_1343_51#_M1035_g N_VGND_c_2841_n 0.00540915f $X=7.19 $Y=0.595 $X2=0
+ $Y2=0
cc_1134 N_A_1343_51#_c_1266_n N_VGND_c_2841_n 0.00388395f $X=6.795 $Y=0.915
+ $X2=0 $Y2=0
@@ -2018,7 +2018,7 @@
+ $Y2=0
cc_1139 N_A_1343_51#_M1032_d N_VGND_c_2845_n 0.00232718f $X=9.56 $Y=0.235 $X2=0
+ $Y2=0
-cc_1140 N_A_1343_51#_M1012_g N_VGND_c_2845_n 0.0054106f $X=7.19 $Y=0.595 $X2=0
+cc_1140 N_A_1343_51#_M1035_g N_VGND_c_2845_n 0.0054106f $X=7.19 $Y=0.595 $X2=0
+ $Y2=0
cc_1141 N_A_1343_51#_c_1266_n N_VGND_c_2845_n 0.0054106f $X=6.795 $Y=0.915 $X2=0
+ $Y2=0
@@ -2034,13 +2034,13 @@
+ $Y2=0
cc_1147 N_A_1343_51#_c_1282_n N_VGND_c_2845_n 0.0722643f $X=13.325 $Y=0.435
+ $X2=0 $Y2=0
-cc_1148 N_A_1343_51#_M1012_g N_VGND_c_2848_n 0.00284344f $X=7.19 $Y=0.595 $X2=0
+cc_1148 N_A_1343_51#_M1035_g N_VGND_c_2848_n 0.00284344f $X=7.19 $Y=0.595 $X2=0
+ $Y2=0
cc_1149 N_A_1343_51#_c_1266_n N_A_1009_107#_c_3056_n 0.00235098f $X=6.795
+ $Y=0.915 $X2=0 $Y2=0
cc_1150 N_A_1343_51#_c_1269_n N_A_1453_77#_c_3075_n 0.0551213f $X=8.355 $Y=0.96
+ $X2=0 $Y2=0
-cc_1151 N_A_1343_51#_M1012_g N_A_1453_77#_c_3076_n 0.00436134f $X=7.19 $Y=0.595
+cc_1151 N_A_1343_51#_M1035_g N_A_1453_77#_c_3076_n 0.00436134f $X=7.19 $Y=0.595
+ $X2=0 $Y2=0
cc_1152 N_A_1343_51#_c_1270_n N_A_1453_77#_c_3076_n 0.025806f $X=7.57 $Y=0.96
+ $X2=0 $Y2=0
diff --git a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.spice b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.spice
index 12635c8..9f2cfba 100644
--- a/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.spice
+++ b/cells/srsdfrtn/sky130_fd_sc_lp__srsdfrtn_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtn_1.spice
-* Created: Fri Aug 28 11:33:51 2020
+* Created: Wed Sep 2 10:39:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
@@ -49,10 +49,10 @@
MM1034 N_A_305_97#_M1034_d N_A_666_89#_M1034_g A_1201_215# VNB NSHORT L=0.15
+ W=0.42 AD=0.1155 AS=0.0441 PD=1.39 PS=0.63 NRD=0 NRS=14.28 M=1 R=2.8
+ SA=75001.1 SB=75000.2 A=0.063 P=1.14 MULT=1
-MM1035 A_1373_77# N_A_1343_51#_M1035_g N_A_1009_107#_M1035_s VNB NSHORT L=0.15
+MM1012 A_1373_77# N_A_1343_51#_M1012_g N_A_1009_107#_M1012_s VNB NSHORT L=0.15
+ W=0.42 AD=0.0525 AS=0.1239 PD=0.67 PS=1.43 NRD=19.992 NRS=2.856 M=1 R=2.8
+ SA=75000.2 SB=75000.6 A=0.063 P=1.14 MULT=1
-MM1012 N_A_1453_77#_M1012_d N_A_1343_51#_M1012_g A_1373_77# VNB NSHORT L=0.15
+MM1035 N_A_1453_77#_M1035_d N_A_1343_51#_M1035_g A_1373_77# VNB NSHORT L=0.15
+ W=0.42 AD=0.1155 AS=0.0525 PD=1.39 PS=0.67 NRD=0 NRS=19.992 M=1 R=2.8
+ SA=75000.6 SB=75000.2 A=0.063 P=1.14 MULT=1
MM1007 N_A_1453_77#_M1007_d N_RESET_B_M1007_g N_VGND_M1007_s VNB NSHORT L=0.15
diff --git a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.lvs.report b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.lvs.report
new file mode 100644
index 0000000..a0e8819
--- /dev/null
+++ b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.lvs.report
@@ -0,0 +1,474 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srsdfrtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srsdfrtp_1.sp ('sky130_fd_sc_lp__srsdfrtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.spice ('sky130_fd_sc_lp__srsdfrtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:10 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srsdfrtp_1 sky130_fd_sc_lp__srsdfrtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srsdfrtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srsdfrtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 41 41
+
+ Instances: 28 28 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 22 22
+
+ Instances: 6 6 MN (4 pins)
+ 12 12 MP (4 pins)
+ 2 2 SMN2 (4 pins)
+ 3 3 SMN3 (5 pins)
+ 6 6 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1 (6 pins)
+ 1 1 SPMN((2+2)*1) (7 pins)
+ ------ ------
+ Total Inst: 31 31
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 22 22 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 2 2 0 0 SMN2
+ 3 3 0 0 SMN3
+ 6 6 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1
+ 1 1 0 0 SPMN((2+2)*1)
+ ------- ------- --------- ---------
+ Total Inst: 31 31 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD RESET_B CLK SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pex.spice b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pex.spice
index 1132da8..076c029 100644
--- a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pex.spice
+++ b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtp_1.pex.spice
-* Created: Fri Aug 28 11:34:00 2020
+* Created: Wed Sep 2 10:39:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pxi.spice b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pxi.spice
index 002720a..a5ec2e4 100644
--- a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pxi.spice
+++ b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtp_1.pxi.spice
-* Created: Fri Aug 28 11:34:00 2020
+* Created: Wed Sep 2 10:39:14 2020
*
x_PM_SKY130_FD_SC_LP__SRSDFRTP_1%SCE N_SCE_M1003_g N_SCE_M1034_g N_SCE_c_360_n
+ N_SCE_c_365_n N_SCE_M1017_g N_SCE_M1040_g N_SCE_c_362_n N_SCE_c_367_n SCE SCE
diff --git a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.spice b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.spice
index fc4c789..86779e7 100644
--- a/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.spice
+++ b/cells/srsdfrtp/sky130_fd_sc_lp__srsdfrtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfrtp_1.spice
-* Created: Fri Aug 28 11:34:00 2020
+* Created: Wed Sep 2 10:39:14 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.lvs.report b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.lvs.report
new file mode 100644
index 0000000..c3da019
--- /dev/null
+++ b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.lvs.report
@@ -0,0 +1,472 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srsdfstp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srsdfstp_1.sp ('sky130_fd_sc_lp__srsdfstp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.spice ('sky130_fd_sc_lp__srsdfstp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srsdfstp_1 sky130_fd_sc_lp__srsdfstp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srsdfstp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srsdfstp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 41 41
+
+ Instances: 28 28 MN (4 pins)
+ 24 24 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 53 52
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 12 12
+
+ Nets: 23 23
+
+ Instances: 6 6 MN (4 pins)
+ 12 12 MP (4 pins)
+ 7 7 SMN2 (4 pins)
+ 1 1 SMN3 (5 pins)
+ 6 6 SMP2 (4 pins)
+ 1 1 SPMN_2_1_1_1 (7 pins)
+ ------ ------
+ Total Inst: 33 33
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 12 12 0 0
+
+ Nets: 23 23 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 12 12 0 0 MP(PHIGHVT)
+ 7 7 0 0 SMN2
+ 1 1 0 0 SMN3
+ 6 6 0 0 SMP2
+ 1 1 0 0 SPMN_2_1_1_1
+ ------- ------- --------- ---------
+ Total Inst: 33 33 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCD D SCE SET_B CLK SLEEP_B VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pex.spice b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pex.spice
index c41081d..dd753a5 100644
--- a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pex.spice
+++ b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfstp_1.pex.spice
-* Created: Fri Aug 28 11:34:09 2020
+* Created: Wed Sep 2 10:39:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pxi.spice b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pxi.spice
index c7e3614..165dfbb 100644
--- a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pxi.spice
+++ b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfstp_1.pxi.spice
-* Created: Fri Aug 28 11:34:09 2020
+* Created: Wed Sep 2 10:39:22 2020
*
x_PM_SKY130_FD_SC_LP__SRSDFSTP_1%SCD N_SCD_M1001_g N_SCD_M1000_g N_SCD_c_360_n
+ N_SCD_c_365_n SCD SCD N_SCD_c_362_n PM_SKY130_FD_SC_LP__SRSDFSTP_1%SCD
diff --git a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.spice b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.spice
index b368eda..48a1f61 100644
--- a/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.spice
+++ b/cells/srsdfstp/sky130_fd_sc_lp__srsdfstp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfstp_1.spice
-* Created: Fri Aug 28 11:34:09 2020
+* Created: Wed Sep 2 10:39:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.lvs.report b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.lvs.report
new file mode 100644
index 0000000..d7da7b2
--- /dev/null
+++ b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.lvs.report
@@ -0,0 +1,470 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__srsdfxtp_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__srsdfxtp_1.sp ('sky130_fd_sc_lp__srsdfxtp_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.spice ('sky130_fd_sc_lp__srsdfxtp_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:25 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__srsdfxtp_1 sky130_fd_sc_lp__srsdfxtp_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__srsdfxtp_1
+SOURCE CELL NAME: sky130_fd_sc_lp__srsdfxtp_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 34 34
+
+ Instances: 22 22 MN (4 pins)
+ 19 19 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 42 41
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 11 11
+
+ Nets: 20 20
+
+ Instances: 6 6 MN (4 pins)
+ 9 9 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ 2 2 SMN3 (5 pins)
+ 5 5 SMP2 (4 pins)
+ ------ ------
+ Total Inst: 27 27
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 11 11 0 0
+
+ Nets: 20 20 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 9 9 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ 2 2 0 0 SMN3
+ 5 5 0 0 SMP2
+ ------- ------- --------- ---------
+ Total Inst: 27 27 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB SCE D SCD SLEEP_B CLK VPWR KAPWR Q VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pex.spice b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pex.spice
index 8f14d36..6ab3bf2 100644
--- a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pex.spice
+++ b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfxtp_1.pex.spice
-* Created: Fri Aug 28 11:34:18 2020
+* Created: Wed Sep 2 10:39:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pxi.spice b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pxi.spice
index bb7e30b..15785a5 100644
--- a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pxi.spice
+++ b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfxtp_1.pxi.spice
-* Created: Fri Aug 28 11:34:18 2020
+* Created: Wed Sep 2 10:39:30 2020
*
x_PM_SKY130_FD_SC_LP__SRSDFXTP_1%SCE N_SCE_c_292_n N_SCE_c_302_n N_SCE_M1030_g
+ N_SCE_M1040_g N_SCE_c_303_n N_SCE_c_304_n N_SCE_c_305_n N_SCE_M1000_g
diff --git a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.spice b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.spice
index 3ebee89..e76da0c 100644
--- a/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.spice
+++ b/cells/srsdfxtp/sky130_fd_sc_lp__srsdfxtp_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__srsdfxtp_1.spice
-* Created: Fri Aug 28 11:34:18 2020
+* Created: Wed Sep 2 10:39:30 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/tap/sky130_fd_sc_lp__tap_1.lvs.report b/cells/tap/sky130_fd_sc_lp__tap_1.lvs.report
new file mode 100644
index 0000000..9922586
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_lp__tap_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__tap_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__tap_1.sp ('sky130_fd_sc_lp__tap_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/tap/sky130_fd_sc_lp__tap_1.spice ('sky130_fd_sc_lp__tap_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tap/sky130_fd_sc_lp__tap_2.lvs.report b/cells/tap/sky130_fd_sc_lp__tap_2.lvs.report
new file mode 100644
index 0000000..5ac0d55
--- /dev/null
+++ b/cells/tap/sky130_fd_sc_lp__tap_2.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__tap_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__tap_2.sp ('sky130_fd_sc_lp__tap_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/tap/sky130_fd_sc_lp__tap_2.spice ('sky130_fd_sc_lp__tap_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:37 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd/sky130_fd_sc_lp__tapvgnd_1.lvs.report b/cells/tapvgnd/sky130_fd_sc_lp__tapvgnd_1.lvs.report
new file mode 100644
index 0000000..b651c46
--- /dev/null
+++ b/cells/tapvgnd/sky130_fd_sc_lp__tapvgnd_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__tapvgnd_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__tapvgnd_1.sp ('sky130_fd_sc_lp__tapvgnd_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/tapvgnd/sky130_fd_sc_lp__tapvgnd_1.spice ('sky130_fd_sc_lp__tapvgnd_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:40 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2_1.lvs.report b/cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2_1.lvs.report
new file mode 100644
index 0000000..c9a4adb
--- /dev/null
+++ b/cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__tapvgnd2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__tapvgnd2_1.sp ('sky130_fd_sc_lp__tapvgnd2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/tapvgnd2/sky130_fd_sc_lp__tapvgnd2_1.spice ('sky130_fd_sc_lp__tapvgnd2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:43 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd_1.lvs.report b/cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd_1.lvs.report
new file mode 100644
index 0000000..9241eae
--- /dev/null
+++ b/cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd_1.lvs.report
@@ -0,0 +1,375 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__tapvpwrvgnd_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__tapvpwrvgnd_1.sp ('sky130_fd_sc_lp__tapvpwrvgnd_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/tapvpwrvgnd/sky130_fd_sc_lp__tapvpwrvgnd_1.spice ('sky130_fd_sc_lp__tapvpwrvgnd_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:46 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # # ########################
+ # # # #
+ # # NOT COMPARED #
+ # # # #
+ # # ########################
+
+
+ Error: Nothing in source.
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.lvs.report
new file mode 100644
index 0000000..fa334eb
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_0.sp ('sky130_fd_sc_lp__xnor2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_0.spice ('sky130_fd_sc_lp__xnor2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:49 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_0 sky130_fd_sc_lp__xnor2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pex.spice
index dffee6d..ca0e7da 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_0.pex.spice
-* Created: Fri Aug 28 11:34:50 2020
+* Created: Wed Sep 2 10:39:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pxi.spice
index 70fec8a..a7f2ea8 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_0.pxi.spice
-* Created: Fri Aug 28 11:34:50 2020
+* Created: Wed Sep 2 10:39:54 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_0%A N_A_M1006_g N_A_M1000_g N_A_c_74_n N_A_c_75_n
+ N_A_c_76_n N_A_c_77_n N_A_M1003_g N_A_M1005_g N_A_c_88_n N_A_c_89_n N_A_c_79_n
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.spice
index a050664..d7045dc 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_0.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_0.spice
-* Created: Fri Aug 28 11:34:50 2020
+* Created: Wed Sep 2 10:39:54 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.lvs.report
new file mode 100644
index 0000000..b671845
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_1.sp ('sky130_fd_sc_lp__xnor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_1.spice ('sky130_fd_sc_lp__xnor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:39:57 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_1 sky130_fd_sc_lp__xnor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pex.spice
index 63b6100..b49ed70 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_1.pex.spice
-* Created: Fri Aug 28 11:34:58 2020
+* Created: Wed Sep 2 10:40:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pxi.spice
index 04efec2..3fb283d 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_1.pxi.spice
-* Created: Fri Aug 28 11:34:58 2020
+* Created: Wed Sep 2 10:40:02 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_1%B N_B_M1004_g N_B_M1002_g N_B_M1000_g N_B_M1001_g
+ N_B_c_77_p N_B_c_71_n N_B_c_64_n N_B_c_65_n B B N_B_c_67_n N_B_c_68_n
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.spice
index 9626578..cef011b 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_1.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_1.spice
-* Created: Fri Aug 28 11:34:58 2020
+* Created: Wed Sep 2 10:40:02 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.lvs.report
new file mode 100644
index 0000000..017110a
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_2.sp ('sky130_fd_sc_lp__xnor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_2.spice ('sky130_fd_sc_lp__xnor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:05 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_2 sky130_fd_sc_lp__xnor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pex.spice
index 2c1dd70..282f5d4 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_2.pex.spice
-* Created: Fri Aug 28 11:35:07 2020
+* Created: Wed Sep 2 10:40:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pxi.spice
index d245555..4aea63f 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_2.pxi.spice
-* Created: Fri Aug 28 11:35:07 2020
+* Created: Wed Sep 2 10:40:09 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_2%A N_A_M1007_g N_A_M1014_g N_A_M1019_g N_A_M1011_g
+ N_A_M1000_g N_A_M1010_g N_A_M1008_g N_A_M1009_g N_A_c_117_n N_A_c_118_n
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.spice
index 74f8514..999fea3 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_2.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_2.spice
-* Created: Fri Aug 28 11:35:07 2020
+* Created: Wed Sep 2 10:40:09 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.lvs.report
new file mode 100644
index 0000000..cd379c9
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_4.sp ('sky130_fd_sc_lp__xnor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_4.spice ('sky130_fd_sc_lp__xnor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:13 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_4 sky130_fd_sc_lp__xnor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pex.spice
index 989893f..cebb993 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_4.pex.spice
-* Created: Fri Aug 28 11:35:15 2020
+* Created: Wed Sep 2 10:40:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pxi.spice
index 9d29c0d..df8c3b5 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_4.pxi.spice
-* Created: Fri Aug 28 11:35:15 2020
+* Created: Wed Sep 2 10:40:17 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_4%A N_A_M1019_g N_A_M1006_g N_A_M1031_g N_A_M1017_g
+ N_A_M1024_g N_A_M1036_g N_A_M1037_g N_A_M1027_g N_A_M1018_g N_A_M1008_g
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.spice
index 879b465..2be0479 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_4.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_4.spice
-* Created: Fri Aug 28 11:35:15 2020
+* Created: Wed Sep 2 10:40:17 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.lvs.report
new file mode 100644
index 0000000..d4d65f3
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_lp.sp ('sky130_fd_sc_lp__xnor2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.spice ('sky130_fd_sc_lp__xnor2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:20 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_lp sky130_fd_sc_lp__xnor2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pex.spice
index 5096469..84e35fa 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_lp.pex.spice
-* Created: Fri Aug 28 11:35:23 2020
+* Created: Wed Sep 2 10:40:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pxi.spice
index b9cd027..c496c40 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_lp.pxi.spice
-* Created: Fri Aug 28 11:35:23 2020
+* Created: Wed Sep 2 10:40:24 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_LP%A_82_66# N_A_82_66#_M1008_d N_A_82_66#_M1007_d
+ N_A_82_66#_M1009_g N_A_82_66#_M1000_g N_A_82_66#_c_63_n N_A_82_66#_c_69_n
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.spice
index 58d107b..beb95eb 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_lp.spice
-* Created: Fri Aug 28 11:35:23 2020
+* Created: Wed Sep 2 10:40:24 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.lvs.report b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.lvs.report
new file mode 100644
index 0000000..413fe0f
--- /dev/null
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor2_m.sp ('sky130_fd_sc_lp__xnor2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor2/sky130_fd_sc_lp__xnor2_m.spice ('sky130_fd_sc_lp__xnor2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:28 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor2_m sky130_fd_sc_lp__xnor2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MP (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMN_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MP(PHIGHVT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMN_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR Y VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pex.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pex.spice
index 81ea437..69dd21a 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pex.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_m.pex.spice
-* Created: Fri Aug 28 11:35:31 2020
+* Created: Wed Sep 2 10:40:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pxi.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pxi.spice
index 033e1a5..175fd0e 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pxi.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_m.pxi.spice
-* Created: Fri Aug 28 11:35:31 2020
+* Created: Wed Sep 2 10:40:32 2020
*
x_PM_SKY130_FD_SC_LP__XNOR2_M%A N_A_M1007_g N_A_c_61_n N_A_M1001_g N_A_M1003_g
+ N_A_M1008_g N_A_c_63_n A A A N_A_c_65_n PM_SKY130_FD_SC_LP__XNOR2_M%A
diff --git a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.spice b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.spice
index bd63bf1..4af795e 100644
--- a/cells/xnor2/sky130_fd_sc_lp__xnor2_m.spice
+++ b/cells/xnor2/sky130_fd_sc_lp__xnor2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor2_m.spice
-* Created: Fri Aug 28 11:35:31 2020
+* Created: Wed Sep 2 10:40:32 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.lvs.report b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.lvs.report
new file mode 100644
index 0000000..1503948
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor3_1.sp ('sky130_fd_sc_lp__xnor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor3/sky130_fd_sc_lp__xnor3_1.spice ('sky130_fd_sc_lp__xnor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:36 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor3_1 sky130_fd_sc_lp__xnor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB C B A X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pex.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pex.spice
index edb818d..91d8b45 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_1.pex.spice
-* Created: Fri Aug 28 11:35:40 2020
+* Created: Wed Sep 2 10:40:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pxi.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pxi.spice
index c17c829..2043a94 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_1.pxi.spice
-* Created: Fri Aug 28 11:35:40 2020
+* Created: Wed Sep 2 10:40:41 2020
*
x_PM_SKY130_FD_SC_LP__XNOR3_1%A_81_259# N_A_81_259#_M1010_d N_A_81_259#_M1011_d
+ N_A_81_259#_M1020_g N_A_81_259#_M1019_g N_A_81_259#_c_160_n
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.spice
index e9e5f47..83dc009 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_1.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_1.spice
-* Created: Fri Aug 28 11:35:40 2020
+* Created: Wed Sep 2 10:40:41 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.lvs.report b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.lvs.report
new file mode 100644
index 0000000..6488030
--- /dev/null
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xnor3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xnor3_lp.sp ('sky130_fd_sc_lp__xnor3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.spice ('sky130_fd_sc_lp__xnor3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:44 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xnor3_lp sky130_fd_sc_lp__xnor3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xnor3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__xnor3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 16 16 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pex.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pex.spice
index 7ae6efd..4bb8c17 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pex.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_lp.pex.spice
-* Created: Fri Aug 28 11:35:56 2020
+* Created: Wed Sep 2 10:40:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pxi.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pxi.spice
index d8c312b..05b0b86 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pxi.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_lp.pxi.spice
-* Created: Fri Aug 28 11:35:56 2020
+* Created: Wed Sep 2 10:40:48 2020
*
x_PM_SKY130_FD_SC_LP__XNOR3_LP%A N_A_M1004_g N_A_M1024_g N_A_M1018_g A
+ N_A_c_175_n PM_SKY130_FD_SC_LP__XNOR3_LP%A
diff --git a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.spice b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.spice
index e1c1783..77d316f 100644
--- a/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.spice
+++ b/cells/xnor3/sky130_fd_sc_lp__xnor3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xnor3_lp.spice
-* Created: Fri Aug 28 11:35:56 2020
+* Created: Wed Sep 2 10:40:48 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_0.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_0.lvs.report
new file mode 100644
index 0000000..ac06017
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_0.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_0.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_0.sp ('sky130_fd_sc_lp__xor2_0')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_0.spice ('sky130_fd_sc_lp__xor2_0')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:40:52 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_0 sky130_fd_sc_lp__xor2_0
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_0
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_0
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_0.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_0.pex.spice
index 8abf32c..6e6c060 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_0.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_0.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_0.pex.spice
-* Created: Fri Aug 28 11:36:04 2020
+* Created: Wed Sep 2 10:40:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_0.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_0.pxi.spice
index 107f231..6aa3a44 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_0.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_0.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_0.pxi.spice
-* Created: Fri Aug 28 11:36:04 2020
+* Created: Wed Sep 2 10:40:59 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_0%B N_B_M1001_g N_B_M1009_g N_B_M1006_g N_B_M1005_g
+ N_B_c_74_n N_B_c_75_n N_B_c_76_n B B B B N_B_c_78_n N_B_c_79_n
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_0.spice b/cells/xor2/sky130_fd_sc_lp__xor2_0.spice
index 63962fe..936526b 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_0.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_0.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_0.spice
-* Created: Fri Aug 28 11:36:04 2020
+* Created: Wed Sep 2 10:40:59 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_1.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_1.lvs.report
new file mode 100644
index 0000000..779d72a
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_1.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_1.sp ('sky130_fd_sc_lp__xor2_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_1.spice ('sky130_fd_sc_lp__xor2_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:03 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_1 sky130_fd_sc_lp__xor2_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_1
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB B A VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_1.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_1.pex.spice
index 8a5dcdf..bd3b752 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_1.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_1.pex.spice
-* Created: Fri Aug 28 11:36:13 2020
+* Created: Wed Sep 2 10:41:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_1.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_1.pxi.spice
index 3872fb1..859ae7c 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_1.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_1.pxi.spice
-* Created: Fri Aug 28 11:36:13 2020
+* Created: Wed Sep 2 10:41:07 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_1%B N_B_c_62_n N_B_M1008_g N_B_M1001_g N_B_M1003_g
+ N_B_M1004_g N_B_c_65_n N_B_c_66_n N_B_c_72_n N_B_c_67_n N_B_c_68_n B B
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_1.spice b/cells/xor2/sky130_fd_sc_lp__xor2_1.spice
index 42a0349..e3e8480 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_1.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_1.spice
-* Created: Fri Aug 28 11:36:13 2020
+* Created: Wed Sep 2 10:41:07 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_2.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_2.lvs.report
new file mode 100644
index 0000000..2296abe
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_2.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_2.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_2.sp ('sky130_fd_sc_lp__xor2_2')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_2.spice ('sky130_fd_sc_lp__xor2_2')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:11 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_2 sky130_fd_sc_lp__xor2_2
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_2
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_2
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 10 10 MN (4 pins)
+ 10 10 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 21 20
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 20 layout mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+ 20 source mos transistors were reduced to 10.
+ 10 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_2.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_2.pex.spice
index 74e0d7f..fa710d2 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_2.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_2.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_2.pex.spice
-* Created: Fri Aug 28 11:36:21 2020
+* Created: Wed Sep 2 10:41:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_2.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_2.pxi.spice
index 3b895ef..f3e9b59 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_2.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_2.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_2.pxi.spice
-* Created: Fri Aug 28 11:36:21 2020
+* Created: Wed Sep 2 10:41:15 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_2%A N_A_M1003_g N_A_M1001_g N_A_M1015_g N_A_M1004_g
+ N_A_M1006_g N_A_M1008_g N_A_M1013_g N_A_M1010_g N_A_c_106_n N_A_c_130_p
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_2.spice b/cells/xor2/sky130_fd_sc_lp__xor2_2.spice
index fa8daf7..4aa4deb 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_2.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_2.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_2.spice
-* Created: Fri Aug 28 11:36:21 2020
+* Created: Wed Sep 2 10:41:15 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_4.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_4.lvs.report
new file mode 100644
index 0000000..bc70f26
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_4.lvs.report
@@ -0,0 +1,473 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_4.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_4.sp ('sky130_fd_sc_lp__xor2_4')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_4.spice ('sky130_fd_sc_lp__xor2_4')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:18 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_4 sky130_fd_sc_lp__xor2_4
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_4
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_4
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 20 20 MN (4 pins)
+ 20 20 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 41 40
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+ 40 layout mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+ 40 source mos transistors were reduced to 10.
+ 30 mos transistors were deleted by parallel reduction.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_4.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_4.pex.spice
index d22f773..0ace016 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_4.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_4.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_4.pex.spice
-* Created: Fri Aug 28 11:36:30 2020
+* Created: Wed Sep 2 10:41:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_4.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_4.pxi.spice
index 8597b62..3273c32 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_4.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_4.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_4.pxi.spice
-* Created: Fri Aug 28 11:36:30 2020
+* Created: Wed Sep 2 10:41:22 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_4%A N_A_M1012_g N_A_M1000_g N_A_M1020_g N_A_M1004_g
+ N_A_M1030_g N_A_M1014_g N_A_M1039_g N_A_M1037_g N_A_M1008_g N_A_M1006_g
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_4.spice b/cells/xor2/sky130_fd_sc_lp__xor2_4.spice
index 122b22c..6f7ff6e 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_4.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_4.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_4.spice
-* Created: Fri Aug 28 11:36:30 2020
+* Created: Wed Sep 2 10:41:22 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_lp.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_lp.lvs.report
new file mode 100644
index 0000000..f415eea
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_lp.sp ('sky130_fd_sc_lp__xor2_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_lp.spice ('sky130_fd_sc_lp__xor2_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:26 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_lp sky130_fd_sc_lp__xor2_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 14 14
+
+ Instances: 8 8 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 14 13
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 4 4 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 4 4 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B X VPWR VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_lp.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_lp.pex.spice
index 91afa23..0d93833 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_lp.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_lp.pex.spice
-* Created: Fri Aug 28 11:36:38 2020
+* Created: Wed Sep 2 10:41:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_lp.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_lp.pxi.spice
index 3c4e63c..6f23e8d 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_lp.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_lp.pxi.spice
-* Created: Fri Aug 28 11:36:38 2020
+* Created: Wed Sep 2 10:41:29 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_LP%A_84_93# N_A_84_93#_M1003_d N_A_84_93#_M1010_s
+ N_A_84_93#_M1002_g N_A_84_93#_M1004_g N_A_84_93#_M1012_g N_A_84_93#_c_85_n
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_lp.spice b/cells/xor2/sky130_fd_sc_lp__xor2_lp.spice
index 7c33466..8bd5c0c 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_lp.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_lp.spice
-* Created: Fri Aug 28 11:36:38 2020
+* Created: Wed Sep 2 10:41:29 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_m.lvs.report b/cells/xor2/sky130_fd_sc_lp__xor2_m.lvs.report
new file mode 100644
index 0000000..b50a83c
--- /dev/null
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_m.lvs.report
@@ -0,0 +1,468 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor2_m.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor2_m.sp ('sky130_fd_sc_lp__xor2_m')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor2/sky130_fd_sc_lp__xor2_m.spice ('sky130_fd_sc_lp__xor2_m')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:33 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor2_m sky130_fd_sc_lp__xor2_m
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor2_m
+SOURCE CELL NAME: sky130_fd_sc_lp__xor2_m
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 11 11
+
+ Instances: 5 5 MN (4 pins)
+ 5 5 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 11 10
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 7 7
+
+ Nets: 8 8
+
+ Instances: 3 3 MN (4 pins)
+ 1 1 SMN2 (4 pins)
+ 1 1 SMP2 (4 pins)
+ 1 1 SPMP_2_1 (5 pins)
+ ------ ------
+ Total Inst: 6 6
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 7 7 0 0
+
+ Nets: 8 8 0 0
+
+ Instances: 3 3 0 0 MN(NSHORT)
+ 1 1 0 0 SMN2
+ 1 1 0 0 SMP2
+ 1 1 0 0 SPMP_2_1
+ ------- ------- --------- ---------
+ Total Inst: 6 6 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_m.pex.spice b/cells/xor2/sky130_fd_sc_lp__xor2_m.pex.spice
index a61eaf8..c4d1aa2 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_m.pex.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_m.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_m.pex.spice
-* Created: Fri Aug 28 11:36:46 2020
+* Created: Wed Sep 2 10:41:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_m.pxi.spice b/cells/xor2/sky130_fd_sc_lp__xor2_m.pxi.spice
index 86cad2c..09e365b 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_m.pxi.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_m.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_m.pxi.spice
-* Created: Fri Aug 28 11:36:46 2020
+* Created: Wed Sep 2 10:41:37 2020
*
x_PM_SKY130_FD_SC_LP__XOR2_M%A N_A_c_70_n N_A_M1002_g N_A_M1009_g N_A_M1008_g
+ N_A_c_74_n N_A_M1007_g N_A_c_76_n A A N_A_c_78_n PM_SKY130_FD_SC_LP__XOR2_M%A
diff --git a/cells/xor2/sky130_fd_sc_lp__xor2_m.spice b/cells/xor2/sky130_fd_sc_lp__xor2_m.spice
index 65a53be..5bd814d 100644
--- a/cells/xor2/sky130_fd_sc_lp__xor2_m.spice
+++ b/cells/xor2/sky130_fd_sc_lp__xor2_m.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor2_m.spice
-* Created: Fri Aug 28 11:36:46 2020
+* Created: Wed Sep 2 10:41:37 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_1.lvs.report b/cells/xor3/sky130_fd_sc_lp__xor3_1.lvs.report
new file mode 100644
index 0000000..2560579
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_1.lvs.report
@@ -0,0 +1,464 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor3_1.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor3_1.sp ('sky130_fd_sc_lp__xor3_1')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor3/sky130_fd_sc_lp__xor3_1.spice ('sky130_fd_sc_lp__xor3_1')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:41 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor3_1 sky130_fd_sc_lp__xor3_1
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor3_1
+SOURCE CELL NAME: sky130_fd_sc_lp__xor3_1
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 23 22
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 11 11 MN (4 pins)
+ 11 11 MP (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 11 11 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_1.pex.spice b/cells/xor3/sky130_fd_sc_lp__xor3_1.pex.spice
index 08d445f..d7599eb 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_1.pex.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_1.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_1.pex.spice
-* Created: Fri Aug 28 11:37:03 2020
+* Created: Wed Sep 2 10:41:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_1.pxi.spice b/cells/xor3/sky130_fd_sc_lp__xor3_1.pxi.spice
index 11ba4ab..9e2c348 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_1.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_1.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_1.pxi.spice
-* Created: Fri Aug 28 11:37:03 2020
+* Created: Wed Sep 2 10:41:45 2020
*
x_PM_SKY130_FD_SC_LP__XOR3_1%A_86_305# N_A_86_305#_M1004_d N_A_86_305#_M1021_d
+ N_A_86_305#_M1016_d N_A_86_305#_M1019_d N_A_86_305#_M1000_g
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_1.spice b/cells/xor3/sky130_fd_sc_lp__xor3_1.spice
index 60a492c..2259b51 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_1.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_1.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_1.spice
-* Created: Fri Aug 28 11:37:03 2020
+* Created: Wed Sep 2 10:41:45 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_lp.lvs.report b/cells/xor3/sky130_fd_sc_lp__xor3_lp.lvs.report
new file mode 100644
index 0000000..fd03adb
--- /dev/null
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_lp.lvs.report
@@ -0,0 +1,466 @@
+
+
+
+ ##################################################
+ ## ##
+ ## C A L I B R E S Y S T E M ##
+ ## ##
+ ## L V S R E P O R T ##
+ ## ##
+ ##################################################
+
+
+
+REPORT FILE NAME: sky130_fd_sc_lp__xor3_lp.lvs.report
+LAYOUT NAME: svdb/sky130_fd_sc_lp__xor3_lp.sp ('sky130_fd_sc_lp__xor3_lp')
+SOURCE NAME: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./../../sky130_fd_sc_lp/cells/xor3/sky130_fd_sc_lp__xor3_lp.spice ('sky130_fd_sc_lp__xor3_lp')
+RULE FILE: /home/hlusk/repos/SkyWater/osugooglelib/calibre/./_xrcControlFile_s8_
+CREATION TIME: Wed Sep 2 10:41:48 2020
+CURRENT DIRECTORY: /home/hlusk/repos/SkyWater/osugooglelib/calibre
+USER NAME: hlusk
+CALIBRE VERSION: v2018.4_34.26 Mon Dec 3 14:40:54 PST 2018
+
+
+
+ OVERALL COMPARISON RESULTS
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+
+**************************************************************************************************************
+ CELL SUMMARY
+**************************************************************************************************************
+
+ Result Layout Source
+ ----------- ----------- --------------
+ CORRECT sky130_fd_sc_lp__xor3_lp sky130_fd_sc_lp__xor3_lp
+
+
+
+**************************************************************************************************************
+ LVS PARAMETERS
+**************************************************************************************************************
+
+
+o LVS Setup:
+
+ // LVS COMPONENT TYPE PROPERTY
+ // LVS COMPONENT SUBTYPE PROPERTY
+ // LVS PIN NAME PROPERTY
+ // LVS POWER NAME
+ // LVS GROUND NAME
+ LVS CELL SUPPLY NO
+ LVS RECOGNIZE GATES ALL
+ LVS IGNORE PORTS NO
+ LVS CHECK PORT NAMES YES
+ LVS IGNORE TRIVIAL NAMED PORTS NO
+ LVS BUILTIN DEVICE PIN SWAP YES
+ LVS ALL CAPACITOR PINS SWAPPABLE NO
+ LVS DISCARD PINS BY DEVICE YES
+ LVS SOFT SUBSTRATE PINS NO
+ LVS INJECT LOGIC NO
+ LVS EXPAND UNBALANCED CELLS YES
+ LVS FLATTEN INSIDE CELL NO
+ LVS EXPAND SEED PROMOTIONS NO
+ LVS PRESERVE PARAMETERIZED CELLS NO
+ LVS GLOBALS ARE PORTS YES
+ LVS REVERSE WL NO
+ LVS SPICE PREFER PINS YES
+ LVS SPICE SLASH IS SPACE NO
+ LVS SPICE ALLOW FLOATING PINS YES
+ LVS SPICE ALLOW INLINE PARAMETERS NO
+ LVS SPICE ALLOW UNQUOTED STRINGS YES
+ LVS SPICE CONDITIONAL LDD NO
+ LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
+ // LVS SPICE EXCLUDE CELL SOURCE
+ // LVS SPICE EXCLUDE CELL LAYOUT
+ LVS SPICE IMPLIED MOS AREA NO
+ // LVS SPICE MULTIPLIER NAME
+ LVS SPICE OVERRIDE GLOBALS YES
+ LVS SPICE REDEFINE PARAM YES
+ LVS SPICE REPLICATE DEVICES YES
+ LVS SPICE SCALE X PARAMETERS NO
+ LVS SPICE STRICT WL YES
+ // LVS SPICE OPTION
+ LVS STRICT SUBTYPES YES
+ LVS EXACT SUBTYPES NO
+ LAYOUT CASE NO
+ SOURCE CASE NO
+ LVS COMPARE CASE NO
+ LVS DOWNCASE DEVICE NO
+ LVS REPORT MAXIMUM 50
+ LVS PROPERTY RESOLUTION MAXIMUM ALL
+ LVS SIGNATURE MAXIMUM ALL
+ // LVS FILTER UNUSED OPTION
+ // LVS REPORT OPTION
+ LVS REPORT UNITS YES
+ // LVS NON USER NAME PORT
+ LVS NON USER NAME NET "^n[0-9]*$" "^net[0-9]*$"
+ // LVS NON USER NAME INSTANCE
+ // LVS IGNORE DEVICE PIN
+ // LVS PREFER NETS FILTER SOURCE
+ // LVS PREFER NETS FILTER LAYOUT
+
+ // Device Type Map
+
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p35" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_0p69" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_1p41" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xhrpoly_2p85" SOURCE LAYOUT
+ LVS DEVICE TYPE RESISTOR "xuhrpoly_2p85" SOURCE LAYOUT
+
+ // Reduction
+
+ LVS REDUCE SERIES MOS NO
+ LVS REDUCE PARALLEL MOS NO
+ LVS REDUCE SEMI SERIES MOS NO
+ LVS REDUCE SPLIT GATES YES [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE PARALLEL BIPOLAR NO
+ LVS REDUCE SERIES CAPACITORS NO
+ LVS REDUCE PARALLEL CAPACITORS NO
+ LVS REDUCE SERIES RESISTORS NO
+ LVS REDUCE PARALLEL RESISTORS NO
+ LVS REDUCE PARALLEL DIODES NO
+
+ LVS REDUCE condiode PARALLEL
+ LVS REDUCE condiodeHvPsub PARALLEL
+ LVS REDUCE p20vhv1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE n20vhviso1 PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE nvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE pvhv PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MP PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE M PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE MN PARALLEL [ TOLERANCE l 1 w 1 ]
+ LVS REDUCE Q(npnpar1x1) PARALLEL
+ LVS REDUCE Q(npnpar1x2) PARALLEL
+ LVS REDUCE Q(npn_1x1_2p0_hv) PARALLEL
+ LVS REDUCE Q(pnppar) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE Q(pnppar5x) PARALLEL [ TOLERANCE bArea 1 bPeri 1 eArea 1 ePeri 1 ]
+ LVS REDUCE D PARALLEL [ TOLERANCE a 1 p 1 ]
+ LVS REDUCE D SERIES POS NEG NO
+ LVS REDUCE C(xcmimc1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE C(xcmimc2) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R(mrp1) PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R PARALLEL [ TOLERANCE w 1 l 1 ]
+ LVS REDUCE R SERIES POS NEG NO
+ LVS REDUCE R(short) PARALLEL
+ LVS REDUCE R(short) SERIES POS NEG NO
+ LVS REDUCE R(fuse) PARALLEL NO
+ LVS REDUCE R(fuse) SERIES POS NEG NO
+ LVS REDUCE R(metop) PARALLEL [ TOLERANCE metopNumber 0 ]
+ LVS REDUCE R(metop) SERIES POS NEG NO
+ LVS REDUCTION PRIORITY PARALLEL
+
+ LVS SHORT EQUIVALENT NODES NO
+
+ // Filter
+
+ LVS FILTER R(cds_thru) SHORT SOURCE
+ LVS FILTER R(cds_thru) SHORT LAYOUT
+ LVS FILTER Dpar OPEN SOURCE
+ LVS FILTER Dpar OPEN LAYOUT
+ LVS FILTER Probe OPEN SOURCE
+ LVS FILTER Probe OPEN LAYOUT
+ LVS FILTER icecap OPEN SOURCE
+ LVS FILTER s8fmlt_iref_termx OPEN SOURCE
+ LVS FILTER s8fmlt_neg_termx OPEN SOURCE
+ LVS FILTER s8fmlt_termx OPEN SOURCE
+ LVS FILTER s8fmlt_vdac_termx OPEN SOURCE
+ LVS FILTER D OPEN SOURCE
+ LVS FILTER diff_dev OPEN SOURCE
+ LVS FILTER diff_dev OPEN LAYOUT
+ LVS FILTER tap_dev OPEN SOURCE
+ LVS FILTER tap_dev OPEN LAYOUT
+ LVS FILTER cad_dummy_open_device OPEN SOURCE
+ LVS FILTER cad_dummy_open_device OPEN LAYOUT
+
+ // Trace Property
+
+ TRACE PROPERTY xcnwvc m m 0
+ TRACE PROPERTY xcnwvc w w 0
+ TRACE PROPERTY xcnwvc l l 0
+ TRACE PROPERTY xcnwvc2 m m 0
+ TRACE PROPERTY xcnwvc2 w w 0
+ TRACE PROPERTY xcnwvc2 l l 0
+ TRACE PROPERTY xchvnwc m m 0
+ TRACE PROPERTY q(npnpar1x1) m m 0
+ TRACE PROPERTY q(npnpar1x2) m m 0
+ TRACE PROPERTY q(npn_1x1_2p0_hv) m m 0
+ TRACE PROPERTY q(pnppar) barea barea 0
+ TRACE PROPERTY q(pnppar) bperi bperi 0
+ TRACE PROPERTY q(pnppar) earea earea 0
+ TRACE PROPERTY q(pnppar) eperi eperi 0
+ TRACE PROPERTY q(pnppar) m m 0
+ TRACE PROPERTY q(pnppar5x) barea barea 0
+ TRACE PROPERTY q(pnppar5x) bperi bperi 0
+ TRACE PROPERTY q(pnppar5x) earea earea 0
+ TRACE PROPERTY q(pnppar5x) eperi eperi 0
+ TRACE PROPERTY q(pnppar5x) m m 0
+ TRACE PROPERTY d(ndiode) a a 1
+ TRACE PROPERTY d(ndiode) p p 1
+ TRACE PROPERTY d(ndiode) m m 0
+ TRACE PROPERTY d(ndiode_h) a a 1
+ TRACE PROPERTY d(ndiode_h) p p 1
+ TRACE PROPERTY d(ndiode_h) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_300) m m 0
+ TRACE PROPERTY d(pdiode) a a 1
+ TRACE PROPERTY d(pdiode) p p 1
+ TRACE PROPERTY d(pdiode) m m 0
+ TRACE PROPERTY d(pdiode_h) a a 1
+ TRACE PROPERTY d(pdiode_h) p p 1
+ TRACE PROPERTY d(pdiode_h) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_100) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_100) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_200) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_200) m m 0
+ TRACE PROPERTY d(xesd_pdiode_h_300) a a 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) p p 1
+ TRACE PROPERTY d(xesd_pdiode_h_300) m m 0
+ TRACE PROPERTY d(dnwdiode_psub) a a 1
+ TRACE PROPERTY d(dnwdiode_psub) p p 1
+ TRACE PROPERTY d(dnwdiode_psub) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_100) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_200) m m 0
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) a a 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) p p 1
+ TRACE PROPERTY d(xesd_ndiode_h_dnwl_300) m m 0
+ TRACE PROPERTY xcmvpp m m 0
+ TRACE PROPERTY xcmvpp_2 m m 0
+ TRACE PROPERTY xcmvpp2_nhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp2_phv5x4 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap2_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_wafflecap1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l40 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l20 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l10 m m 0
+ TRACE PROPERTY xcmvpp_hd5_atlas_fingercap_l5 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1_met5pullin m m 0
+ TRACE PROPERTY xcmvpp_hd5_5x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_4x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_3x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_2x1 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x2 m m 0
+ TRACE PROPERTY xcmvpp_hd5_1x1 m m 0
+ TRACE PROPERTY xcmvppx4_2xnhvnative10x4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym50p4shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_lim5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m5shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_lim4shield m m 0
+ TRACE PROPERTY xcmvpp6p8x6p1_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_polym4shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m4shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3_lishield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m3shield m m 0
+ TRACE PROPERTY xcmvpp8p6x7p9_m3shield m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m3shield m m 0
+ TRACE PROPERTY xcmvpp1p8x1p8_m3shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4m5shield m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m4 m m 0
+ TRACE PROPERTY xcmvpp11p5x11p7_m1m2 m m 0
+ TRACE PROPERTY xcmvpp4p4x4p6_m1m2 m m 0
+ TRACE PROPERTY xcmvpp5 m m 0
+ TRACE PROPERTY xcmvpp4 m m 0
+ TRACE PROPERTY xcmvpp3 m m 0
+ TRACE PROPERTY r(mrdn) w w 1
+ TRACE PROPERTY r(mrdn) l l 1
+ TRACE PROPERTY r(mrdn) m m 0
+ TRACE PROPERTY r(mrdn_hv) w w 1
+ TRACE PROPERTY r(mrdn_hv) l l 1
+ TRACE PROPERTY r(mrdn_hv) m m 0
+ TRACE PROPERTY r(mrdp) w w 1
+ TRACE PROPERTY r(mrdp) l l 1
+ TRACE PROPERTY r(mrdp) m m 0
+ TRACE PROPERTY r(mrdp_hv) w w 1
+ TRACE PROPERTY r(mrdp_hv) l l 1
+ TRACE PROPERTY r(mrdp_hv) m m 0
+ TRACE PROPERTY r(mrl1) w w 1
+ TRACE PROPERTY r(mrl1) l l 1
+ TRACE PROPERTY r(mrl1) m m 0
+ TRACE PROPERTY r(xpwres) w w 1
+ TRACE PROPERTY r(xpwres) l l 1
+ TRACE PROPERTY r(xpwres) m m 0
+ TRACE PROPERTY r(short) m m 0
+ TRACE PROPERTY r(fuse) w w 1
+ TRACE PROPERTY r(fuse) l l 1
+ TRACE PROPERTY r(fuse) m m 0
+ TRACE PROPERTY r(metop) metopnumber metopnumber 0
+ TRACE PROPERTY d(dnwdiode_psub_victim) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_victim) m m 0
+ TRACE PROPERTY d(nwdiode_victim) a a 10
+ TRACE PROPERTY d(nwdiode_victim) p p 10
+ TRACE PROPERTY d(nwdiode_victim) m m 0
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) a a 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) p p 10
+ TRACE PROPERTY d(dnwdiode_psub_aggressor) m m 0
+ TRACE PROPERTY d(nwdiode_aggressor) a a 10
+ TRACE PROPERTY d(nwdiode_aggressor) p p 10
+ TRACE PROPERTY d(nwdiode_aggressor) m m 0
+
+ // User Trace Property
+
+ TRACE PROPERTY mn(nshort) m mult w l
+ TRACE PROPERTY mn(npass) m mult w l
+ TRACE PROPERTY mn(nlowvt) m mult w l
+ TRACE PROPERTY m(sonos_e) m mult w l
+ TRACE PROPERTY m m mult w l
+ TRACE PROPERTY m(fnpass) m mult w l
+ TRACE PROPERTY mn(nhv) m mult w l
+ TRACE PROPERTY mn(nhvnative) m mult w l
+ TRACE PROPERTY mn(ntvnative) m mult w l
+ TRACE PROPERTY mp(pshort) m mult w l
+ TRACE PROPERTY mp m mult w l
+ TRACE PROPERTY mp(phighvt) m mult w l
+ TRACE PROPERTY mp(plowvt) m mult w l
+ TRACE PROPERTY mp(phv) m mult w l
+ TRACE PROPERTY mn(nshortesd) m mult w l
+ TRACE PROPERTY mn(nhvesd) m mult w l
+ TRACE PROPERTY mn(nhvnativeesd) m mult w l
+ TRACE PROPERTY mp(phvesd) m mult w l
+ TRACE PROPERTY nvhv m mult w l
+ TRACE PROPERTY n20vhv1 m mult w l
+ TRACE PROPERTY n20nativevhv1 m mult w l
+ TRACE PROPERTY n20vhviso1 m mult w l
+ TRACE PROPERTY n20nativevhviso1 m mult w l
+ TRACE PROPERTY pvhv m mult w l
+ TRACE PROPERTY p20vhv1 m mult w l
+ TRACE PROPERTY c(xcmimc1) w l m
+ TRACE PROPERTY c(xcmimc2) w l m
+ TRACE PROPERTY r(mrp1) m w l
+ TRACE PROPERTY xhrpoly_0p35 m w l
+ TRACE PROPERTY xuhrpoly_0p35 m w l
+ TRACE PROPERTY xhrpoly_0p69 m w l
+ TRACE PROPERTY xuhrpoly_0p69 m w l
+ TRACE PROPERTY xhrpoly_1p41 m w l
+ TRACE PROPERTY xuhrpoly_1p41 m w l
+ TRACE PROPERTY xhrpoly_2p85 m w l
+ TRACE PROPERTY xuhrpoly_2p85 m w l
+
+
+
+ CELL COMPARISON RESULTS ( TOP LEVEL )
+
+
+
+ # ################### _ _
+ # # # * *
+ # # # CORRECT # |
+ # # # # \___/
+ # ###################
+
+
+
+LAYOUT CELL NAME: sky130_fd_sc_lp__xor3_lp
+SOURCE CELL NAME: sky130_fd_sc_lp__xor3_lp
+
+--------------------------------------------------------------------------------------------------------------
+
+INITIAL NUMBERS OF OBJECTS
+--------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 20 20
+
+ Instances: 16 16 MN (4 pins)
+ 11 11 MP (4 pins)
+ 1 0 * Dpar (2 pins)
+ ------ ------
+ Total Inst: 28 27
+
+
+NUMBERS OF OBJECTS AFTER TRANSFORMATION
+---------------------------------------
+
+ Layout Source Component Type
+ ------ ------ --------------
+ Ports: 8 8
+
+ Nets: 15 15
+
+ Instances: 6 6 MN (4 pins)
+ 11 11 MP (4 pins)
+ 5 5 SMN2 (4 pins)
+ ------ ------
+ Total Inst: 22 22
+
+
+ * = Number of objects in layout different from number in source.
+
+
+
+**************************************************************************************************************
+ INFORMATION AND WARNINGS
+**************************************************************************************************************
+
+
+ Matched Matched Unmatched Unmatched Component
+ Layout Source Layout Source Type
+ ------- ------- --------- --------- ---------
+ Ports: 8 8 0 0
+
+ Nets: 15 15 0 0
+
+ Instances: 6 6 0 0 MN(NSHORT)
+ 11 11 0 0 MP(PHIGHVT)
+ 5 5 0 0 SMN2
+ ------- ------- --------- ---------
+ Total Inst: 22 22 0 0
+
+
+o Statistics:
+
+ 1 layout instance was filtered and its pins removed from adjoining nets.
+
+
+o Initial Correspondence Points:
+
+ Ports: VNB VPB A B C VPWR X VGND
+
+
+**************************************************************************************************************
+ SUMMARY
+**************************************************************************************************************
+
+Total CPU Time: 0 sec
+Total Elapsed Time: 0 sec
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_lp.pex.spice b/cells/xor3/sky130_fd_sc_lp__xor3_lp.pex.spice
index 189d64d..b4132b7 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_lp.pex.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_lp.pex.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_lp.pex.spice
-* Created: Fri Aug 28 11:37:11 2020
+* Created: Wed Sep 2 10:41:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
* Nominal Temperature: 27C
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_lp.pxi.spice b/cells/xor3/sky130_fd_sc_lp__xor3_lp.pxi.spice
index 3d856f7..589a192 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_lp.pxi.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_lp.pxi.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_lp.pxi.spice
-* Created: Fri Aug 28 11:37:11 2020
+* Created: Wed Sep 2 10:41:52 2020
*
x_PM_SKY130_FD_SC_LP__XOR3_LP%A N_A_M1002_g N_A_M1023_g N_A_M1025_g A
+ N_A_c_194_n N_A_c_195_n PM_SKY130_FD_SC_LP__XOR3_LP%A
diff --git a/cells/xor3/sky130_fd_sc_lp__xor3_lp.spice b/cells/xor3/sky130_fd_sc_lp__xor3_lp.spice
index 2ed4533..9e418f6 100644
--- a/cells/xor3/sky130_fd_sc_lp__xor3_lp.spice
+++ b/cells/xor3/sky130_fd_sc_lp__xor3_lp.spice
@@ -1,5 +1,5 @@
* File: sky130_fd_sc_lp__xor3_lp.spice
-* Created: Fri Aug 28 11:37:11 2020
+* Created: Wed Sep 2 10:41:52 2020
* Program "Calibre xRC"
* Version "v2018.4_34.26"
*
